diff --git a/src/axi_burst_splitter.sv b/src/axi_burst_splitter.sv
index a46ce2c5e..4fe6f7e78 100644
--- a/src/axi_burst_splitter.sv
+++ b/src/axi_burst_splitter.sv
@@ -78,7 +78,6 @@ module axi_burst_splitter #(
     .NoMstPorts   ( 2           ),
     .MaxTrans     ( MaxTxns     ),
     .AxiLookBits  ( IdWidth     ),
-    .FallThrough  ( 1'b1        ),
     .SpillAw      ( 1'b0        ),
     .SpillW       ( 1'b0        ),
     .SpillB       ( 1'b0        ),
diff --git a/src/axi_demux.sv b/src/axi_demux.sv
index 37e2d5912..4ab4aadcf 100644
--- a/src/axi_demux.sv
+++ b/src/axi_demux.sv
@@ -51,7 +51,6 @@ module axi_demux #(
   parameter int unsigned MaxTrans       = 32'd8,
   parameter int unsigned AxiLookBits    = 32'd3,
   parameter bit          UniqueIds      = 1'b0,
-  parameter bit          FallThrough    = 1'b0,
   parameter bit          SpillAw        = 1'b1,
   parameter bit          SpillW         = 1'b0,
   parameter bit          SpillB         = 1'b0,
@@ -870,7 +869,6 @@ module axi_demux_intf #(
     .MaxTrans       ( MAX_TRANS     ),
     .AxiLookBits    ( AXI_LOOK_BITS ),
     .UniqueIds      ( UNIQUE_IDS    ),
-    .FallThrough    ( FALL_THROUGH  ),
     .SpillAw        ( SPILL_AW      ),
     .SpillW         ( SPILL_W       ),
     .SpillB         ( SPILL_B       ),
diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv
index 8688cb355..df21c8b1d 100644
--- a/src/axi_id_serialize.sv
+++ b/src/axi_id_serialize.sv
@@ -160,7 +160,6 @@ module axi_id_serialize #(
     .NoMstPorts  ( AxiMstPortMaxUniqIds ),
     .MaxTrans    ( AxiSlvPortMaxTxns    ),
     .AxiLookBits ( AxiSlvPortIdWidth    ),
-    .FallThrough ( 1'b1                 ),
     .SpillAw     ( 1'b1                 ),
     .SpillW      ( 1'b0                 ),
     .SpillB      ( 1'b0                 ),
diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv
index da6bbc8bc..57c2529a0 100644
--- a/src/axi_isolate.sv
+++ b/src/axi_isolate.sv
@@ -107,7 +107,6 @@ module axi_isolate #(
       // We don't need many bits here as the common case will be to go for the pass-through.
       .AxiLookBits    ( 1           ),
       .UniqueIds      ( 1'b0        ),
-      .FallThrough    ( 1'b1        ),
       .SpillAw        ( 1'b0        ),
       .SpillW         ( 1'b0        ),
       .SpillB         ( 1'b0        ),
diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv
index e50383d02..cc7c6198d 100644
--- a/src/axi_to_mem_banked.sv
+++ b/src/axi_to_mem_banked.sv
@@ -151,7 +151,6 @@ module axi_to_mem_banked #(
     .MaxTrans    ( MemLatency+2  ), // allow multiple Ax vectors to not starve W channel
     .AxiLookBits ( 32'd1         ), // select is fixed, do not need it
     .UniqueIds   ( 1'b0          ),
-    .FallThrough ( 1'b1          ),
     .SpillAw     ( 1'b1          ),
     .SpillW      ( 1'b1          ),
     .SpillB      ( 1'b1          ),
diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv
index 764084619..0971ef6f5 100644
--- a/src/axi_xbar.sv
+++ b/src/axi_xbar.sv
@@ -164,7 +164,6 @@ import cf_math_pkg::idx_width;
       .MaxTrans       ( Cfg.MaxMstTrans        ),
       .AxiLookBits    ( Cfg.AxiIdUsedSlvPorts  ),
       .UniqueIds      ( Cfg.UniqueIds          ),
-      .FallThrough    ( Cfg.FallThrough        ),
       .SpillAw        ( Cfg.LatencyMode[9]     ),
       .SpillW         ( Cfg.LatencyMode[8]     ),
       .SpillB         ( Cfg.LatencyMode[7]     ),