- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-
-#include QMK_KEYBOARD_H
-#include "rgblite.h"
-
-// Defines names for use in layer keycodes and the keymap
-enum layer_names {
- _BASE,
- _FUNC,
-};
-
-// set your keycodes here
-#define layer1_left KC_PAUS
-#define layer1_right KC_MPLY
-#define layer2_left KC_MPRV
-#define layer2_right KC_MNXT
-
-
-enum custom_keycodes {
- LEFT1 = SAFE_RANGE,
- RIGHT1,
- LEFT2,
- RIGHT2
-};
-
-const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
- [_BASE] = LAYOUT(
- LEFT1, RIGHT1
- ),
- [_FUNC] = LAYOUT(
- LEFT2, RIGHT2
- )
-};
-
-static bool key1_down = false;
-static bool key2_down = false;
-static char layer_switched = 0; // this prevents the individual keys getting triggered after a layerchange
-
-bool process_record_user(uint16_t keycode, keyrecord_t *record)
-{
- switch (keycode)
- {
- case LEFT1:
- if (record->event.pressed)
- {
- if (key2_down)
- {
- layer_on(1);
- layer_switched = 2;
- return false;
- break;
- }
- key1_down = true;
- }
- else {
- if (layer_switched > 0) {
- --layer_switched;
- key1_down = false;
- }
- else {
- tap_code(layer1_left);
- key1_down = false;
- }
- }
- return false;
- break;
- case RIGHT1:
- if (record->event.pressed)
- {
- if (key1_down)
- {
- layer_on(1);
- layer_switched = 2;
- return false;
- break;
- }
- key2_down = true;
- }
- else {
- if (layer_switched > 0) {
- --layer_switched;
- key2_down = false;
- }
- else {
- tap_code(layer1_right);
- key2_down = false;
- }
- }
- return false;
- break;
- case LEFT2:
- if (record->event.pressed)
- {
- if (key2_down)
- {
- layer_off(1);
- layer_switched = 2;
- return false;
- break;
- }
- key1_down = true;
- }
- else {
- if (layer_switched > 0) {
- --layer_switched;
- key1_down = false;
- }
- else {
- tap_code(layer2_left);
- key1_down = false;
- }
- }
- return false;
- break;
- case RIGHT2:
- if (record->event.pressed)
- {
- if (key1_down)
- {
- layer_off(1);
- layer_switched = 2;
- return false;
- break;
- }
- key2_down = true;
- }
- else {
- if (layer_switched > 0) {
- --layer_switched;
- key2_down = false;
- }
- else {
- tap_code(layer2_right);
- key2_down = false;
- }
- }
- return false;
- break;
- }
- return true;
-};
-
-// layer colors
-layer_state_t layer_state_set_user(layer_state_t state) {
- switch (get_highest_layer(state)) {
- case _FUNC:
- rgblite_setrgb(RGB_RED);
- break;
- default: // for any other layers, or the default layer
- rgblite_setrgb(RGB_GREEN);
- break;
- }
- return state;
-}
-
-// default color
-void keyboard_post_init_user(void) {
- rgblite_init();
- rgblite_setrgb(RGB_GREEN);
-}
diff --git a/keyboards/xiudi/xd002/keymaps/multilayer_rgb/rgblite.h b/keyboards/xiudi/xd002/keymaps/multilayer_rgb/rgblite.h
deleted file mode 100644
index 103b228d33b6..000000000000
--- a/keyboards/xiudi/xd002/keymaps/multilayer_rgb/rgblite.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#pragma once
-
-#include "ws2812.h"
-#include "color.h"
-
-static inline void rgblite_init(void) {
- ws2812_init();
-}
-
-static inline void rgblite_setrgb(uint8_t _r, uint8_t _g, uint8_t _b) {
- rgb_led_t leds[RGBLIGHT_LED_COUNT] = {{.r = _r, .g = _g, .b = _b}, {.r = _r, .g = _g, .b = _b}};
- ws2812_setleds(leds, RGBLIGHT_LED_COUNT);
-}
diff --git a/keyboards/xiudi/xd002/keymaps/multilayer_rgb/rules.mk b/keyboards/xiudi/xd002/keymaps/multilayer_rgb/rules.mk
deleted file mode 100644
index 07c75adb4707..000000000000
--- a/keyboards/xiudi/xd002/keymaps/multilayer_rgb/rules.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-WS2812_DRIVER_REQUIRED = yes
-EXTRAKEY_ENABLE = yes
diff --git a/keyboards/xiudi/xd002/keymaps/rgb_lite/config.h b/keyboards/xiudi/xd002/keymaps/rgb_lite/config.h
new file mode 100644
index 000000000000..bb9f2fc153d8
--- /dev/null
+++ b/keyboards/xiudi/xd002/keymaps/rgb_lite/config.h
@@ -0,0 +1,3 @@
+#pragma once
+
+#define WS2812_LED_COUNT 2
diff --git a/keyboards/xiudi/xd002/keymaps/rgb_lite/keymap.c b/keyboards/xiudi/xd002/keymaps/rgb_lite/keymap.c
index aac4dc6fde1f..96595b1e2f51 100644
--- a/keyboards/xiudi/xd002/keymaps/rgb_lite/keymap.c
+++ b/keyboards/xiudi/xd002/keymaps/rgb_lite/keymap.c
@@ -8,14 +8,14 @@ enum custom_keycodes {
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[0] = LAYOUT(
- RGB_HUI, QMKURL
+ UG_HUEU, QMKURL
)
};
bool process_record_user(uint16_t keycode, keyrecord_t *record) {
if (record->event.pressed) {
switch (keycode) {
- case RGB_HUI:
+ case QK_UNDERGLOW_HUE_UP:
rgblite_increase_hue();
break;
case QMKURL:
diff --git a/keyboards/xiudi/xd002/keymaps/rgb_lite/rgblite.h b/keyboards/xiudi/xd002/keymaps/rgb_lite/rgblite.h
index 0bb0582415ce..3ee8c44b87d0 100644
--- a/keyboards/xiudi/xd002/keymaps/rgb_lite/rgblite.h
+++ b/keyboards/xiudi/xd002/keymaps/rgb_lite/rgblite.h
@@ -7,9 +7,9 @@ static inline void rgblite_init(void) {
ws2812_init();
}
-static inline void rgblite_setrgb(uint8_t _r, uint8_t _g, uint8_t _b) {
- rgb_led_t leds[RGBLIGHT_LED_COUNT] = {{.r = _r, .g = _g, .b = _b}, {.r = _r, .g = _g, .b = _b}};
- ws2812_setleds(leds, RGBLIGHT_LED_COUNT);
+static inline void rgblite_setrgb(uint8_t r, uint8_t g, uint8_t b) {
+ ws2812_set_color_all(r, g, b);
+ ws2812_flush();
}
static void rgblite_increase_hue(void) {
diff --git a/keyboards/xiudi/xd60/keymaps/crd_ansi/keymap.c b/keyboards/xiudi/xd60/keymaps/crd_ansi/keymap.c
index a5be75c180b9..9cd135176cc2 100644
--- a/keyboards/xiudi/xd60/keymaps/crd_ansi/keymap.c
+++ b/keyboards/xiudi/xd60/keymaps/crd_ansi/keymap.c
@@ -23,8 +23,8 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[_FL] = LAYOUT_60_ansi(
KC_ESC, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL,
_______, KC_HOME, KC_UP, KC_END, _______, _______, _______, _______, KC_MUTE, _______, _______, KC_PGDN, KC_PGUP, QK_BOOT,
- _______, KC_LEFT, KC_DOWN, KC_RGHT, _______, _______, KC_SCRL, KC_VOLD, KC_VOLU, KC_PAUS, _______, _______, RGB_TOG,
- _______, _______, _______, _______, _______, _______, _______, _______, RGB_VAD, RGB_VAI, RGB_MOD, _______,
+ _______, KC_LEFT, KC_DOWN, KC_RGHT, _______, _______, KC_SCRL, KC_VOLD, KC_VOLU, KC_PAUS, _______, _______, UG_TOGG,
+ _______, _______, _______, _______, _______, _______, _______, _______, UG_VALD, UG_VALU, UG_NEXT, _______,
_______, _______, _______, _______, _______, _______, _______, _______
)
};
diff --git a/keyboards/yandrstudio/nz64/keymaps/default/keymap.c b/keyboards/yandrstudio/nz64/keymaps/default/keymap.c
index 9283a3f97513..26f9a0c748dd 100644
--- a/keyboards/yandrstudio/nz64/keymaps/default/keymap.c
+++ b/keyboards/yandrstudio/nz64/keymaps/default/keymap.c
@@ -26,7 +26,7 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[1] = LAYOUT(
KC_GRV , KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL,
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
- KC_TRNS, URGB_K, RGB_HUI, RGB_HUD, RGB_SAI, RGB_SAD, KC_TRNS, KC_TRNS, KC_TRNS, GU_TOGG, KC_TRNS, KC_TRNS, KC_TRNS,
- KC_TRNS, RGB_TOG, RGB_MOD, RGB_RMOD,RGB_VAI, RGB_VAD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
+ KC_TRNS, URGB_K, RM_HUEU, RM_HUED, RM_SATU, RM_SATD, KC_TRNS, KC_TRNS, KC_TRNS, GU_TOGG, KC_TRNS, KC_TRNS, KC_TRNS,
+ KC_TRNS, RM_TOGG, RM_NEXT, RM_PREV, RM_VALU, RM_VALD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS)
};
diff --git a/keyboards/yandrstudio/nz67v2/keymaps/default/keymap.c b/keyboards/yandrstudio/nz67v2/keymaps/default/keymap.c
index 522b8d1043d3..01d3781d4ff8 100644
--- a/keyboards/yandrstudio/nz67v2/keymaps/default/keymap.c
+++ b/keyboards/yandrstudio/nz67v2/keymaps/default/keymap.c
@@ -26,7 +26,7 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[1] = LAYOUT_all(
KC_GRV, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL, KC_TRNS,
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
- KC_TRNS, URGB_K, RGB_HUI, RGB_HUD, RGB_SAI, RGB_SAD, KC_TRNS, KC_TRNS, KC_TRNS, GU_TOGG, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
- KC_TRNS, RGB_TOG, RGB_MOD, RGB_RMOD, RGB_VAI, RGB_VAD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
+ KC_TRNS, URGB_K, RM_HUEU, RM_HUED, RM_SATU, RM_SATD, KC_TRNS, KC_TRNS, KC_TRNS, GU_TOGG, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
+ KC_TRNS, RM_TOGG, RM_NEXT, RM_PREV, RM_VALU, RM_VALD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS)
};
diff --git a/keyboards/yandrstudio/tg67/keymaps/default/keymap.c b/keyboards/yandrstudio/tg67/keymaps/default/keymap.c
index 17e31d90c516..e5d11b017827 100644
--- a/keyboards/yandrstudio/tg67/keymaps/default/keymap.c
+++ b/keyboards/yandrstudio/tg67/keymaps/default/keymap.c
@@ -25,7 +25,7 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[1] = LAYOUT(
KC_GRV, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL, KC_TRNS,
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
- KC_TRNS, KC_TRNS, RGB_HUI, RGB_HUD, RGB_SAI, RGB_SAD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
- KC_TRNS, RGB_TOG, RGB_MOD, RGB_RMOD,RGB_VAI, RGB_VAD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
+ KC_TRNS, KC_TRNS, RM_HUEU, RM_HUED, RM_SATU, RM_SATD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
+ KC_TRNS, RM_TOGG, RM_NEXT, RM_PREV, RM_VALU, RM_VALD, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS)
};
diff --git a/keyboards/ymdk/id75/keymaps/default/keymap.json b/keyboards/ymdk/id75/keymaps/default/keymap.json
index cfea8be49476..7d0664c0a6b6 100644
--- a/keyboards/ymdk/id75/keymaps/default/keymap.json
+++ b/keyboards/ymdk/id75/keymaps/default/keymap.json
@@ -16,7 +16,7 @@
[
"KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS",
"KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS",
- "RGB_MOD", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS",
+ "RM_NEXT", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS",
"KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS",
"KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "QK_BOOT"
]
diff --git a/keyboards/ymdk/ymd09/keymaps/default/keymap.c b/keyboards/ymdk/ymd09/keymaps/default/keymap.c
index 035bc079b887..820235abcf30 100644
--- a/keyboards/ymdk/ymd09/keymaps/default/keymap.c
+++ b/keyboards/ymdk/ymd09/keymaps/default/keymap.c
@@ -21,8 +21,8 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
KC_KP_4, LT(1, KC_KP_5), KC_KP_6,
KC_KP_1, KC_KP_2, KC_KP_3),
- [1] = LAYOUT(RGB_RMOD, RGB_VAI, RGB_MOD,
- RGB_HUI, KC_TRNS, RGB_SAI,
- RGB_HUD, RGB_VAD, RGB_SAD),
+ [1] = LAYOUT(RM_PREV, RM_VALU, RM_NEXT,
+ RM_HUEU, KC_TRNS, RM_SATU,
+ RM_HUED, RM_VALD, RM_SATD),
};
diff --git a/keyboards/ymdk/ymd40/air40/keymaps/default/keymap.c b/keyboards/ymdk/ymd40/air40/keymaps/default/keymap.c
index b798dce7b2bf..ea09ee215ad7 100644
--- a/keyboards/ymdk/ymd40/air40/keymaps/default/keymap.c
+++ b/keyboards/ymdk/ymd40/air40/keymaps/default/keymap.c
@@ -43,8 +43,8 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
_______, _______, _______, _______, _______, _______, _______, _______, KC_MNXT, KC_VOLD, KC_VOLU, KC_MPLY
),
[_ADJUST] = LAYOUT_ortho_4x12(
- QK_BOOT, RGB_TOG, RGB_HUI, RGB_SAI, RGB_VAI, _______, _______, _______, _______, _______, _______, DB_TOGG,
- _______, RGB_MOD, RGB_HUD, RGB_SAD, RGB_VAD, AG_NORM, AG_SWAP, _______, _______, _______, _______, _______,
+ QK_BOOT, RM_TOGG, RM_HUEU, RM_SATU, RM_VALU, _______, _______, _______, _______, _______, _______, DB_TOGG,
+ _______, RM_NEXT, RM_HUED, RM_SATD, RM_VALD, AG_NORM, AG_SWAP, _______, _______, _______, _______, _______,
_______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
_______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______
)
diff --git a/keyboards/ymdk/ymd62/keymaps/default/keymap.c b/keyboards/ymdk/ymd62/keymaps/default/keymap.c
index 79c128295eff..e5be1d7910ad 100644
--- a/keyboards/ymdk/ymd62/keymaps/default/keymap.c
+++ b/keyboards/ymdk/ymd62/keymaps/default/keymap.c
@@ -14,6 +14,6 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
KC_GRV, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_DEL ,
KC_TRNS, KC_TRNS, KC_UP, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, QK_BOOT ,
KC_TRNS, KC_LEFT, KC_DOWN, KC_RGHT, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS,
- KC_TRNS, RGB_TOG, RGB_MOD, RGB_RMOD, RGB_HUI, RGB_HUD, RGB_SAI, RGB_SAD, RGB_VAI, RGB_VAD, RGB_M_P, KC_TRNS, KC_TRNS,
+ KC_TRNS, RM_TOGG, RM_NEXT, RM_PREV, RM_HUEU, RM_HUED, RM_SATU, RM_SATD, RM_VALU, RM_VALD, RGB_M_P, KC_TRNS, KC_TRNS,
KC_VOLU, KC_VOLD, KC_MUTE, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS)
};
\ No newline at end of file
diff --git a/keyboards/ymdk/ymd75/rev4/iso/keymaps/default/keymap.c b/keyboards/ymdk/ymd75/rev4/iso/keymaps/default/keymap.c
index 15dc1dc8b70e..3f5225c43215 100644
--- a/keyboards/ymdk/ymd75/rev4/iso/keymaps/default/keymap.c
+++ b/keyboards/ymdk/ymd75/rev4/iso/keymaps/default/keymap.c
@@ -28,7 +28,7 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
),
[1] = LAYOUT_75_iso(
QK_BOOT, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
- _______, RGB_TOG, RGB_MOD, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
+ _______, RM_TOGG, RM_NEXT, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
_______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
_______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
_______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
diff --git a/keyboards/yncognito/batpad/keymaps/default/keymap.c b/keyboards/yncognito/batpad/keymaps/default/keymap.c
index 6cf40a182ec9..26ad7e81eb05 100644
--- a/keyboards/yncognito/batpad/keymaps/default/keymap.c
+++ b/keyboards/yncognito/batpad/keymaps/default/keymap.c
@@ -19,15 +19,15 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[0] = LAYOUT_ortho_2x4(
KC_Q, KC_W, KC_E, KC_R,
- KC_LGUI, KC_SPC, RGB_TOG, RGB_MOD
+ KC_LGUI, KC_SPC, RM_TOGG, RM_NEXT
),
[1] = LAYOUT_ortho_2x4(
KC_Q, KC_W, KC_E, KC_R,
- KC_LGUI, KC_SPC, RGB_TOG, RGB_MOD
+ KC_LGUI, KC_SPC, RM_TOGG, RM_NEXT
),
[2] = LAYOUT_ortho_2x4(
KC_Q, KC_W, KC_E, KC_R,
- KC_LGUI, KC_SPC, RGB_TOG, RGB_MOD
+ KC_LGUI, KC_SPC, RM_TOGG, RM_NEXT
),
diff --git a/keyboards/yosino58/keymaps/default/keymap.c b/keyboards/yosino58/keymaps/default/keymap.c
index 88320c2898cd..ff1f8ca5d4b7 100644
--- a/keyboards/yosino58/keymaps/default/keymap.c
+++ b/keyboards/yosino58/keymaps/default/keymap.c
@@ -106,8 +106,8 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[_ADJUST] = LAYOUT(
QK_BOOT, XXXXXXX, XXXXXXX, XXXXXXX, XXXXXXX, XXXXXXX, KC_MUTE, KC_VOLU, KC_MPLY, XXXXXXX, XXXXXXX, XXXXXXX,
XXXXXXX, XXXXXXX, XXXXXXX, KC_PSCR, KC_SCRL, KC_PAUS, KC_MPRV, KC_VOLD, KC_MNXT, XXXXXXX, XXXXXXX, XXXXXXX,
- XXXXXXX, XXXXXXX, XXXXXXX, KC_INS, KC_HOME, KC_PGUP, XXXXXXX, XXXXXXX, RGB_TOG, RGB_HUI, RGB_SAI, RGB_VAI,
- XXXXXXX, XXXXXXX, XXXXXXX, KC_DEL, KC_END, KC_PGDN, XXXXXXX, _______, _______, XXXXXXX, XXXXXXX, RGBRST, RGB_MOD, RGB_HUD, RGB_SAD, RGB_VAD,
+ XXXXXXX, XXXXXXX, XXXXXXX, KC_INS, KC_HOME, KC_PGUP, XXXXXXX, XXXXXXX, UG_TOGG, UG_HUEU, UG_SATU, UG_VALU,
+ XXXXXXX, XXXXXXX, XXXXXXX, KC_DEL, KC_END, KC_PGDN, XXXXXXX, _______, _______, XXXXXXX, XXXXXXX, RGBRST, UG_NEXT, UG_HUED, UG_SATD, UG_VALD,
XXXXXXX, _______, XXXXXXX, XXXXXXX, XXXXXXX, XXXXXXX
)
};
@@ -265,7 +265,7 @@ bool process_record_user(uint16_t keycode, keyrecord_t *record) {
}
return false;
break;
- case RGB_MOD:
+ case QK_UNDERGLOW_MODE_NEXT:
#ifdef RGBLIGHT_ENABLE
if (record->event.pressed) {
rgblight_mode(RGB_current_mode);
diff --git a/keyboards/yushakobo/quick17/keymaps/default/keymap.c b/keyboards/yushakobo/quick17/keymaps/default/keymap.c
index 2bde382cae46..80e1b04ca535 100644
--- a/keyboards/yushakobo/quick17/keymaps/default/keymap.c
+++ b/keyboards/yushakobo/quick17/keymaps/default/keymap.c
@@ -35,11 +35,11 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[_EDIT2] = LAYOUT(
KC_ESC, KC_Q, KC_BTN3,KC_INS, KC_ENT, KC_DEL,
KC_LCTL,KC_LBRC,KC_RBRC,KC_PGDN,KC_PGUP,LCTL(KC_Y),
- KC_LSFT,TO(3), RGB_TOG,TO(0), _______,KC_NO
+ KC_LSFT,TO(3), RM_TOGG,TO(0), _______,KC_NO
),
[_FN] = LAYOUT(
- KC_ESC, KC_LANG,KC_NO, RGB_TOG,KC_MNXT,KC_VOLU,
- KC_CAPS,KC_NUM, KC_NO, RGB_MOD,KC_MPRV,KC_VOLD,
+ KC_ESC, KC_LANG,KC_NO, RM_TOGG,KC_MNXT,KC_VOLU,
+ KC_CAPS,KC_NUM, KC_NO, RM_NEXT,KC_MPRV,KC_VOLD,
CG_NORM,CG_LSWP,EE_CLR, QK_BOOT,TO(0), KC_MUTE
)
};
diff --git a/keyboards/yushakobo/quick17/quick17_prefs.h b/keyboards/yushakobo/quick17/quick17_prefs.h
index a498381cee58..1c95e2efb903 100644
--- a/keyboards/yushakobo/quick17/quick17_prefs.h
+++ b/keyboards/yushakobo/quick17/quick17_prefs.h
@@ -27,7 +27,7 @@ enum layer_names {
_FN
};
-#define _HSV(H, S, V) (HSV){ .h = H, .s = S, .v = V }
+#define _HSV(H, S, V) (hsv_t){ .h = H, .s = S, .v = V }
#define _RGB(rgb) rgb.r, rgb.g, rgb.b
bool input_mode(void);
diff --git a/keyboards/yushakobo/quick17/rgb_matrix_kb.inc b/keyboards/yushakobo/quick17/rgb_matrix_kb.inc
index 4998cce0291a..170cf8a8d7b5 100644
--- a/keyboards/yushakobo/quick17/rgb_matrix_kb.inc
+++ b/keyboards/yushakobo/quick17/rgb_matrix_kb.inc
@@ -52,17 +52,17 @@ const uint8_t rgb_keymaps [][RGB_MATRIX_LED_COUNT] = {
};
static void led_color_set(uint8_t index, uint8_t color_patterns) {
- HSV hsv = rgb_matrix_config.hsv; // 'quantum/color.h'
- RGB rgb_white = hsv_to_rgb(_HSV( 0, 0, hsv.v)); // HSV_WHITE
- RGB rgb_indc1 = hsv_to_rgb(_HSV(128, 255, hsv.v)); // HSV_TEAL
- RGB rgb_indc2 = hsv_to_rgb(_HSV(191, 255, hsv.v)); // HSV_PURPLE
- RGB rgb_indc3 = hsv_to_rgb(_HSV( 64, 255, hsv.v)); // HSV_CHARTREUSE
- RGB rgb_indc4 = hsv_to_rgb(_HSV(106, 255, hsv.v)); // HSV_SPRINGGREEN
- RGB rgb_indc5 = hsv_to_rgb(_HSV(234, 128, hsv.v)); // HSV_PINK
- RGB rgb_indc6 = hsv_to_rgb(_HSV(213, 255, hsv.v)); // HSV_MAGENTA
- RGB rgb_indc_ja = hsv_to_rgb(_HSV( 0, 255, hsv.v)); // HSV_RED
- RGB rgb_indc_en = hsv_to_rgb(_HSV( 85, 255, hsv.v)); // HSV_GREEN
- RGB rgb_indc_win = hsv_to_rgb(_HSV(170, 255, hsv.v)); // HSV_BLUE
+ hsv_t hsv = rgb_matrix_config.hsv; // 'quantum/color.h'
+ rgb_t rgb_white = hsv_to_rgb(_HSV( 0, 0, hsv.v)); // HSV_WHITE
+ rgb_t rgb_indc1 = hsv_to_rgb(_HSV(128, 255, hsv.v)); // HSV_TEAL
+ rgb_t rgb_indc2 = hsv_to_rgb(_HSV(191, 255, hsv.v)); // HSV_PURPLE
+ rgb_t rgb_indc3 = hsv_to_rgb(_HSV( 64, 255, hsv.v)); // HSV_CHARTREUSE
+ rgb_t rgb_indc4 = hsv_to_rgb(_HSV(106, 255, hsv.v)); // HSV_SPRINGGREEN
+ rgb_t rgb_indc5 = hsv_to_rgb(_HSV(234, 128, hsv.v)); // HSV_PINK
+ rgb_t rgb_indc6 = hsv_to_rgb(_HSV(213, 255, hsv.v)); // HSV_MAGENTA
+ rgb_t rgb_indc_ja = hsv_to_rgb(_HSV( 0, 255, hsv.v)); // HSV_RED
+ rgb_t rgb_indc_en = hsv_to_rgb(_HSV( 85, 255, hsv.v)); // HSV_GREEN
+ rgb_t rgb_indc_win = hsv_to_rgb(_HSV(170, 255, hsv.v)); // HSV_BLUE
switch(color_patterns){
case BOUT: rgb_matrix_set_color(index, RGB_BLACK); break;
case _____: rgb_matrix_set_color(index, _RGB(rgb_white)); break;
diff --git a/keyboards/ziptyze/lets_split_v3/keymaps/default/keymap.c b/keyboards/ziptyze/lets_split_v3/keymaps/default/keymap.c
index d640e1bf2349..cd899c8a89e3 100644
--- a/keyboards/ziptyze/lets_split_v3/keymaps/default/keymap.c
+++ b/keyboards/ziptyze/lets_split_v3/keymaps/default/keymap.c
@@ -37,7 +37,7 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
),
[3] = LAYOUT_ortho_4x12(
- _______, QK_BOOT, DB_TOGG, RGB_TOG, RGB_MOD, RGB_HUI, RGB_HUD, RGB_SAI, RGB_SAD, RGB_VAI, RGB_VAD, KC_DEL ,
+ _______, QK_BOOT, DB_TOGG, RM_TOGG, RM_NEXT, RM_HUEU, RM_HUED, RM_SATU, RM_SATD, RM_VALU, RM_VALD, KC_DEL ,
_______, _______, _______, AU_ON, AU_OFF, AG_NORM, AG_SWAP, _______, _______, _______, _______, _______,
_______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______,
_______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______, _______
diff --git a/keyboards/zsa/moonlander/keymaps/default/keymap.c b/keyboards/zsa/moonlander/keymaps/default/keymap.c
index ad7705eff835..338e8e4f97fd 100644
--- a/keyboards/zsa/moonlander/keymaps/default/keymap.c
+++ b/keyboards/zsa/moonlander/keymaps/default/keymap.c
@@ -47,8 +47,8 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
_______, KC_EXLM, KC_AT, KC_LCBR, KC_RCBR, KC_PIPE, _______, _______, KC_UP, KC_7, KC_8, KC_9, KC_ASTR, KC_F12,
_______, KC_HASH, KC_DLR, KC_LPRN, KC_RPRN, KC_GRV, _______, _______, KC_DOWN, KC_4, KC_5, KC_6, KC_PLUS, _______,
_______, KC_PERC, KC_CIRC, KC_LBRC, KC_RBRC, KC_TILD, KC_AMPR, KC_1, KC_2, KC_3, KC_BSLS, _______,
- EE_CLR, _______, _______, _______, _______, RGB_VAI, RGB_TOG, _______, KC_DOT, KC_0, KC_EQL, _______,
- RGB_HUD, RGB_VAD, RGB_HUI, TOGGLE_LAYER_COLOR,_______, _______
+ EE_CLR, _______, _______, _______, _______, RM_VALU, RM_TOGG, _______, KC_DOT, KC_0, KC_EQL, _______,
+ RM_HUED, RM_VALD, RM_HUEU, TOGGLE_LAYER_COLOR,_______, _______
),
[MDIA] = LAYOUT(
diff --git a/keyboards/zsa/moonlander/moonlander.c b/keyboards/zsa/moonlander/moonlander.c
index faa1dc75e827..999fcbe1dd48 100644
--- a/keyboards/zsa/moonlander/moonlander.c
+++ b/keyboards/zsa/moonlander/moonlander.c
@@ -275,6 +275,7 @@ bool music_mask_kb(uint16_t keycode) {
case QK_TO ... QK_TO_MAX:
case QK_MOMENTARY ... QK_MOMENTARY_MAX:
case QK_DEF_LAYER ... QK_DEF_LAYER_MAX:
+ case QK_PERSISTENT_DEF_LAYER ... QK_PERSISTENT_DEF_LAYER_MAX:
case QK_TOGGLE_LAYER ... QK_TOGGLE_LAYER_MAX:
case QK_ONE_SHOT_LAYER ... QK_ONE_SHOT_LAYER_MAX:
case QK_LAYER_TAP_TOGGLE ... QK_LAYER_TAP_TOGGLE_MAX:
@@ -368,7 +369,7 @@ bool process_record_kb(uint16_t keycode, keyrecord_t *record) {
eeconfig_update_kb(keyboard_config.raw);
}
break;
- case RGB_TOG:
+ case QK_RGB_MATRIX_TOGGLE:
if (record->event.pressed) {
switch (rgb_matrix_get_flags()) {
case LED_FLAG_ALL: {
diff --git a/keyboards/zsa/planck_ez/keymaps/default/keymap.json b/keyboards/zsa/planck_ez/keymaps/default/keymap.json
index 4b27cc2970a8..b9f0cd2ae4fe 100644
--- a/keyboards/zsa/planck_ez/keymaps/default/keymap.json
+++ b/keyboards/zsa/planck_ez/keymaps/default/keymap.json
@@ -5,7 +5,7 @@
["KC_TAB", "KC_Q", "KC_W", "KC_E", "KC_R", "KC_T", "KC_Y", "KC_U", "KC_I", "KC_O", "KC_P", "KC_BSPC", "KC_ESC", "KC_A", "KC_S", "KC_D", "KC_F", "KC_G", "KC_H", "KC_J", "KC_K", "KC_L", "KC_SCLN", "KC_QUOT", "KC_LSFT", "KC_Z", "KC_X", "KC_C", "KC_V", "KC_B", "KC_N", "KC_M", "KC_COMM", "KC_DOT", "KC_SLSH", "KC_ENT", "CW_TOGG", "KC_LCTL", "KC_LALT", "KC_LGUI", "TL_LOWR", "KC_SPC", "TL_UPPR", "KC_LEFT", "KC_DOWN", "KC_UP", "KC_RGHT"],
["KC_TILD", "KC_EXLM", "KC_AT", "KC_HASH", "KC_DLR", "KC_PERC", "KC_CIRC", "KC_AMPR", "KC_ASTR", "KC_LPRN", "KC_RPRN", "KC_BSPC", "KC_DEL", "KC_F1", "KC_F2", "KC_F3", "KC_F4", "KC_F5", "KC_F6", "KC_UNDS", "KC_PLUS", "KC_LCBR", "KC_RCBR", "KC_PIPE", "KC_TRNS", "KC_F7", "KC_F8", "KC_F9", "KC_F10", "KC_F11", "KC_F12", "S(KC_NUHS)", "S(KC_NUBS)", "KC_HOME", "KC_END", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_MNXT", "KC_VOLD", "KC_VOLU", "KC_MPLY"],
["KC_GRV", "KC_1", "KC_2", "KC_3", "KC_4", "KC_5", "KC_6", "KC_7", "KC_8", "KC_9", "KC_0", "KC_BSPC", "KC_DEL", "KC_F1", "KC_F2", "KC_F3", "KC_F4", "KC_F5", "KC_F6", "KC_MINS", "KC_EQL", "KC_LBRC", "KC_RBRC", "KC_BSLS", "KC_TRNS", "KC_F7", "KC_F8", "KC_F9", "KC_F10", "KC_F11", "KC_F12", "KC_NUHS", "KC_NUBS", "KC_PGUP", "KC_PGDN", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_MNXT", "KC_VOLD", "KC_VOLU", "KC_MPLY"],
- ["KC_TRNS", "QK_BOOT", "DB_TOGG", "RGB_TOG", "RGB_MOD", "RGB_HUI", "RGB_HUD", "RGB_SAI", "RGB_SAD", "RGB_VAI", "RGB_VAD", "KC_DEL", "KC_TRNS", "KC_TRNS", "MU_NEXT", "AU_ON", "AU_OFF", "AG_NORM", "AG_SWAP", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "AU_PREV", "AU_NEXT", "MU_ON", "MU_OFF", "MI_ON", "MI_OFF", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS"]
+ ["KC_TRNS", "QK_BOOT", "DB_TOGG", "RM_TOGG", "RM_NEXT", "RM_HUEU", "RM_HUED", "RM_SATU", "RM_SATD", "RM_VALU", "RM_VALD", "KC_DEL", "KC_TRNS", "KC_TRNS", "MU_NEXT", "AU_ON", "AU_OFF", "AG_NORM", "AG_SWAP", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "AU_PREV", "AU_NEXT", "MU_ON", "MU_OFF", "MI_ON", "MI_OFF", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS", "KC_TRNS"]
],
"layout": "LAYOUT_planck_1x2uC",
"config": {
diff --git a/keyboards/zsa/planck_ez/planck_ez.c b/keyboards/zsa/planck_ez/planck_ez.c
index 9c0e911654eb..ff82f43c668d 100644
--- a/keyboards/zsa/planck_ez/planck_ez.c
+++ b/keyboards/zsa/planck_ez/planck_ez.c
@@ -206,7 +206,7 @@ bool process_record_kb(uint16_t keycode, keyrecord_t *record) {
eeconfig_update_kb(keyboard_config.raw);
}
break;
- case RGB_TOG:
+ case QK_RGB_MATRIX_TOGGLE:
if (record->event.pressed) {
switch (rgb_matrix_get_flags()) {
case LED_FLAG_ALL: {
@@ -237,6 +237,7 @@ bool music_mask_kb(uint16_t keycode) {
case QK_TO ... QK_TO_MAX:
case QK_MOMENTARY ... QK_MOMENTARY_MAX:
case QK_DEF_LAYER ... QK_DEF_LAYER_MAX:
+ case QK_PERSISTENT_DEF_LAYER ... QK_PERSISTENT_DEF_LAYER_MAX:
case QK_TOGGLE_LAYER ... QK_TOGGLE_LAYER_MAX:
case QK_ONE_SHOT_LAYER ... QK_ONE_SHOT_LAYER_MAX:
case QK_LAYER_TAP_TOGGLE ... QK_LAYER_TAP_TOGGLE_MAX:
diff --git a/keyboards/zsa/voyager/keymaps/default/keymap.c b/keyboards/zsa/voyager/keymaps/default/keymap.c
index e05794de756b..3004c332226a 100644
--- a/keyboards/zsa/voyager/keymaps/default/keymap.c
+++ b/keyboards/zsa/voyager/keymaps/default/keymap.c
@@ -20,7 +20,7 @@ const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
_______, _______, _______, KC_0
),
[2] = LAYOUT(
- RGB_TOG, QK_KB, RGB_MOD, RGB_M_P, RGB_VAD, RGB_VAI, _______, _______, _______, _______, _______, QK_BOOT,
+ RM_TOGG, QK_KB, RM_NEXT, RGB_M_P, RM_VALD, RM_VALU, _______, _______, _______, _______, _______, QK_BOOT,
_______, _______, KC_VOLD, KC_VOLU, KC_MUTE, _______, KC_PGUP, KC_HOME, KC_UP, KC_END, _______, _______,
_______, KC_MPRV, KC_MNXT, KC_MSTP, KC_MPLY, _______, KC_PGDN, KC_LEFT, KC_DOWN, KC_RGHT, _______, _______,
_______, _______, _______, _______, _______, _______, _______, C(S(KC_TAB)), C(KC_TAB), _______, _______, _______,
diff --git a/keyboards/zsa/voyager/voyager.c b/keyboards/zsa/voyager/voyager.c
index 69d42bba1a3e..6d4f6c5f26a3 100644
--- a/keyboards/zsa/voyager/voyager.c
+++ b/keyboards/zsa/voyager/voyager.c
@@ -249,7 +249,7 @@ bool process_record_kb(uint16_t keycode, keyrecord_t *record) {
if (keyboard_config.disable_layer_led) rgb_matrix_set_color_all(0, 0, 0);
}
break;
- case RGB_TOG:
+ case QK_RGB_MATRIX_TOGGLE:
if (record->event.pressed) {
switch (rgb_matrix_get_flags()) {
case LED_FLAG_ALL: {
diff --git a/layouts/community/60_tsangan_hhkb/readme.md b/layouts/community/60_tsangan_hhkb/readme.md
deleted file mode 100644
index 78a0b82beeb9..000000000000
--- a/layouts/community/60_tsangan_hhkb/readme.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# 60_tsangan_hhkb
-
- LAYOUT_60_tsangan_hhkb
diff --git a/layouts/default/60_tsangan_hhkb/default_60_tsangan_hhkb/keymap.c b/layouts/default/60_tsangan_hhkb/default_60_tsangan_hhkb/keymap.c
deleted file mode 100644
index 132763959074..000000000000
--- a/layouts/default/60_tsangan_hhkb/default_60_tsangan_hhkb/keymap.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// Copyright 2023 QMK
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include QMK_KEYBOARD_H
-
-const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
- /*
- * ┌───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┐
- * │ ` │ 1 │ 2 │ 3 │ 4 │ 5 │ 6 │ 7 │ 8 │ 9 │ 0 │ - │ = │Bsp│Bsp│
- * ├───┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴───┤
- * │ Tab │ Q │ W │ E │ R │ T │ Y │ U │ I │ O │ P │ [ │ ] │ \ │
- * ├─────┴┬──┴┬──┴┬──┴┬──┴┬──┴┬──┴┬──┴┬──┴┬──┴┬──┴┬──┴┬──┴─────┤
- * │ Caps │ A │ S │ D │ F │ G │ H │ J │ K │ L │ ; │ ' │ Enter │
- * ├──────┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴─┬─┴────┬───┤
- * │ Shift │ Z │ X │ C │ V │ B │ N │ M │ , │ . │ / │ Shift│Sft│
- * ├─────┬──┴┬──┴──┬┴───┴───┴───┴───┴───┴───┴──┬┴───┴┬───┬─┴───┤
- * │Ctrl │GUI│ Alt │ │ Alt │GUI│ Ctrl│
- * └─────┴───┴─────┴───────────────────────────┴─────┴───┴─────┘
- */
- [0] = LAYOUT_60_tsangan_hhkb(
- KC_GRV, KC_1, KC_2, KC_3, KC_4, KC_5, KC_6, KC_7, KC_8, KC_9, KC_0, KC_MINS, KC_EQL, KC_BSPC, KC_BSPC,
- KC_TAB, KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, KC_LBRC, KC_RBRC, KC_BSLS,
- KC_CAPS, KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, KC_QUOT, KC_ENT,
- KC_LSFT, KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, KC_RSFT, KC_RSFT,
- KC_LCTL, KC_LGUI, KC_LALT, KC_SPC, KC_RALT, KC_RGUI, KC_RCTL
- )
-};
diff --git a/layouts/default/60_tsangan_hhkb/info.json b/layouts/default/60_tsangan_hhkb/info.json
deleted file mode 100644
index 091456eb7016..000000000000
--- a/layouts/default/60_tsangan_hhkb/info.json
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- "keyboard_name": "60% ANSI Tsangan HHKB layout",
- "url": "",
- "maintainer": "qmk",
- "layouts": {
- "LAYOUT_60_tsangan_hhkb": {
- "layout": [
- {"x":0, "y":0},
- {"x":1, "y":0},
- {"x":2, "y":0},
- {"x":3, "y":0},
- {"x":4, "y":0},
- {"x":5, "y":0},
- {"x":6, "y":0},
- {"x":7, "y":0},
- {"x":8, "y":0},
- {"x":9, "y":0},
- {"x":10, "y":0},
- {"x":11, "y":0},
- {"x":12, "y":0},
- {"x":13, "y":0},
- {"x":14, "y":0},
-
- {"x":0, "y":1, "w":1.5},
- {"x":1.5, "y":1},
- {"x":2.5, "y":1},
- {"x":3.5, "y":1},
- {"x":4.5, "y":1},
- {"x":5.5, "y":1},
- {"x":6.5, "y":1},
- {"x":7.5, "y":1},
- {"x":8.5, "y":1},
- {"x":9.5, "y":1},
- {"x":10.5, "y":1},
- {"x":11.5, "y":1},
- {"x":12.5, "y":1},
- {"x":13.5, "y":1, "w":1.5},
-
- {"x":0, "y":2, "w":1.75},
- {"x":1.75, "y":2},
- {"x":2.75, "y":2},
- {"x":3.75, "y":2},
- {"x":4.75, "y":2},
- {"x":5.75, "y":2},
- {"x":6.75, "y":2},
- {"x":7.75, "y":2},
- {"x":8.75, "y":2},
- {"x":9.75, "y":2},
- {"x":10.75, "y":2},
- {"x":11.75, "y":2},
- {"x":12.75, "y":2, "w":2.25},
-
- {"x":0, "y":3, "w":2.25},
- {"x":2.25, "y":3},
- {"x":3.25, "y":3},
- {"x":4.25, "y":3},
- {"x":5.25, "y":3},
- {"x":6.25, "y":3},
- {"x":7.25, "y":3},
- {"x":8.25, "y":3},
- {"x":9.25, "y":3},
- {"x":10.25, "y":3},
- {"x":11.25, "y":3},
- {"x":12.25, "y":3, "w":1.75},
- {"x":14, "y":3},
-
- {"x":0, "y":4, "w":1.5},
- {"x":1.5, "y":4},
- {"x":2.5, "y":4, "w":1.5},
- {"x":4, "y":4, "w":7},
- {"x":11, "y":4, "w":1.5},
- {"x":12.5, "y":4},
- {"x":13.5, "y":4, "w":1.5}
- ]
- }
- }
-}
diff --git a/layouts/default/60_tsangan_hhkb/layout.json b/layouts/default/60_tsangan_hhkb/layout.json
deleted file mode 100644
index c387347d9e67..000000000000
--- a/layouts/default/60_tsangan_hhkb/layout.json
+++ /dev/null
@@ -1,5 +0,0 @@
-[{a:7},"","","","","","","","","","","","","","",""],
-[{w:1.5},"","","","","","","","","","","","","",{w:1.5},""],
-[{w:1.75},"","","","","","","","","","","","",{w:2.25},""],
-[{w:2.25},"","","","","","","","","","","",{w:1.75},"",""],
-[{w:1.5},"","",{w:1.5},"",{w:7},"",{w:1.5},"","",{w:1.5},""]
diff --git a/layouts/default/60_tsangan_hhkb/readme.md b/layouts/default/60_tsangan_hhkb/readme.md
deleted file mode 100644
index 78a0b82beeb9..000000000000
--- a/layouts/default/60_tsangan_hhkb/readme.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# 60_tsangan_hhkb
-
- LAYOUT_60_tsangan_hhkb
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h
deleted file mode 100644
index 4be7e8c84889..000000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h
+++ /dev/null
@@ -1,7226 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_math.h
- * Description: Public header file for CMSIS DSP Library
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- \mainpage CMSIS DSP Software Library
- *
- * Introduction
- * ------------
- *
- * This user manual describes the CMSIS DSP software library,
- * a suite of common signal processing functions for use on Cortex-M processor based devices.
- *
- * The library is divided into a number of functions each covering a specific category:
- * - Basic math functions
- * - Fast math functions
- * - Complex math functions
- * - Filters
- * - Matrix functions
- * - Transforms
- * - Motor control functions
- * - Statistical functions
- * - Support functions
- * - Interpolation functions
- *
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,
- * 32-bit integer and 32-bit floating-point values.
- *
- * Using the Library
- * ------------
- *
- * The library installer contains prebuilt versions of the libraries in the Lib folder.
- * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
- * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
- * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
- * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
- * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
- * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
- * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
- * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
- * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
- * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
- * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
- * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
- * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
- * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
- * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
- * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
- * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
- * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
- * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
- *
- * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
- * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
- * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
- *
- *
- * Examples
- * --------
- *
- * The library ships with a number of examples which demonstrate how to use the library functions.
- *
- * Toolchain Support
- * ------------
- *
- * The library has been developed and tested with MDK-ARM version 5.14.0.0
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
- *
- * Building the Library
- * ------------
- *
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
- * - arm_cortexM_math.uvprojx
- *
- *
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
- *
- * Pre-processor Macros
- * ------------
- *
- * Each library project have differant pre-processor macros.
- *
- * - UNALIGNED_SUPPORT_DISABLE:
- *
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
- *
- * - ARM_MATH_BIG_ENDIAN:
- *
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * - ARM_MATH_MATRIX_CHECK:
- *
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
- *
- * - ARM_MATH_ROUNDING:
- *
- * Define macro ARM_MATH_ROUNDING for rounding on support functions
- *
- * - ARM_MATH_CMx:
- *
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
- * ARM_MATH_CM7 for building the library on cortex-M7.
- *
- * - ARM_MATH_ARMV8MxL:
- *
- * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
- * on ARMv8M Mainline target.
- *
- * - __FPU_PRESENT:
- *
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
- *
- * - __DSP_PRESENT:
- *
- * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
- *
- *
- * CMSIS-DSP in ARM::CMSIS Pack
- * -----------------------------
- *
- * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
- * |File/Folder |Content |
- * |------------------------------|------------------------------------------------------------------------|
- * |\b CMSIS\\Documentation\\DSP | This documentation |
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
- *
- *
- * Revision History of CMSIS-DSP
- * ------------
- * Please refer to \ref ChangeLog_pg.
- *
- * Copyright Notice
- * ------------
- *
- * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
- */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures. For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- *
- * typedef struct
- * {
- * uint16_t numRows; // number of rows of the matrix.
- * uint16_t numCols; // number of columns of the matrix.
- * float32_t *pData; // points to the data of the matrix.
- * } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data. The array is of size numRows X numCols
- * and the values are arranged in row order. That is, the
- * matrix element (i, j) is stored at:
- *
- * pData[i*numCols + j]
- *
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
- * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure. For example:
- *
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns
- * specifies the number of columns, and pData points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- *
- * ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return
- *
- * ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- *
- * ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return ARM_MATH_SUCCESS.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* ignore some GCC warnings */
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-#endif
-
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
- #include "core_cm7.h"
- #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
- #include "core_cm4.h"
- #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
- #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
- #include "core_cm0.h"
- #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
- #include "core_cm0plus.h"
- #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
- #include "core_armv8mbl.h"
- #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
- #include "core_armv8mml.h"
- #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
- #define ARM_MATH_DSP
- #endif
-#else
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
- /**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31 (0x100)
-#define DELTA_Q15 0x5
-#define INDEX_MASK 0x0000003F
-#ifndef PI
- #define PI 3.14159265358979f
-#endif
-
- /**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define FAST_MATH_TABLE_SIZE 512
-#define FAST_MATH_Q31_SHIFT (32 - 10)
-#define FAST_MATH_Q15_SHIFT (16 - 10)
-#define CONTROLLER_Q31_SHIFT (32 - 9)
-#define TABLE_SPACING_Q31 0x400000
-#define TABLE_SPACING_Q15 0x80
-
- /**
- * @brief Macros required for SINE and COSINE Controller functions
- */
- /* 1.31(q31) Fixed value of 2/360 */
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING 0xB60B61
-
- /**
- * @brief Macro for Unaligned Support
- */
-#ifndef UNALIGNED_SUPPORT_DISABLE
- #define ALIGN4
-#else
- #if defined (__GNUC__)
- #define ALIGN4 __attribute__((aligned(4)))
- #else
- #define ALIGN4 __align(4)
- #endif
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /**
- * @brief Error status returned by some functions in the library.
- */
-
- typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
-
- /**
- * @brief 8-bit fractional data type in 1.7 format.
- */
- typedef int8_t q7_t;
-
- /**
- * @brief 16-bit fractional data type in 1.15 format.
- */
- typedef int16_t q15_t;
-
- /**
- * @brief 32-bit fractional data type in 1.31 format.
- */
- typedef int32_t q31_t;
-
- /**
- * @brief 64-bit fractional data type in 1.63 format.
- */
- typedef int64_t q63_t;
-
- /**
- * @brief 32-bit floating-point type definition.
- */
- typedef float float32_t;
-
- /**
- * @brief 64-bit floating-point type definition.
- */
- typedef double float64_t;
-
- /**
- * @brief definition to read/write two 16 bit values.
- */
-#if defined ( __CC_ARM )
- #define __SIMD32_TYPE int32_t __packed
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
- #define __SIMD32_TYPE int32_t __packed
- #define CMSIS_UNUSED
- #define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED
- #define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
- #define __SIMD32_TYPE __unaligned int32_t
- #define CMSIS_UNUSED
- #define CMSIS_INLINE
-
-#else
- #error Unknown compiler
-#endif
-
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
-#define __SIMD64(addr) (*(int64_t **) & (addr))
-
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
- /**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
- /**
- * @brief definition to pack four 8 bit values.
- */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-
-#endif
-
-
- /**
- * @brief Clips Q63 to Q31 values.
- */
- CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
- }
-
- /**
- * @brief Clips Q63 to Q15 values.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
- }
-
- /**
- * @brief Clips Q31 to Q7 values.
- */
- CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
- q31_t x)
- {
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
- }
-
- /**
- * @brief Clips Q31 to Q15 values.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
- q31_t x)
- {
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
- }
-
- /**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
- CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
- {
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
- (((q63_t) (x >> 32) * y)));
- }
-
-/*
- #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
- #define __CLZ __clz
- #endif
- */
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
- CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
- q31_t data);
-
- CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
- q31_t data)
- {
- uint32_t count = 0;
- uint32_t mask = 0x80000000;
-
- while ((data & mask) == 0)
- {
- count += 1u;
- mask = mask >> 1u;
- }
-
- return (count);
- }
-#endif
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
-
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- q31_t * pRecipTable)
- {
- q31_t out;
- uint32_t tempVal;
- uint32_t index, i;
- uint32_t signBits;
-
- if (in > 0)
- {
- signBits = ((uint32_t) (__CLZ( in) - 1));
- }
- else
- {
- signBits = ((uint32_t) (__CLZ(-in) - 1));
- }
-
- /* Convert input sample to 1.31 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 24);
- index = (index & INDEX_MASK);
-
- /* 1.31 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (uint32_t) (((q63_t) in * out) >> 31);
- tempVal = 0x7FFFFFFFu - tempVal;
- /* 1.31 with exp 1 */
- /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
- out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1u);
- }
-
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- q15_t * pRecipTable)
- {
- q15_t out = 0;
- uint32_t tempVal = 0;
- uint32_t index = 0, i = 0;
- uint32_t signBits = 0;
-
- if (in > 0)
- {
- signBits = ((uint32_t)(__CLZ( in) - 17));
- }
- else
- {
- signBits = ((uint32_t)(__CLZ(-in) - 17));
- }
-
- /* Convert input sample to 1.15 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 8);
- index = (index & INDEX_MASK);
-
- /* 1.15 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (uint32_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFFu - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1);
- }
-
-
- /*
- * @brief C custom defined intrinisic function for only M0 processors
- */
-#if defined(ARM_MATH_CM0_FAMILY)
- CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
- q31_t x,
- uint32_t y)
- {
- int32_t posMax, negMin;
- uint32_t i;
-
- posMax = 1;
- for (i = 0; i < (y - 1); i++)
- {
- posMax = posMax * 2;
- }
-
- if (x > 0)
- {
- posMax = (posMax - 1);
-
- if (x > posMax)
- {
- x = posMax;
- }
- }
- else
- {
- negMin = -posMax;
-
- if (x < negMin)
- {
- x = negMin;
- }
- }
- return (x);
- }
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
- /*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-
- /*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
- uint32_t x,
- uint32_t y)
- {
-/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
- q31_t r = 0, s = 0;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QASX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
- /*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined QADD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SXTB16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
- uint32_t x)
- {
- return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
- ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
- }
-
- /*
- * @brief C custom defined SMMLA for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
- int32_t x,
- int32_t y,
- int32_t sum)
- {
- return (sum + (int32_t) (((int64_t) x * y) >> 32));
- }
-
-#if 0
- /*
- * @brief C custom defined PKHBT for unavailable DSP extension
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
- uint32_t x,
- uint32_t y,
- uint32_t leftshift)
- {
- return ( ((x ) & 0x0000FFFFUL) |
- ((y << leftshift) & 0xFFFF0000UL) );
- }
-
- /*
- * @brief C custom defined PKHTB for unavailable DSP extension
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
- uint32_t x,
- uint32_t y,
- uint32_t rightshift)
- {
- return ( ((x ) & 0xFFFF0000UL) |
- ((y >> rightshift) & 0x0000FFFFUL) );
- }
-#endif
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-
- /**
- * @brief Instance structure for the Q7 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q7;
-
- /**
- * @brief Instance structure for the Q15 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_f32;
-
-
- /**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in] S points to an instance of the Q7 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 FIR filter.
- * @param[in,out] S points to an instance of the Q7 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed.
- */
- void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] S points to an instance of the Q15 FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR filter.
- * @param[in,out] S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * numTaps is not a supported value.
- */
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in] S points to an instance of the Q31 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR filter.
- * @param[in,out] S points to an instance of the Q31 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in] S points to an instance of the floating-point FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR filter.
- * @param[in,out] S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
- typedef struct
- {
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q15;
-
- /**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q31;
-
- /**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_casd_df1_inst_f32;
-
-
- /**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float32_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f32;
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float64_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f64;
-
- /**
- * @brief Instance structure for the Q15 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q15_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q31_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q31;
-
-
- /**
- * @brief Floating-point matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Q31, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
-
- /**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
-
- /**
- * @brief Q31 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix scaling.
- * @param[in] pSrc points to the input matrix
- * @param[in] scale scale factor
- * @param[out] pDst points to the output matrix
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
- arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t * pData);
-
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t * pData);
-
-
- /**
- * @brief Floating-point matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t * pData);
-
-
-
- /**
- * @brief Instance structure for the Q15 PID Control.
- */
- typedef struct
- {
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
- q15_t A1;
- q15_t A2;
-#else
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
- q15_t state[3]; /**< The state array of length 3. */
- q15_t Kp; /**< The proportional gain. */
- q15_t Ki; /**< The integral gain. */
- q15_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 PID Control.
- */
- typedef struct
- {
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- q31_t A2; /**< The derived gain, A2 = Kd . */
- q31_t state[3]; /**< The state array of length 3. */
- q31_t Kp; /**< The proportional gain. */
- q31_t Ki; /**< The integral gain. */
- q31_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point PID Control.
- */
- typedef struct
- {
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- float32_t A2; /**< The derived gain, A2 = Kd . */
- float32_t state[3]; /**< The state array of length 3. */
- float32_t Kp; /**< The proportional gain. */
- float32_t Ki; /**< The integral gain. */
- float32_t Kd; /**< The derivative gain. */
- } arm_pid_instance_f32;
-
-
-
- /**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- */
- void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
-
-
- /**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q31 PID Control structure
- */
-
- void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
-
-
- /**
- * @brief Initialization function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the q15 PID Control structure
- */
- void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
-
-
- /**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
- typedef struct
- {
- uint32_t nValues; /**< nValues */
- float32_t x1; /**< x1 */
- float32_t xSpacing; /**< xSpacing */
- float32_t *pYData; /**< pointer to the table of Y values */
- } arm_linear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q15;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q7;
-
-
- /**
- * @brief Q7 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q15(
- arm_cfft_radix2_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q15(
- const arm_cfft_radix2_instance_q15 * S,
- q15_t * pSrc);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
-
- /**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q31(
- arm_cfft_radix2_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q31(
- const arm_cfft_radix2_instance_q31 * S,
- q31_t * pSrc);
-
- /**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
- void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_f32(
- arm_cfft_radix2_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_f32(
- const arm_cfft_radix2_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
- const arm_cfft_instance_q15 * S,
- q15_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
- const arm_cfft_instance_q31 * S,
- q31_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_f32;
-
- void arm_cfft_f32(
- const arm_cfft_instance_f32 * S,
- float32_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q15;
-
- arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
-
- /**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q31;
-
- arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_f32;
-
- arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct
- {
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
- uint16_t fftLenRFFT; /**< length of the real sequence */
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
- } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
- arm_rfft_fast_instance_f32 * S,
- uint16_t fftLen);
-
-void arm_rfft_fast_f32(
- arm_rfft_fast_instance_f32 * S,
- float32_t * p, float32_t * pOut,
- uint8_t ifftFlag);
-
- /**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- float32_t normalize; /**< normalizing factor. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- float32_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_f32;
-
-
- /**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
- */
- arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
-
-
- /**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q31_t normalize; /**< normalizing factor. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- q31_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q31;
-
-
- /**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
- */
- arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
-
-
- /**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q31 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q15_t normalize; /**< normalizing factor. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- q15_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
- */
- arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
-
-
- /**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q15 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
-
-
- /**
- * @brief Floating-point vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Dot product of floating-point vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
-
-
- /**
- * @brief Dot product of Q7 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
-
-
- /**
- * @brief Dot product of Q15 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Dot product of Q31 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q7 sequences
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Instance structure for the Q15 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in] S points to an instance of the floating-point FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR decimator.
- * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- */
- arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- */
- arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- */
- arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
- } arm_fir_interpolate_instance_f32;
-
-
- /**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- */
- arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- */
- arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- */
- arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
- } arm_biquad_cas_df1_32x64_ins_q31;
-
-
- /**
- * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_stereo_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f64;
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_stereo_df2T_f32(
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f64(
- const arm_biquad_cascade_df2T_instance_f64 * S,
- float64_t * pSrc,
- float64_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_stereo_df2T_init_f32(
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f64(
- arm_biquad_cascade_df2T_instance_f64 * S,
- uint8_t numStages,
- float64_t * pCoeffs,
- float64_t * pState);
-
-
- /**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_f32;
-
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState);
-
-
- /**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState);
-
-
- /**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pkCoeffs,
- float32_t * pvCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pkCoeffs,
- q31_t * pvCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the Q15 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- */
- void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pkCoeffs,
- q15_t * pvCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the floating-point LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that controls filter coefficient updates. */
- } arm_lms_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that control filter coefficient updates. */
- float32_t energy; /**< saves previous frame energy. */
- float32_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q31_t *recipTable; /**< points to the reciprocal initial value table. */
- q31_t energy; /**< saves previous frame energy. */
- q31_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< Number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */
- q15_t energy; /**< saves previous frame energy. */
- q15_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q15;
-
-
- /**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Correlation of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
- void arm_correlate_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
-
- void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
-
- void arm_correlate_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
- void arm_correlate_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_correlate_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q15;
-
- /**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q7;
-
-
- /**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cos output.
- */
- void arm_sin_cos_f32(
- float32_t theta,
- float32_t * pSinVal,
- float32_t * pCosVal);
-
-
- /**
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cosine output.
- */
- void arm_sin_cos_q31(
- q31_t theta,
- q31_t * pSinVal,
- q31_t * pCosVal);
-
-
- /**
- * @brief Floating-point complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * S points to an instance of the PID control data structure. in
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- *
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- * A0 = Kp + Ki + Kd
- * A1 = (-Kp ) - (2 * Kd )
- * A2 = Kd
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup PID
- * @{
- */
-
- /**
- * @brief Process function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- */
- CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
- {
- float32_t out;
-
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
- out = (S->A0 * in) +
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q31 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
- CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
- {
- q63_t acc;
- q31_t out;
-
- /* acc = A0 * x[n] */
- acc = (q63_t) S->A0 * in;
-
- /* acc += A1 * x[n-1] */
- acc += (q63_t) S->A1 * S->state[0];
-
- /* acc += A2 * x[n-2] */
- acc += (q63_t) S->A2 * S->state[1];
-
- /* convert output to 1.31 format to add y[n-1] */
- out = (q31_t) (acc >> 31u);
-
- /* out += y[n-1] */
- out += S->state[2];
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
-
- /**
- * @brief Process function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
- {
- q63_t acc;
- q15_t out;
-
-#if defined (ARM_MATH_DSP)
- __SIMD32_TYPE *vstate;
-
- /* Implementation of PID controller */
-
- /* acc = A0 * x[n] */
- acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- vstate = __SIMD32_CONST(S->state);
- acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
-#else
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0) * in;
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0];
- acc += (q31_t) S->A2 * S->state[1];
-#endif
-
- /* acc += y[n-1] */
- acc += (q31_t) S->state[2] << 15;
-
- /* saturate the output */
- out = (q15_t) (__SSAT((acc >> 15), 16));
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
- /**
- * @} end of PID group
- */
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f64(
- const arm_matrix_instance_f64 * src,
- arm_matrix_instance_f64 * dst);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
- * in the two-phase orthogonal stator axis Ialpha and Ibeta.
- * When Ialpha is superposed with Ia as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
- * can be calculated using only Ia and Ib.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where Ia and Ib are the instantaneous stator phases and
- * pIalpha and pIbeta are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup clarke
- * @{
- */
-
- /**
- *
- * @brief Floating-point Clarke transform
- * @param[in] Ia input three-phase coordinate a
- * @param[in] Ib input three-phase coordinate b
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- */
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
- {
- /* Calculate pIalpha using the equation, pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
- }
-
-
- /**
- * @brief Clarke transform for Q31 version
- * @param[in] Ia input three-phase coordinate a
- * @param[in] Ib input three-phase coordinate b
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
- /* pIbeta is calculated by adding the intermediate products */
- *pIbeta = __QADD(product1, product2);
- }
-
- /**
- * @} end of clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where pIa and pIb are the instantaneous stator phases and
- * Ialpha and Ibeta are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_clarke
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Clarke transform
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] pIa points to output three-phase coordinate a
- * @param[out] pIb points to output three-phase coordinate b
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
- {
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
- *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
- }
-
-
- /**
- * @brief Inverse Clarke transform for Q31 version
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] pIa points to output three-phase coordinate a
- * @param[out] pIb points to output three-phase coordinate b
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
- /* pIb is calculated by subtracting the products */
- *pIb = __QSUB(product2, product1);
- }
-
- /**
- * @} end of inv_clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where Ialpha and Ibeta are the stator vector components,
- * pId and pIq are rotor vector components and cosVal and sinVal are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup park
- * @{
- */
-
- /**
- * @brief Floating-point Park transform
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] pId points to output rotor reference frame d
- * @param[out] pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * The function implements the forward Park transform.
- *
- */
- CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
- *pId = Ialpha * cosVal + Ibeta * sinVal;
-
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;
- }
-
-
- /**
- * @brief Park transform for Q31 version
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] pId points to output rotor reference frame d
- * @param[out] pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Ialpha * cosVal) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * sinVal) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Ialpha * sinVal) */
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * cosVal) */
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
- /* Calculate pId by adding the two intermediate products 1 and 2 */
- *pId = __QADD(product1, product2);
-
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
- *pIq = __QSUB(product4, product3);
- }
-
- /**
- * @} end of park group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where pIalpha and pIbeta are the stator vector components,
- * Id and Iq are rotor vector components and cosVal and sinVal are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_park
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Park transform
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
- *pIalpha = Id * cosVal - Iq * sinVal;
-
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
- *pIbeta = Id * sinVal + Iq * cosVal;
- }
-
-
- /**
- * @brief Inverse Park transform for Q31 version
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Id * cosVal) */
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * sinVal) */
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Id * sinVal) */
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * cosVal) */
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */
- *pIalpha = __QSUB(product1, product2);
-
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */
- *pIbeta = __QADD(product4, product3);
- }
-
- /**
- * @} end of Inverse park group
- */
-
-
- /**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- *
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- * where x0, x1 are nearest values of input x
- * y0, y1 are nearest values to output y
- *
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * S points to an instance of the Linear Interpolate function data structure.
- * x is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
- /**
- * @addtogroup LinearInterpolate
- * @{
- */
-
- /**
- * @brief Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
- * @param[in] x input sample to process
- * @return y processed output sample.
- *
- */
- CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
- {
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (int32_t) ((x - S->x1) / xSpacing);
-
- if (i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if ((uint32_t)i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues - 1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i + 1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
- }
-
- /* returns output value */
- return (y);
- }
-
-
- /**
- *
- * @brief Process function for the Q31 Linear Interpolation Function.
- * @param[in] pYData pointer to Q31 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
- q31_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q31_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (q31_t)0xFFF00000) >> 20);
-
- if (index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if (index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1u);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q15 Linear Interpolation Function.
- * @param[in] pYData pointer to Q15 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
- q15_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (int32_t)0xFFF00000) >> 20);
-
- if (index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if (index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (q15_t) (y >> 20);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q7 Linear Interpolation Function.
- * @param[in] pYData pointer to Q7 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
- CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
- q7_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q7_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- uint32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- if (x < 0)
- {
- return (pYData[0]);
- }
- index = (x >> 20) & 0xfff;
-
- if (index >= (nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (q7_t) (y >> 20);
- }
- }
-
- /**
- * @} end of LinearInterpolate group
- */
-
- /**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
- float32_t arm_sin_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q31_t arm_sin_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q15_t arm_sin_q15(
- q15_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
- float32_t arm_cos_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q31_t arm_cos_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q15_t arm_cos_q15(
- q15_t x);
-
-
- /**
- * @ingroup groupFastMath
- */
-
-
- /**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- *
- * x1 = x0 - f(x0)/f'(x0)
- *
- * where x1 is the current estimate,
- * x0 is the previous estimate, and
- * f'(x0) is the derivative of f() evaluated at x0.
- * For the square root function, the algorithm reduces to:
- *
- * x0 = in/2 [initial guess]
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]
- *
- */
-
-
- /**
- * @addtogroup SQRT
- * @{
- */
-
- /**
- * @brief Floating-point square root function.
- * @param[in] in input value.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * in is negative value and returns zero output for negative values.
- */
- CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
- float32_t in,
- float32_t * pOut)
- {
- if (in >= 0.0f)
- {
-
-#if (__FPU_USED == 1) && defined ( __CC_ARM )
- *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
- *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
- *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
- __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
- *pOut = sqrtf(in);
-#endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
- }
-
-
- /**
- * @brief Q31 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * in is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q31(
- q31_t in,
- q31_t * pOut);
-
-
- /**
- * @brief Q15 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * in is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q15(
- q15_t in,
- q15_t * pOut);
-
- /**
- * @} end of SQRT group
- */
-
-
- /**
- * @brief floating-point Circular write function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
-
- /**
- * @brief floating-point Circular Read function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == (int32_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q15 Circular write function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q15 Circular Read function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == (q15_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q7 Circular write function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q7 Circular Read function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == (q7_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
-
-
- /**
- * @brief Mean value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Mean value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Floating-point complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
-
-
- /**
- * @brief Q31 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
-
-
- /**
- * @brief Floating-point complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
-
-
- /**
- * @brief Q15 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Minimum value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] result is output pointer
- * @param[in] index is the array index of the minimum value in the input buffer.
- */
- void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
-
-
- /**
- * @brief Minimum value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[in] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * Algorithm
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- *
- * typedef struct
- * {
- * uint16_t numRows;
- * uint16_t numCols;
- * float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- *
- *
- * \par
- * where numRows specifies the number of rows in the table;
- * numCols specifies the number of columns in the table;
- * and pData points to an array of size numRows*numCols values.
- * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
- *
- * \par
- * Let (x, y) specify the desired interpolation point. Then define:
- *
- * XF = floor(x)
- * YF = floor(y)
- *
- * \par
- * The interpolated output point is computed as:
- *
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)
- *
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
- /**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
-
- /**
- *
- * @brief Floating-point bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate.
- * @param[in] Y interpolation coordinate.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
- {
- float32_t out;
- float32_t f00, f01, f10, f11;
- float32_t *pData = S->pData;
- int32_t xIndex, yIndex, index;
- float32_t xdiff, ydiff;
- float32_t b1, b2, b3, b4;
-
- xIndex = (int32_t) X;
- yIndex = (int32_t) Y;
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
- {
- return (0);
- }
-
- /* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
- /* Read two nearest points in X-direction */
- f00 = pData[index];
- f01 = pData[index + 1];
-
- /* Calculation of index for two nearest points in Y-direction */
- index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
- /* Read two nearest points in Y-direction */
- f10 = pData[index];
- f11 = pData[index + 1];
-
- /* Calculation of intermediate values */
- b1 = f00;
- b2 = f01 - f00;
- b3 = f10 - f00;
- b4 = f00 - f01 - f10 + f11;
-
- /* Calculation of fractional part in X */
- xdiff = X - xIndex;
-
- /* Calculation of fractional part in Y */
- ydiff = Y - yIndex;
-
- /* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
- /* return to application */
- return (out);
- }
-
-
- /**
- *
- * @brief Q31 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
- {
- q31_t out; /* Temporary output */
- q31_t acc = 0; /* output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q31_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* shift left xfract by 11 to keep 1.31 format */
- xfract = (X & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
- x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
- /* 20 bits for the fractional part */
- /* shift left yfract by 11 to keep 1.31 format */
- yfract = (Y & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
- y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* Convert acc to 1.31(q31) format */
- return ((q31_t)(acc << 2));
- }
-
-
- /**
- * @brief Q15 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q15_t x1, x2, y1, y2; /* Nearest output values */
- q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
- q15_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
- acc = ((q63_t) out * (0xFFFFF - yfract));
-
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
- acc += ((q63_t) out * (xfract));
-
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* acc is in 13.51 format and down shift acc by 36 times */
- /* Convert out to 1.15 format */
- return ((q15_t)(acc >> 36));
- }
-
-
- /**
- * @brief Q7 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q7_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
- out = ((x1 * (0xFFFFF - xfract)));
- acc = (((q63_t) out * (0xFFFFF - yfract)));
-
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
- out = ((x2 * (0xFFFFF - yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y1 * (0xFFFFF - xfract)));
- acc += (((q63_t) out * (yfract)));
-
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y2 * (yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
- return ((q7_t)(acc >> 40));
- }
-
- /**
- * @} end of BilinearInterpolate group
- */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if defined ( __CC_ARM )
- /* Enter low optimization region - place directly above function definition */
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("push") \
- _Pragma ("O1")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
- #define LOW_OPTIMIZATION_EXIT \
- _Pragma ("pop")
- #else
- #define LOW_OPTIMIZATION_EXIT
- #endif
-
- /* Enter low optimization region - place directly above function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
- #define LOW_OPTIMIZATION_ENTER \
- __attribute__(( optimize("-O1") ))
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
- /* Enter low optimization region - place directly above function definition */
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define LOW_OPTIMIZATION_EXIT
-
- /* Enter low optimization region - place directly above function definition */
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h
deleted file mode 100644
index 8b989f851ae7..000000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_compiler.h
- * @brief CMSIS compiler generic header file
- * @version V5.0.1
- * @date 30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include
-
-/*
- * ARM Compiler 4/5
- */
-#if defined ( __CC_ARM )
- #include "cmsis_armcc.h"
-
-
-/*
- * ARM Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
- #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
-
- #include
-
- #ifndef __NO_RETURN
- #define __NO_RETURN __noreturn
- #endif
- #ifndef __USED
- #define __USED __root
- #endif
- #ifndef __WEAK
- #define __WEAK __weak
- #endif
- #ifndef __UNALIGNED_UINT32
- __packed struct T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
- #define __ALIGNED(x)
- #endif
- #ifndef __PACKED
- #define __PACKED __packed
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT __packed struct
- #endif
-
-
-/*
- * TI ARM Compiler
- */
-#elif defined ( __TI_ARM__ )
- #include
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
- #endif
- #ifndef __USED
- #define __USED __attribute__((used))
- #endif
- #ifndef __WEAK
- #define __WEAK __attribute__((weak))
- #endif
- #ifndef __UNALIGNED_UINT32
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
- #endif
- #ifndef __PACKED
- #define __PACKED __attribute__((packed))
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed))
- #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
- /*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
- #endif
- #ifndef __USED
- #define __USED __attribute__((used))
- #endif
- #ifndef __WEAK
- #define __WEAK __attribute__((weak))
- #endif
- #ifndef __UNALIGNED_UINT32
- struct __packed__ T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #define __ALIGNED(x) __align(x)
- #endif
- #ifndef __PACKED
- #define __PACKED __packed__
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __packed__
- #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
- #include
-
- #ifndef __ASM
- #define __ASM _asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __NO_RETURN
- // NO RETURN is automatically detected hence no warning here
- #define __NO_RETURN
- #endif
- #ifndef __USED
- #warning No compiler specific solution for __USED. __USED is ignored.
- #define __USED
- #endif
- #ifndef __WEAK
- #define __WEAK __weak
- #endif
- #ifndef __UNALIGNED_UINT32
- @packed struct T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
- #define __ALIGNED(x)
- #endif
- #ifndef __PACKED
- #define __PACKED @packed
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT @packed struct
- #endif
-
-
-#else
- #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h
deleted file mode 100644
index 074cd7ab3279..000000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h
+++ /dev/null
@@ -1,1899 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_gcc.h
- * @brief CMSIS compiler GCC header file
- * @version V5.0.1
- * @date 02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __UNALIGNED_UINT32
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpacked"
-#pragma GCC diagnostic ignored "-Wattributes"
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-#pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- uint32_t result;
-
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- return(result);
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#else
- (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-//{
-// __ASM volatile ("nop");
-//}
-#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-//{
-// __ASM volatile ("wfi");
-//}
-#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-//{
-// __ASM volatile ("wfe");
-//}
-#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-//{
-// __ASM volatile ("sev");
-//}
-#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in integer value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in two unsigned short values.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief Reverse byte order in signed short value
- \details Reverses the byte order in a signed short value with sign extension to integer.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- int32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return(result);
-}
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief Load-Acquire (8 bit)
- \details Executes a LDAB instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire (16 bit)
- \details Executes a LDAH instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire (32 bit)
- \details Executes a LDA instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release (8 bit)
- \details Executes a STLB instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (16 bit)
- \details Executes a STLH instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (32 bit)
- \details Executes a STL instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Load-Acquire Exclusive (8 bit)
- \details Executes a LDAB exclusive instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (16 bit)
- \details Executes a LDAH exclusive instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (32 bit)
- \details Executes a LDA exclusive instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (8 bit)
- \details Executes a STLB exclusive instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (16 bit)
- \details Executes a STLH exclusive instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (32 bit)
- \details Executes a STL exclusive instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h
deleted file mode 100644
index 2da78d3983e8..000000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h
+++ /dev/null
@@ -1,2103 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (4U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000U
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
-#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt b/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt
deleted file mode 100644
index 8dada3edaf50..000000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt
+++ /dev/null
@@ -1,201 +0,0 @@
- Apache License
- Version 2.0, January 2004
- http://www.apache.org/licenses/
-
- TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
-
- 1. Definitions.
-
- "License" shall mean the terms and conditions for use, reproduction,
- and distribution as defined by Sections 1 through 9 of this document.
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- the copyright owner that is granting the License.
-
- "Legal Entity" shall mean the union of the acting entity and all
- other entities that control, are controlled by, or are under common
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- direction or management of such entity, whether by contract or
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- on behalf of whom a Contribution has been received by Licensor and
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- of the NOTICE file are for informational purposes only and
- do not modify the License. You may add Your own attribution
- notices within Derivative Works that You distribute, alongside
- or as an addendum to the NOTICE text from the Work, provided
- that such additional attribution notices cannot be construed
- as modifying the License.
-
- You may add Your own copyright statement to Your modifications and
- may provide additional or different license terms and conditions
- for use, reproduction, or distribution of Your modifications, or
- for any such Derivative Works as a whole, provided Your use,
- reproduction, and distribution of the Work otherwise complies with
- the conditions stated in this License.
-
- 5. Submission of Contributions. Unless You explicitly state otherwise,
- any Contribution intentionally submitted for inclusion in the Work
- by You to the Licensor shall be under the terms and conditions of
- this License, without any additional terms or conditions.
- Notwithstanding the above, nothing herein shall supersede or modify
- the terms of any separate license agreement you may have executed
- with Licensor regarding such Contributions.
-
- 6. Trademarks. This License does not grant permission to use the trade
- names, trademarks, service marks, or product names of the Licensor,
- except as required for reasonable and customary use in describing the
- origin of the Work and reproducing the content of the NOTICE file.
-
- 7. Disclaimer of Warranty. Unless required by applicable law or
- agreed to in writing, Licensor provides the Work (and each
- Contributor provides its Contributions) on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- implied, including, without limitation, any warranties or conditions
- of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
- PARTICULAR PURPOSE. You are solely responsible for determining the
- appropriateness of using or redistributing the Work and assume any
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- 8. Limitation of Liability. In no event and under no legal theory,
- whether in tort (including negligence), contract, or otherwise,
- unless required by applicable law (such as deliberate and grossly
- negligent acts) or agreed to in writing, shall any Contributor be
- liable to You for damages, including any direct, indirect, special,
- incidental, or consequential damages of any character arising as a
- result of this License or out of the use or inability to use the
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- other commercial damages or losses), even if such Contributor
- has been advised of the possibility of such damages.
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- the Work or Derivative Works thereof, You may choose to offer,
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- on Your own behalf and on Your sole responsibility, not on behalf
- of any other Contributor, and only if You agree to indemnify,
- defend, and hold each Contributor harmless for any liability
- incurred by, or claims asserted against, such Contributor by reason
- of your accepting any such warranty or additional liability.
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- APPENDIX: How to apply the Apache License to your work.
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- boilerplate notice, with the fields enclosed by brackets "{}"
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- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld
deleted file mode 100644
index 1c635478633e..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD51J18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-/*rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000*/
- rom (rx) : ORIGIN = 0x00004000, LENGTH = 0x0003C000
- ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
- bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
- qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
-
-/* The heap size used by the application. */
-HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x800;
-
-_srom = ORIGIN(rom);
-_lrom = LENGTH(rom);
-_erom = ORIGIN(rom) + LENGTH(rom);
-_sram = ORIGIN(ram);
-_lram = LENGTH(ram);
-_eram = ORIGIN(ram) + LENGTH(ram);
-
-/* Section Definitions */
-SECTIONS
-{
- .text :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors .vectors.*))
- *(.text .text.* .gnu.linkonce.t.*)
- *(.glue_7t) *(.glue_7)
- *(.rodata .rodata* .gnu.linkonce.r.*)
- *(.ARM.extab* .gnu.linkonce.armextab.*)
-
- /* Support C constructors, and C destructors in both user code
- and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
- KEEP(*(.init))
- . = ALIGN(4);
- __preinit_array_start = .;
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-
- . = ALIGN(4);
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-
- . = ALIGN(4);
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*crtend.o(.ctors))
-
- . = ALIGN(4);
- KEEP(*(.fini))
-
- . = ALIGN(4);
- __fini_array_start = .;
- KEEP (*(.fini_array))
- KEEP (*(SORT(.fini_array.*)))
- __fini_array_end = .;
-
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*crtend.o(.dtors))
-
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } > rom
-
- /* .ARM.exidx is sorted, so has to go in its own output section. */
- PROVIDE_HIDDEN (__exidx_start = .);
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > rom
- PROVIDE_HIDDEN (__exidx_end = .);
-
- . = ALIGN(4);
- _etext = .;
-
- .relocate : AT (_etext)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.ramfunc .ramfunc.*);
- *(.data .data.*);
- . = ALIGN(4);
- _erelocate = .;
- } > ram
-
- .bkupram (NOLOAD):
- {
- . = ALIGN(8);
- _sbkupram = .;
- *(.bkupram .bkupram.*);
- . = ALIGN(8);
- _ebkupram = .;
- } > bkupram
-
- .qspi (NOLOAD):
- {
- . = ALIGN(8);
- _sqspi = .;
- *(.qspi .qspi.*);
- . = ALIGN(8);
- _eqspi = .;
- } > qspi
-
- /* .bss section which is used for uninitialized data */
- .bss (NOLOAD) :
- {
- . = ALIGN(4);
- _sbss = . ;
- _szero = .;
- *(.bss .bss.*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = . ;
- _ezero = .;
- } > ram
-
- /* .heap section for syscalls */
- .heap (NOLOAD) :
- {
- . = ALIGN(4);
- _end = .;
- end = .;
- _heap_start = .;
- . = . + HEAP_SIZE;
- _heap_end = .;
- } > ram
-
- /* stack section */
- .stack (NOLOAD):
- {
- . = ALIGN(8);
- _sstack = .;
- . = . + STACK_SIZE;
- . = ALIGN(8);
- _estack = .;
- } > ram
-
- . = ALIGN(4);
- _end = . ;
-}
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h
deleted file mode 100644
index 80801fc12878..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * \brief Component version header file
- *
- * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
- *
- * \license_start
- *
- * \page License
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \license_stop
- *
- */
-
-#ifndef _COMPONENT_VERSION_H_INCLUDED
-#define _COMPONENT_VERSION_H_INCLUDED
-
-#define COMPONENT_VERSION_MAJOR 1
-#define COMPONENT_VERSION_MINOR 0
-
-//
-// The COMPONENT_VERSION define is composed of the major and the minor version number.
-//
-// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
-// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
-// is at least 8 digits long.
-//
-#define COMPONENT_VERSION 00010000
-
-//
-// The build number does not refer to the component, but to the build number
-// of the device pack that provides the component.
-//
-#define BUILD_NUMBER 70
-
-//
-// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
-//
-#define COMPONENT_VERSION_STRING "1.0"
-
-//
-// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
-//
-// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
-//
-// "%Y-%m-%d %H:%M:%S"
-//
-//
-#define COMPONENT_DATE_STRING "2017-08-09 09:59:41"
-
-#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
-
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h
deleted file mode 100644
index 24623d00acb1..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h
+++ /dev/null
@@ -1,598 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for AC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_AC_COMPONENT_
-#define _SAMD51_AC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR AC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_AC Analog Comparators */
-/*@{*/
-
-#define AC_U2501
-#define REV_AC 0x100
-
-/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
-#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
-
-#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
-#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
-#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
-#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
-#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
-
-/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
- uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
-#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
-
-#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
-#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
-#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
-#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
-#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
-#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos)
-#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
-#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */
-
-/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
- uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
- uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
- uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} AC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
-#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
-
-#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
-#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
-#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
-#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
-#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
-#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
-#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
-#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
-#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
-#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
-#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
-#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
-#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
-#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
-#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
-#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
-#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
-#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
-#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
-#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
-#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
-#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
-#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
-#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
-#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
-#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
-#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */
-
-/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
-#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
-#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
-#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
-#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
-#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
-#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos)
-#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
-#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
-#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
-#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
-#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos)
-#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
-#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */
-
-/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
-#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
-
-#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
-#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
-#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
-#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
-#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
-#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos)
-#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
-#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
-#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
-#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
-#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos)
-#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
-#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */
-
-/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
- __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN:1; /*!< bit: 4 Window x */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
-#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
-#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
-#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
-#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
-#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos)
-#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
-#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
-#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
-#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
-#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos)
-#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
-#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */
-
-/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
-#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
-
-#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
-#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
-#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
-#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
-#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
-#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos)
-#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
-#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
-#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
-#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
-#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
-#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
-#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */
-
-/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
- uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} AC_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
-#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
-
-#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
-#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
-#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
-#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
-#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
-#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos)
-#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
-#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */
-
-/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
-#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
-
-#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
-#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
-#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
-
-/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
- uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_WINCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
-#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
-
-#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
-#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
-#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
-#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
-#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
-#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
-#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
-#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
-#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */
-
-/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AC_SCALER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
-#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
-
-#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
-#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
-#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
-#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
-
-/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
- uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
- uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
- uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
- uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
- uint32_t :1; /*!< bit: 27 Reserved */
- uint32_t OUT:2; /*!< bit: 28..29 Output */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} AC_COMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
-#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
-
-#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
-#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
-#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
-#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
-#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
-#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
-#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
-#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
-#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
-#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
-#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
-#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
-#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
-#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
-#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
-#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
-#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
-#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
-#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
-#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
-#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
-#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
-#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
-#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
-#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
-#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
-#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
-#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
-#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */
-#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
-#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */
-#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */
-#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */
-#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
-#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
-#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
-#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
-#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
-#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
-#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
-#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
-
-/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
- uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
- uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :3; /*!< bit: 0.. 2 Reserved */
- uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} AC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
-#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
-#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
-#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
-#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
-#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
-#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
-#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
-#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
-#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
-#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
-#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
-
-/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */
- uint16_t :14; /*!< bit: 2..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} AC_CALIB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */
-#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */
-
-#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
-#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos)
-#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
-#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */
-
-/** \brief AC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
- __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
- __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
- __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
- __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
- __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
- RoReg8 Reserved1[0x1];
- __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
- RoReg8 Reserved2[0x2];
- __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
- RoReg8 Reserved3[0x8];
- __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
- __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */
-} Ac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_AC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h
deleted file mode 100644
index 33c38ae3f8fa..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h
+++ /dev/null
@@ -1,871 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for ADC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_ADC_COMPONENT_
-#define _SAMD51_ADC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR ADC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_ADC Analog Digital Converter */
-/*@{*/
-
-#define ADC_U2500
-#define REV_ADC 0x100
-
-/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t :1; /*!< bit: 2 Reserved */
- uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */
- uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
- uint16_t :4; /*!< bit: 11..14 Reserved */
- uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
-#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */
-
-#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
-#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
-#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
-#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
-#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
-#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
-#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
-#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
-#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */
-#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
-#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */
-#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
-#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */
-#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
-#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */
-#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
-#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
-#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
-#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
-#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
-#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
-#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
-#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
-#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
-#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
-#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos)
-#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */
-
-/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
- uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
- uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
- uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */
- uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
- uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */
-#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
-
-#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
-#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
-#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
-#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
-#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
-#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
-#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
-#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
-#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
-#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
-#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
-#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
-#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */
-
-/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */
-#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
-
-#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
-#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
-#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
-
-/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
- uint16_t :2; /*!< bit: 5.. 6 Reserved */
- uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */
- uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
- uint16_t :2; /*!< bit: 13..14 Reserved */
- uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_INPUTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */
-#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
-
-#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
-#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
-#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
-#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
-#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
-#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
-#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
-#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
-#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
-#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
-#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */
-#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
-#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */
-#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
-#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
-#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
-#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */
-#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
-#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
-#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */
-
-/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */
- uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */
- uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */
- uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */
- uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */
-#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */
-
-#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
-#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
-#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */
-#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
-#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
-#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
-#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
-#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
-#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */
-#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */
-#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */
-#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */
-#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */
-#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
-#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */
-#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */
-#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */
-#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
-#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
-#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */
-#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
-#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */
-
-/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_REFCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */
-#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
-
-#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
-#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
-#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
-#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
-#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */
-#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */
-#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */
-#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
-#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
-#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
-#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
-
-/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
- uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_AVGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */
-#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
-
-#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
-#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
-#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
-#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
-#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
-#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
-#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
-#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
-#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
-#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
-#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
-#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
-#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
-#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
-#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
-#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
-#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
-
-/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_SAMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
-#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
-
-#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
-#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
-#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
-#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
-#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
-#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */
-
-/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_WINLT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
-#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
-
-#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
-#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
-#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
-#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
-
-/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_WINUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
-#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
-
-#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
-#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
-#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
-#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
-
-/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_GAINCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */
-#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
-
-#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
-#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
-#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
-#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
-
-/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_OFFSETCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
-#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
-
-#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
-#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
-#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
-#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
-
-/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
- uint8_t START:1; /*!< bit: 1 Start ADC Conversion */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_SWTRIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */
-#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
-
-#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
-#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
-#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */
-#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)
-#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
-
-/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
-#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
-#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
-#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
-#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
-#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
-#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
-#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */
-
-/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
-#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
-
-#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
-#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
-#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
-#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
-#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
-#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
-#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */
-
-/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
- __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
- __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
- __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
-#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
-#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
-#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
-#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
-#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
-#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */
-
-/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} ADC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */
-#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */
-
-#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */
-#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
-#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */
-#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos)
-#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
-#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */
-
-/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
- uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */
- uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */
- uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */
- uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */
- uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */
- uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */
- uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */
- uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */
- uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
-#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
-#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
-#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
-#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
-#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
-#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
-#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
-#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
-#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
-#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
-#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
-#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
-#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
-#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
-#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
-#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
-#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
-#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
-#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
-#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
-#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
-#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
-#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
-#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
-#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
-
-/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_DSEQDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
-#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
-
-#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
-#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
-#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
-#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
-
-/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
- uint32_t CTRLB:1; /*!< bit: 1 Control B */
- uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
- uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
- uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
- uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
- uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
- uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
- uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
- uint32_t :22; /*!< bit: 9..30 Reserved */
- uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_DSEQCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
-#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
-
-#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */
-#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
-#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */
-#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
-#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */
-#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
-#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */
-#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
-#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
-#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
-#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
-#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
-#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
-#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
-#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */
-#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
-#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */
-#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
-#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
-#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
-#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
-
-/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
- uint32_t CTRLB:1; /*!< bit: 1 Control B */
- uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
- uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
- uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
- uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
- uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
- uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
- uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
- uint32_t :22; /*!< bit: 9..30 Reserved */
- uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} ADC_DSEQSTAT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
-#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
-
-#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */
-#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
-#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */
-#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
-#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */
-#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
-#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */
-#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
-#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
-#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
-#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
-#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
-#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
-#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
-#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */
-#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
-#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */
-#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
-#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
-#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
-#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
-
-/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_RESULT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */
-#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
-
-#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
-#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
-#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
-#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
-
-/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_RESS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */
-#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */
-
-#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */
-#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
-#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
-#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */
-
-/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} ADC_CALIB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */
-#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
-
-#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */
-#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
-#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
-#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
-#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
-#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
-#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */
-#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
-#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
-#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */
-
-/** \brief ADC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
- __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */
- __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */
- __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */
- __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */
- RoReg8 Reserved1[0x1];
- __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */
- __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */
- __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
- __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
- __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
- __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
- __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */
- RoReg8 Reserved2[0x17];
- __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */
- __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */
- __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
- __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */
- __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */
- __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
- __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
- __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */
- __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */
- RoReg8 Reserved3[0x2];
- __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */
- RoReg8 Reserved4[0x2];
- __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */
-} Adc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_ADC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h
deleted file mode 100644
index 5a74eac28b50..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for AES
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_AES_COMPONENT_
-#define _SAMD51_AES_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR AES */
-/* ========================================================================== */
-/** \addtogroup SAMD51_AES Advanced Encryption Standard */
-/*@{*/
-
-#define AES_U2238
-#define REV_AES 0x220
-
-/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
- uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
- uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
- uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
- uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
- uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
- uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
- uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} AES_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
-#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
-
-#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
-#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
-#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
-#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
-#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
-#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
-#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
-#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
-#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
-#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
-#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
-#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
-#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
-#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
-#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
-#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
-#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
-#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
-#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
-#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
-#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
-#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
-#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
-#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
-#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
-#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
-#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
-#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
-#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
-#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
-#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
-#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
-#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
-#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
-#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
-#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
-#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
-#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
-#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
-
-/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
- uint8_t NEWMSG:1; /*!< bit: 1 New message */
- uint8_t EOM:1; /*!< bit: 2 End of message */
- uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
-#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
-
-#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
-#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
-#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
-#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
-#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
-#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
-#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
-#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
-#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
-
-/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
- uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
-#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
-#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
-#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
-#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
-#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
-
-/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
- uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
-#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
-
-#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
-#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
-#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
-#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
-#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
-
-/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
- __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
-#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
-
-#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
-#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
-#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
-#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
-#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
-
-/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_DATABUFPTR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
-#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
-
-#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
-#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
-#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
-#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
-
-/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} AES_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
-#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
-
-#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
-#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
-#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
-
-/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_KEYWORD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
-#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
-#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
-
-/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_INDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
-#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
-#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
-
-/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_INTVECTV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
-#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
-#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
-
-/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_HASHKEY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
-#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
-#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
-
-/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_GHASH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
-#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
-#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
-
-/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_CIPLEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
-#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
-#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
-
-/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- uint32_t reg; /*!< Type used for register access */
-} AES_RANDSEED_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
-#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
-#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
-
-/** \brief AES hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
- __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
- __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
- __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
- __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
- __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
- RoReg8 Reserved1[0x2];
- __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
- RoReg8 Reserved2[0xC];
- __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
- __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
- RoReg8 Reserved3[0x10];
- __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
- __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
- RoReg8 Reserved4[0x4];
- __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
- __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
-} Aes;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_AES_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h
deleted file mode 100644
index 9d6754998c61..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h
+++ /dev/null
@@ -1,3207 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for CAN
- *
- * Copyright (c) 2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CAN_COMPONENT_
-#define _SAMD51_CAN_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR CAN */
-/* ========================================================================== */
-/** \addtogroup SAMD51_CAN Control Area Network */
-/*@{*/
-
-#define CAN_U2003
-#define REV_CAN 0x321
-
-/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :20; /*!< bit: 0..19 Reserved */
- uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */
- uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */
- uint32_t REL:4; /*!< bit: 28..31 Core Release */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_CREL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */
-#define CAN_CREL_RESETVALUE 0x32100000u /**< \brief (CAN_CREL reset_value) Core Release */
-
-#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */
-#define CAN_CREL_SUBSTEP_Msk (0xFu << CAN_CREL_SUBSTEP_Pos)
-#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos))
-#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */
-#define CAN_CREL_STEP_Msk (0xFu << CAN_CREL_STEP_Pos)
-#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos))
-#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */
-#define CAN_CREL_REL_Msk (0xFu << CAN_CREL_REL_Pos)
-#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos))
-#define CAN_CREL_MASK 0xFFF00000u /**< \brief (CAN_CREL) MASK Register */
-
-/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ENDN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */
-#define CAN_ENDN_RESETVALUE 0x87654321u /**< \brief (CAN_ENDN reset_value) Endian */
-
-#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */
-#define CAN_ENDN_ETV_Msk (0xFFFFFFFFu << CAN_ENDN_ETV_Pos)
-#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos))
-#define CAN_ENDN_MASK 0xFFFFFFFFu /**< \brief (CAN_ENDN) MASK Register */
-
-/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_MRCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */
-#define CAN_MRCFG_RESETVALUE 0x00000002u /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */
-
-#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */
-#define CAN_MRCFG_QOS_Msk (0x3u << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos))
-#define CAN_MRCFG_QOS_DISABLE_Val 0x0u /**< \brief (CAN_MRCFG) Background (no sensitive operation) */
-#define CAN_MRCFG_QOS_LOW_Val 0x1u /**< \brief (CAN_MRCFG) Sensitive Bandwidth */
-#define CAN_MRCFG_QOS_MEDIUM_Val 0x2u /**< \brief (CAN_MRCFG) Sensitive Latency */
-#define CAN_MRCFG_QOS_HIGH_Val 0x3u /**< \brief (CAN_MRCFG) Critical Latency */
-#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_MASK 0x00000003u /**< \brief (CAN_MRCFG) MASK Register */
-
-/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */
- uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */
- uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */
- uint32_t :2; /*!< bit: 21..22 Reserved */
- uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_DBTP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */
-#define CAN_DBTP_RESETVALUE 0x00000A33u /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */
-
-#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */
-#define CAN_DBTP_DSJW_Msk (0xFu << CAN_DBTP_DSJW_Pos)
-#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos))
-#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */
-#define CAN_DBTP_DTSEG2_Msk (0xFu << CAN_DBTP_DTSEG2_Pos)
-#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos))
-#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */
-#define CAN_DBTP_DTSEG1_Msk (0x1Fu << CAN_DBTP_DTSEG1_Pos)
-#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos))
-#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */
-#define CAN_DBTP_DBRP_Msk (0x1Fu << CAN_DBTP_DBRP_Pos)
-#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos))
-#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */
-#define CAN_DBTP_TDC (0x1u << CAN_DBTP_TDC_Pos)
-#define CAN_DBTP_MASK 0x009F1FFFu /**< \brief (CAN_DBTP) MASK Register */
-
-/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */
- uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */
- uint32_t RX:1; /*!< bit: 7 Receive Pin */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TEST_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */
-#define CAN_TEST_RESETVALUE 0x00000000u /**< \brief (CAN_TEST reset_value) Test */
-
-#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */
-#define CAN_TEST_LBCK (0x1u << CAN_TEST_LBCK_Pos)
-#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */
-#define CAN_TEST_TX_Msk (0x3u << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos))
-#define CAN_TEST_TX_CORE_Val 0x0u /**< \brief (CAN_TEST) TX controlled by CAN core */
-#define CAN_TEST_TX_SAMPLE_Val 0x1u /**< \brief (CAN_TEST) TX monitoring sample point */
-#define CAN_TEST_TX_DOMINANT_Val 0x2u /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */
-#define CAN_TEST_TX_RECESSIVE_Val 0x3u /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */
-#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos)
-#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */
-#define CAN_TEST_RX (0x1u << CAN_TEST_RX_Pos)
-#define CAN_TEST_MASK 0x000000F0u /**< \brief (CAN_TEST) MASK Register */
-
-/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */
- uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RWD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */
-#define CAN_RWD_RESETVALUE 0x00000000u /**< \brief (CAN_RWD reset_value) RAM Watchdog */
-
-#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */
-#define CAN_RWD_WDC_Msk (0xFFu << CAN_RWD_WDC_Pos)
-#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos))
-#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */
-#define CAN_RWD_WDV_Msk (0xFFu << CAN_RWD_WDV_Pos)
-#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos))
-#define CAN_RWD_MASK 0x0000FFFFu /**< \brief (CAN_RWD) MASK Register */
-
-/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INIT:1; /*!< bit: 0 Initialization */
- uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */
- uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */
- uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */
- uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */
- uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */
- uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */
- uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */
- uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */
- uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */
- uint32_t :2; /*!< bit: 10..11 Reserved */
- uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */
- uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */
- uint32_t TXP:1; /*!< bit: 14 Transmit Pause */
- uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_CCCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */
-#define CAN_CCCR_RESETVALUE 0x00000001u /**< \brief (CAN_CCCR reset_value) CC Control */
-
-#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */
-#define CAN_CCCR_INIT (0x1u << CAN_CCCR_INIT_Pos)
-#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */
-#define CAN_CCCR_CCE (0x1u << CAN_CCCR_CCE_Pos)
-#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */
-#define CAN_CCCR_ASM (0x1u << CAN_CCCR_ASM_Pos)
-#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */
-#define CAN_CCCR_CSA (0x1u << CAN_CCCR_CSA_Pos)
-#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */
-#define CAN_CCCR_CSR (0x1u << CAN_CCCR_CSR_Pos)
-#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */
-#define CAN_CCCR_MON (0x1u << CAN_CCCR_MON_Pos)
-#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */
-#define CAN_CCCR_DAR (0x1u << CAN_CCCR_DAR_Pos)
-#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */
-#define CAN_CCCR_TEST (0x1u << CAN_CCCR_TEST_Pos)
-#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */
-#define CAN_CCCR_FDOE (0x1u << CAN_CCCR_FDOE_Pos)
-#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */
-#define CAN_CCCR_BRSE (0x1u << CAN_CCCR_BRSE_Pos)
-#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */
-#define CAN_CCCR_PXHD (0x1u << CAN_CCCR_PXHD_Pos)
-#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */
-#define CAN_CCCR_EFBI (0x1u << CAN_CCCR_EFBI_Pos)
-#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */
-#define CAN_CCCR_TXP (0x1u << CAN_CCCR_TXP_Pos)
-#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */
-#define CAN_CCCR_NISO (0x1u << CAN_CCCR_NISO_Pos)
-#define CAN_CCCR_MASK 0x0000F3FFu /**< \brief (CAN_CCCR) MASK Register */
-
-/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */
- uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */
- uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_NBTP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */
-#define CAN_NBTP_RESETVALUE 0x06000A03u /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */
-
-#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */
-#define CAN_NBTP_NTSEG2_Msk (0x7Fu << CAN_NBTP_NTSEG2_Pos)
-#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos))
-#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */
-#define CAN_NBTP_NTSEG1_Msk (0xFFu << CAN_NBTP_NTSEG1_Pos)
-#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos))
-#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */
-#define CAN_NBTP_NBRP_Msk (0x1FFu << CAN_NBTP_NBRP_Pos)
-#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos))
-#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */
-#define CAN_NBTP_NSJW_Msk (0x7Fu << CAN_NBTP_NSJW_Pos)
-#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos))
-#define CAN_NBTP_MASK 0xFFFFFF7Fu /**< \brief (CAN_NBTP) MASK Register */
-
-/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */
- uint32_t :14; /*!< bit: 2..15 Reserved */
- uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TSCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */
-#define CAN_TSCC_RESETVALUE 0x00000000u /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */
-
-#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */
-#define CAN_TSCC_TSS_Msk (0x3u << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos))
-#define CAN_TSCC_TSS_ZERO_Val 0x0u /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */
-#define CAN_TSCC_TSS_INC_Val 0x1u /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */
-#define CAN_TSCC_TSS_EXT_Val 0x2u /**< \brief (CAN_TSCC) External timestamp counter value used */
-#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */
-#define CAN_TSCC_TCP_Msk (0xFu << CAN_TSCC_TCP_Pos)
-#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos))
-#define CAN_TSCC_MASK 0x000F0003u /**< \brief (CAN_TSCC) MASK Register */
-
-/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TSCV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */
-#define CAN_TSCV_RESETVALUE 0x00000000u /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */
-
-#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */
-#define CAN_TSCV_TSC_Msk (0xFFFFu << CAN_TSCV_TSC_Pos)
-#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos))
-#define CAN_TSCV_MASK 0x0000FFFFu /**< \brief (CAN_TSCV) MASK Register */
-
-/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */
- uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */
- uint32_t :13; /*!< bit: 3..15 Reserved */
- uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TOCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */
-#define CAN_TOCC_RESETVALUE 0xFFFF0000u /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */
-
-#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */
-#define CAN_TOCC_ETOC (0x1u << CAN_TOCC_ETOC_Pos)
-#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */
-#define CAN_TOCC_TOS_Msk (0x3u << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos))
-#define CAN_TOCC_TOS_CONT_Val 0x0u /**< \brief (CAN_TOCC) Continuout operation */
-#define CAN_TOCC_TOS_TXEF_Val 0x1u /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */
-#define CAN_TOCC_TOS_RXF0_Val 0x2u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */
-#define CAN_TOCC_TOS_RXF1_Val 0x3u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */
-#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */
-#define CAN_TOCC_TOP_Msk (0xFFFFu << CAN_TOCC_TOP_Pos)
-#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos))
-#define CAN_TOCC_MASK 0xFFFF0007u /**< \brief (CAN_TOCC) MASK Register */
-
-/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TOCV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */
-#define CAN_TOCV_RESETVALUE 0x0000FFFFu /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */
-
-#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */
-#define CAN_TOCV_TOC_Msk (0xFFFFu << CAN_TOCV_TOC_Pos)
-#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos))
-#define CAN_TOCV_MASK 0x0000FFFFu /**< \brief (CAN_TOCV) MASK Register */
-
-/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */
- uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */
- uint32_t RP:1; /*!< bit: 15 Receive Error Passive */
- uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ECR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */
-#define CAN_ECR_RESETVALUE 0x00000000u /**< \brief (CAN_ECR reset_value) Error Counter */
-
-#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */
-#define CAN_ECR_TEC_Msk (0xFFu << CAN_ECR_TEC_Pos)
-#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos))
-#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */
-#define CAN_ECR_REC_Msk (0x7Fu << CAN_ECR_REC_Pos)
-#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos))
-#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */
-#define CAN_ECR_RP (0x1u << CAN_ECR_RP_Pos)
-#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */
-#define CAN_ECR_CEL_Msk (0xFFu << CAN_ECR_CEL_Pos)
-#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos))
-#define CAN_ECR_MASK 0x00FFFFFFu /**< \brief (CAN_ECR) MASK Register */
-
-/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */
- uint32_t ACT:2; /*!< bit: 3.. 4 Activity */
- uint32_t EP:1; /*!< bit: 5 Error Passive */
- uint32_t EW:1; /*!< bit: 6 Warning Status */
- uint32_t BO:1; /*!< bit: 7 Bus_Off Status */
- uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */
- uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */
- uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */
- uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */
- uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_PSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */
-#define CAN_PSR_RESETVALUE 0x00000707u /**< \brief (CAN_PSR reset_value) Protocol Status */
-
-#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */
-#define CAN_PSR_LEC_Msk (0x7u << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos))
-#define CAN_PSR_LEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */
-#define CAN_PSR_LEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */
-#define CAN_PSR_LEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */
-#define CAN_PSR_LEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */
-#define CAN_PSR_LEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */
-#define CAN_PSR_LEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */
-#define CAN_PSR_LEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */
-#define CAN_PSR_LEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */
-#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos)
-#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */
-#define CAN_PSR_ACT_Msk (0x3u << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos))
-#define CAN_PSR_ACT_SYNC_Val 0x0u /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */
-#define CAN_PSR_ACT_IDLE_Val 0x1u /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */
-#define CAN_PSR_ACT_RX_Val 0x2u /**< \brief (CAN_PSR) Node is operating as receiver */
-#define CAN_PSR_ACT_TX_Val 0x3u /**< \brief (CAN_PSR) Node is operating as transmitter */
-#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos)
-#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */
-#define CAN_PSR_EP (0x1u << CAN_PSR_EP_Pos)
-#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */
-#define CAN_PSR_EW (0x1u << CAN_PSR_EW_Pos)
-#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */
-#define CAN_PSR_BO (0x1u << CAN_PSR_BO_Pos)
-#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */
-#define CAN_PSR_DLEC_Msk (0x7u << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos))
-#define CAN_PSR_DLEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */
-#define CAN_PSR_DLEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */
-#define CAN_PSR_DLEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */
-#define CAN_PSR_DLEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */
-#define CAN_PSR_DLEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */
-#define CAN_PSR_DLEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */
-#define CAN_PSR_DLEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */
-#define CAN_PSR_DLEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */
-#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */
-#define CAN_PSR_RESI (0x1u << CAN_PSR_RESI_Pos)
-#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */
-#define CAN_PSR_RBRS (0x1u << CAN_PSR_RBRS_Pos)
-#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */
-#define CAN_PSR_RFDF (0x1u << CAN_PSR_RFDF_Pos)
-#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */
-#define CAN_PSR_PXE (0x1u << CAN_PSR_PXE_Pos)
-#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */
-#define CAN_PSR_TDCV_Msk (0x7Fu << CAN_PSR_TDCV_Pos)
-#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos))
-#define CAN_PSR_MASK 0x007F7FFFu /**< \brief (CAN_PSR) MASK Register */
-
-/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */
- uint32_t :17; /*!< bit: 15..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TDCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */
-#define CAN_TDCR_RESETVALUE 0x00000000u /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */
-
-#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */
-#define CAN_TDCR_TDCF_Msk (0x7Fu << CAN_TDCR_TDCF_Pos)
-#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos))
-#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */
-#define CAN_TDCR_TDCO_Msk (0x7Fu << CAN_TDCR_TDCO_Pos)
-#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos))
-#define CAN_TDCR_MASK 0x00007F7Fu /**< \brief (CAN_TDCR) MASK Register */
-
-/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */
- uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */
- uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */
- uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */
- uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */
- uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */
- uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */
- uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */
- uint32_t HPM:1; /*!< bit: 8 High Priority Message */
- uint32_t TC:1; /*!< bit: 9 Timestamp Completed */
- uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */
- uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */
- uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */
- uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */
- uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */
- uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */
- uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */
- uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */
- uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */
- uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */
- uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */
- uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */
- uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */
- uint32_t EP:1; /*!< bit: 23 Error Passive */
- uint32_t EW:1; /*!< bit: 24 Warning Status */
- uint32_t BO:1; /*!< bit: 25 Bus_Off Status */
- uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */
- uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */
- uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */
- uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_IR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */
-#define CAN_IR_RESETVALUE 0x00000000u /**< \brief (CAN_IR reset_value) Interrupt */
-
-#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */
-#define CAN_IR_RF0N (0x1u << CAN_IR_RF0N_Pos)
-#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */
-#define CAN_IR_RF0W (0x1u << CAN_IR_RF0W_Pos)
-#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */
-#define CAN_IR_RF0F (0x1u << CAN_IR_RF0F_Pos)
-#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */
-#define CAN_IR_RF0L (0x1u << CAN_IR_RF0L_Pos)
-#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */
-#define CAN_IR_RF1N (0x1u << CAN_IR_RF1N_Pos)
-#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */
-#define CAN_IR_RF1W (0x1u << CAN_IR_RF1W_Pos)
-#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */
-#define CAN_IR_RF1F (0x1u << CAN_IR_RF1F_Pos)
-#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */
-#define CAN_IR_RF1L (0x1u << CAN_IR_RF1L_Pos)
-#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */
-#define CAN_IR_HPM (0x1u << CAN_IR_HPM_Pos)
-#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */
-#define CAN_IR_TC (0x1u << CAN_IR_TC_Pos)
-#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */
-#define CAN_IR_TCF (0x1u << CAN_IR_TCF_Pos)
-#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */
-#define CAN_IR_TFE (0x1u << CAN_IR_TFE_Pos)
-#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */
-#define CAN_IR_TEFN (0x1u << CAN_IR_TEFN_Pos)
-#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */
-#define CAN_IR_TEFW (0x1u << CAN_IR_TEFW_Pos)
-#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */
-#define CAN_IR_TEFF (0x1u << CAN_IR_TEFF_Pos)
-#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */
-#define CAN_IR_TEFL (0x1u << CAN_IR_TEFL_Pos)
-#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */
-#define CAN_IR_TSW (0x1u << CAN_IR_TSW_Pos)
-#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */
-#define CAN_IR_MRAF (0x1u << CAN_IR_MRAF_Pos)
-#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */
-#define CAN_IR_TOO (0x1u << CAN_IR_TOO_Pos)
-#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */
-#define CAN_IR_DRX (0x1u << CAN_IR_DRX_Pos)
-#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */
-#define CAN_IR_BEC (0x1u << CAN_IR_BEC_Pos)
-#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */
-#define CAN_IR_BEU (0x1u << CAN_IR_BEU_Pos)
-#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */
-#define CAN_IR_ELO (0x1u << CAN_IR_ELO_Pos)
-#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */
-#define CAN_IR_EP (0x1u << CAN_IR_EP_Pos)
-#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */
-#define CAN_IR_EW (0x1u << CAN_IR_EW_Pos)
-#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */
-#define CAN_IR_BO (0x1u << CAN_IR_BO_Pos)
-#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */
-#define CAN_IR_WDI (0x1u << CAN_IR_WDI_Pos)
-#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */
-#define CAN_IR_PEA (0x1u << CAN_IR_PEA_Pos)
-#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */
-#define CAN_IR_PED (0x1u << CAN_IR_PED_Pos)
-#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */
-#define CAN_IR_ARA (0x1u << CAN_IR_ARA_Pos)
-#define CAN_IR_MASK 0x3FFFFFFFu /**< \brief (CAN_IR) MASK Register */
-
-/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */
- uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */
- uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */
- uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */
- uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */
- uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */
- uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */
- uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */
- uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */
- uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */
- uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */
- uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */
- uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */
- uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */
- uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */
- uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */
- uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */
- uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */
- uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */
- uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */
- uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */
- uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */
- uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */
- uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */
- uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */
- uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */
- uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */
- uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */
- uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */
- uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_IE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */
-#define CAN_IE_RESETVALUE 0x00000000u /**< \brief (CAN_IE reset_value) Interrupt Enable */
-
-#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */
-#define CAN_IE_RF0NE (0x1u << CAN_IE_RF0NE_Pos)
-#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */
-#define CAN_IE_RF0WE (0x1u << CAN_IE_RF0WE_Pos)
-#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */
-#define CAN_IE_RF0FE (0x1u << CAN_IE_RF0FE_Pos)
-#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */
-#define CAN_IE_RF0LE (0x1u << CAN_IE_RF0LE_Pos)
-#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */
-#define CAN_IE_RF1NE (0x1u << CAN_IE_RF1NE_Pos)
-#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */
-#define CAN_IE_RF1WE (0x1u << CAN_IE_RF1WE_Pos)
-#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */
-#define CAN_IE_RF1FE (0x1u << CAN_IE_RF1FE_Pos)
-#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */
-#define CAN_IE_RF1LE (0x1u << CAN_IE_RF1LE_Pos)
-#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */
-#define CAN_IE_HPME (0x1u << CAN_IE_HPME_Pos)
-#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */
-#define CAN_IE_TCE (0x1u << CAN_IE_TCE_Pos)
-#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */
-#define CAN_IE_TCFE (0x1u << CAN_IE_TCFE_Pos)
-#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */
-#define CAN_IE_TFEE (0x1u << CAN_IE_TFEE_Pos)
-#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */
-#define CAN_IE_TEFNE (0x1u << CAN_IE_TEFNE_Pos)
-#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
-#define CAN_IE_TEFWE (0x1u << CAN_IE_TEFWE_Pos)
-#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */
-#define CAN_IE_TEFFE (0x1u << CAN_IE_TEFFE_Pos)
-#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */
-#define CAN_IE_TEFLE (0x1u << CAN_IE_TEFLE_Pos)
-#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */
-#define CAN_IE_TSWE (0x1u << CAN_IE_TSWE_Pos)
-#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */
-#define CAN_IE_MRAFE (0x1u << CAN_IE_MRAFE_Pos)
-#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */
-#define CAN_IE_TOOE (0x1u << CAN_IE_TOOE_Pos)
-#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */
-#define CAN_IE_DRXE (0x1u << CAN_IE_DRXE_Pos)
-#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */
-#define CAN_IE_BECE (0x1u << CAN_IE_BECE_Pos)
-#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */
-#define CAN_IE_BEUE (0x1u << CAN_IE_BEUE_Pos)
-#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */
-#define CAN_IE_ELOE (0x1u << CAN_IE_ELOE_Pos)
-#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */
-#define CAN_IE_EPE (0x1u << CAN_IE_EPE_Pos)
-#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */
-#define CAN_IE_EWE (0x1u << CAN_IE_EWE_Pos)
-#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */
-#define CAN_IE_BOE (0x1u << CAN_IE_BOE_Pos)
-#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */
-#define CAN_IE_WDIE (0x1u << CAN_IE_WDIE_Pos)
-#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */
-#define CAN_IE_PEAE (0x1u << CAN_IE_PEAE_Pos)
-#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */
-#define CAN_IE_PEDE (0x1u << CAN_IE_PEDE_Pos)
-#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */
-#define CAN_IE_ARAE (0x1u << CAN_IE_ARAE_Pos)
-#define CAN_IE_MASK 0x3FFFFFFFu /**< \brief (CAN_IE) MASK Register */
-
-/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */
- uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */
- uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */
- uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */
- uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */
- uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */
- uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */
- uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */
- uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */
- uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */
- uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */
- uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */
- uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */
- uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */
- uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */
- uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */
- uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */
- uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */
- uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */
- uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */
- uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */
- uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */
- uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */
- uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */
- uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */
- uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */
- uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */
- uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */
- uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */
- uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ILS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */
-#define CAN_ILS_RESETVALUE 0x00000000u /**< \brief (CAN_ILS reset_value) Interrupt Line Select */
-
-#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */
-#define CAN_ILS_RF0NL (0x1u << CAN_ILS_RF0NL_Pos)
-#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */
-#define CAN_ILS_RF0WL (0x1u << CAN_ILS_RF0WL_Pos)
-#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */
-#define CAN_ILS_RF0FL (0x1u << CAN_ILS_RF0FL_Pos)
-#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */
-#define CAN_ILS_RF0LL (0x1u << CAN_ILS_RF0LL_Pos)
-#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */
-#define CAN_ILS_RF1NL (0x1u << CAN_ILS_RF1NL_Pos)
-#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */
-#define CAN_ILS_RF1WL (0x1u << CAN_ILS_RF1WL_Pos)
-#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */
-#define CAN_ILS_RF1FL (0x1u << CAN_ILS_RF1FL_Pos)
-#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */
-#define CAN_ILS_RF1LL (0x1u << CAN_ILS_RF1LL_Pos)
-#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */
-#define CAN_ILS_HPML (0x1u << CAN_ILS_HPML_Pos)
-#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */
-#define CAN_ILS_TCL (0x1u << CAN_ILS_TCL_Pos)
-#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */
-#define CAN_ILS_TCFL (0x1u << CAN_ILS_TCFL_Pos)
-#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */
-#define CAN_ILS_TFEL (0x1u << CAN_ILS_TFEL_Pos)
-#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */
-#define CAN_ILS_TEFNL (0x1u << CAN_ILS_TEFNL_Pos)
-#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
-#define CAN_ILS_TEFWL (0x1u << CAN_ILS_TEFWL_Pos)
-#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */
-#define CAN_ILS_TEFFL (0x1u << CAN_ILS_TEFFL_Pos)
-#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */
-#define CAN_ILS_TEFLL (0x1u << CAN_ILS_TEFLL_Pos)
-#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */
-#define CAN_ILS_TSWL (0x1u << CAN_ILS_TSWL_Pos)
-#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */
-#define CAN_ILS_MRAFL (0x1u << CAN_ILS_MRAFL_Pos)
-#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */
-#define CAN_ILS_TOOL (0x1u << CAN_ILS_TOOL_Pos)
-#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */
-#define CAN_ILS_DRXL (0x1u << CAN_ILS_DRXL_Pos)
-#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */
-#define CAN_ILS_BECL (0x1u << CAN_ILS_BECL_Pos)
-#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */
-#define CAN_ILS_BEUL (0x1u << CAN_ILS_BEUL_Pos)
-#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */
-#define CAN_ILS_ELOL (0x1u << CAN_ILS_ELOL_Pos)
-#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */
-#define CAN_ILS_EPL (0x1u << CAN_ILS_EPL_Pos)
-#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */
-#define CAN_ILS_EWL (0x1u << CAN_ILS_EWL_Pos)
-#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */
-#define CAN_ILS_BOL (0x1u << CAN_ILS_BOL_Pos)
-#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */
-#define CAN_ILS_WDIL (0x1u << CAN_ILS_WDIL_Pos)
-#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */
-#define CAN_ILS_PEAL (0x1u << CAN_ILS_PEAL_Pos)
-#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */
-#define CAN_ILS_PEDL (0x1u << CAN_ILS_PEDL_Pos)
-#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */
-#define CAN_ILS_ARAL (0x1u << CAN_ILS_ARAL_Pos)
-#define CAN_ILS_MASK 0x3FFFFFFFu /**< \brief (CAN_ILS) MASK Register */
-
-/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */
- uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_ILE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */
-#define CAN_ILE_RESETVALUE 0x00000000u /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */
-
-#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */
-#define CAN_ILE_EINT0 (0x1u << CAN_ILE_EINT0_Pos)
-#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */
-#define CAN_ILE_EINT1 (0x1u << CAN_ILE_EINT1_Pos)
-#define CAN_ILE_MASK 0x00000003u /**< \brief (CAN_ILE) MASK Register */
-
-/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */
- uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */
- uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */
- uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_GFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */
-#define CAN_GFC_RESETVALUE 0x00000000u /**< \brief (CAN_GFC reset_value) Global Filter Configuration */
-
-#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */
-#define CAN_GFC_RRFE (0x1u << CAN_GFC_RRFE_Pos)
-#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */
-#define CAN_GFC_RRFS (0x1u << CAN_GFC_RRFS_Pos)
-#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */
-#define CAN_GFC_ANFE_Msk (0x3u << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos))
-#define CAN_GFC_ANFE_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
-#define CAN_GFC_ANFE_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
-#define CAN_GFC_ANFE_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */
-#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */
-#define CAN_GFC_ANFS_Msk (0x3u << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos))
-#define CAN_GFC_ANFS_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
-#define CAN_GFC_ANFS_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
-#define CAN_GFC_ANFS_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */
-#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_MASK 0x0000003Fu /**< \brief (CAN_GFC) MASK Register */
-
-/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */
- uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_SIDFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */
-#define CAN_SIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */
-
-#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */
-#define CAN_SIDFC_FLSSA_Msk (0xFFFFu << CAN_SIDFC_FLSSA_Pos)
-#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos))
-#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */
-#define CAN_SIDFC_LSS_Msk (0xFFu << CAN_SIDFC_LSS_Pos)
-#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos))
-#define CAN_SIDFC_MASK 0x00FFFFFFu /**< \brief (CAN_SIDFC) MASK Register */
-
-/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */
- uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */
-#define CAN_XIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */
-
-#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */
-#define CAN_XIDFC_FLESA_Msk (0xFFFFu << CAN_XIDFC_FLESA_Pos)
-#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos))
-#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */
-#define CAN_XIDFC_LSE_Msk (0x7Fu << CAN_XIDFC_LSE_Pos)
-#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos))
-#define CAN_XIDFC_MASK 0x007FFFFFu /**< \brief (CAN_XIDFC) MASK Register */
-
-/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */
- uint32_t :3; /*!< bit: 29..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDAM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */
-#define CAN_XIDAM_RESETVALUE 0x1FFFFFFFu /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */
-
-#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */
-#define CAN_XIDAM_EIDM_Msk (0x1FFFFFFFu << CAN_XIDAM_EIDM_Pos)
-#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos))
-#define CAN_XIDAM_MASK 0x1FFFFFFFu /**< \brief (CAN_XIDAM) MASK Register */
-
-/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */
- uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */
- uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */
- uint32_t FLST:1; /*!< bit: 15 Filter List */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_HPMS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */
-#define CAN_HPMS_RESETVALUE 0x00000000u /**< \brief (CAN_HPMS reset_value) High Priority Message Status */
-
-#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */
-#define CAN_HPMS_BIDX_Msk (0x3Fu << CAN_HPMS_BIDX_Pos)
-#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos))
-#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */
-#define CAN_HPMS_MSI_Msk (0x3u << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos))
-#define CAN_HPMS_MSI_NONE_Val 0x0u /**< \brief (CAN_HPMS) No FIFO selected */
-#define CAN_HPMS_MSI_LOST_Val 0x1u /**< \brief (CAN_HPMS) FIFO message lost */
-#define CAN_HPMS_MSI_FIFO0_Val 0x2u /**< \brief (CAN_HPMS) Message stored in FIFO 0 */
-#define CAN_HPMS_MSI_FIFO1_Val 0x3u /**< \brief (CAN_HPMS) Message stored in FIFO 1 */
-#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */
-#define CAN_HPMS_FIDX_Msk (0x7Fu << CAN_HPMS_FIDX_Pos)
-#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos))
-#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */
-#define CAN_HPMS_FLST (0x1u << CAN_HPMS_FLST_Pos)
-#define CAN_HPMS_MASK 0x0000FFFFu /**< \brief (CAN_HPMS) MASK Register */
-
-/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ND0:1; /*!< bit: 0 New Data 0 */
- uint32_t ND1:1; /*!< bit: 1 New Data 1 */
- uint32_t ND2:1; /*!< bit: 2 New Data 2 */
- uint32_t ND3:1; /*!< bit: 3 New Data 3 */
- uint32_t ND4:1; /*!< bit: 4 New Data 4 */
- uint32_t ND5:1; /*!< bit: 5 New Data 5 */
- uint32_t ND6:1; /*!< bit: 6 New Data 6 */
- uint32_t ND7:1; /*!< bit: 7 New Data 7 */
- uint32_t ND8:1; /*!< bit: 8 New Data 8 */
- uint32_t ND9:1; /*!< bit: 9 New Data 9 */
- uint32_t ND10:1; /*!< bit: 10 New Data 10 */
- uint32_t ND11:1; /*!< bit: 11 New Data 11 */
- uint32_t ND12:1; /*!< bit: 12 New Data 12 */
- uint32_t ND13:1; /*!< bit: 13 New Data 13 */
- uint32_t ND14:1; /*!< bit: 14 New Data 14 */
- uint32_t ND15:1; /*!< bit: 15 New Data 15 */
- uint32_t ND16:1; /*!< bit: 16 New Data 16 */
- uint32_t ND17:1; /*!< bit: 17 New Data 17 */
- uint32_t ND18:1; /*!< bit: 18 New Data 18 */
- uint32_t ND19:1; /*!< bit: 19 New Data 19 */
- uint32_t ND20:1; /*!< bit: 20 New Data 20 */
- uint32_t ND21:1; /*!< bit: 21 New Data 21 */
- uint32_t ND22:1; /*!< bit: 22 New Data 22 */
- uint32_t ND23:1; /*!< bit: 23 New Data 23 */
- uint32_t ND24:1; /*!< bit: 24 New Data 24 */
- uint32_t ND25:1; /*!< bit: 25 New Data 25 */
- uint32_t ND26:1; /*!< bit: 26 New Data 26 */
- uint32_t ND27:1; /*!< bit: 27 New Data 27 */
- uint32_t ND28:1; /*!< bit: 28 New Data 28 */
- uint32_t ND29:1; /*!< bit: 29 New Data 29 */
- uint32_t ND30:1; /*!< bit: 30 New Data 30 */
- uint32_t ND31:1; /*!< bit: 31 New Data 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_NDAT1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */
-#define CAN_NDAT1_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT1 reset_value) New Data 1 */
-
-#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */
-#define CAN_NDAT1_ND0 (0x1u << CAN_NDAT1_ND0_Pos)
-#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */
-#define CAN_NDAT1_ND1 (0x1u << CAN_NDAT1_ND1_Pos)
-#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */
-#define CAN_NDAT1_ND2 (0x1u << CAN_NDAT1_ND2_Pos)
-#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */
-#define CAN_NDAT1_ND3 (0x1u << CAN_NDAT1_ND3_Pos)
-#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */
-#define CAN_NDAT1_ND4 (0x1u << CAN_NDAT1_ND4_Pos)
-#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */
-#define CAN_NDAT1_ND5 (0x1u << CAN_NDAT1_ND5_Pos)
-#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */
-#define CAN_NDAT1_ND6 (0x1u << CAN_NDAT1_ND6_Pos)
-#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */
-#define CAN_NDAT1_ND7 (0x1u << CAN_NDAT1_ND7_Pos)
-#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */
-#define CAN_NDAT1_ND8 (0x1u << CAN_NDAT1_ND8_Pos)
-#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */
-#define CAN_NDAT1_ND9 (0x1u << CAN_NDAT1_ND9_Pos)
-#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */
-#define CAN_NDAT1_ND10 (0x1u << CAN_NDAT1_ND10_Pos)
-#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */
-#define CAN_NDAT1_ND11 (0x1u << CAN_NDAT1_ND11_Pos)
-#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */
-#define CAN_NDAT1_ND12 (0x1u << CAN_NDAT1_ND12_Pos)
-#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */
-#define CAN_NDAT1_ND13 (0x1u << CAN_NDAT1_ND13_Pos)
-#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */
-#define CAN_NDAT1_ND14 (0x1u << CAN_NDAT1_ND14_Pos)
-#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */
-#define CAN_NDAT1_ND15 (0x1u << CAN_NDAT1_ND15_Pos)
-#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */
-#define CAN_NDAT1_ND16 (0x1u << CAN_NDAT1_ND16_Pos)
-#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */
-#define CAN_NDAT1_ND17 (0x1u << CAN_NDAT1_ND17_Pos)
-#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */
-#define CAN_NDAT1_ND18 (0x1u << CAN_NDAT1_ND18_Pos)
-#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */
-#define CAN_NDAT1_ND19 (0x1u << CAN_NDAT1_ND19_Pos)
-#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */
-#define CAN_NDAT1_ND20 (0x1u << CAN_NDAT1_ND20_Pos)
-#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */
-#define CAN_NDAT1_ND21 (0x1u << CAN_NDAT1_ND21_Pos)
-#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */
-#define CAN_NDAT1_ND22 (0x1u << CAN_NDAT1_ND22_Pos)
-#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */
-#define CAN_NDAT1_ND23 (0x1u << CAN_NDAT1_ND23_Pos)
-#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */
-#define CAN_NDAT1_ND24 (0x1u << CAN_NDAT1_ND24_Pos)
-#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */
-#define CAN_NDAT1_ND25 (0x1u << CAN_NDAT1_ND25_Pos)
-#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */
-#define CAN_NDAT1_ND26 (0x1u << CAN_NDAT1_ND26_Pos)
-#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */
-#define CAN_NDAT1_ND27 (0x1u << CAN_NDAT1_ND27_Pos)
-#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */
-#define CAN_NDAT1_ND28 (0x1u << CAN_NDAT1_ND28_Pos)
-#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */
-#define CAN_NDAT1_ND29 (0x1u << CAN_NDAT1_ND29_Pos)
-#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */
-#define CAN_NDAT1_ND30 (0x1u << CAN_NDAT1_ND30_Pos)
-#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */
-#define CAN_NDAT1_ND31 (0x1u << CAN_NDAT1_ND31_Pos)
-#define CAN_NDAT1_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT1) MASK Register */
-
-/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ND32:1; /*!< bit: 0 New Data 32 */
- uint32_t ND33:1; /*!< bit: 1 New Data 33 */
- uint32_t ND34:1; /*!< bit: 2 New Data 34 */
- uint32_t ND35:1; /*!< bit: 3 New Data 35 */
- uint32_t ND36:1; /*!< bit: 4 New Data 36 */
- uint32_t ND37:1; /*!< bit: 5 New Data 37 */
- uint32_t ND38:1; /*!< bit: 6 New Data 38 */
- uint32_t ND39:1; /*!< bit: 7 New Data 39 */
- uint32_t ND40:1; /*!< bit: 8 New Data 40 */
- uint32_t ND41:1; /*!< bit: 9 New Data 41 */
- uint32_t ND42:1; /*!< bit: 10 New Data 42 */
- uint32_t ND43:1; /*!< bit: 11 New Data 43 */
- uint32_t ND44:1; /*!< bit: 12 New Data 44 */
- uint32_t ND45:1; /*!< bit: 13 New Data 45 */
- uint32_t ND46:1; /*!< bit: 14 New Data 46 */
- uint32_t ND47:1; /*!< bit: 15 New Data 47 */
- uint32_t ND48:1; /*!< bit: 16 New Data 48 */
- uint32_t ND49:1; /*!< bit: 17 New Data 49 */
- uint32_t ND50:1; /*!< bit: 18 New Data 50 */
- uint32_t ND51:1; /*!< bit: 19 New Data 51 */
- uint32_t ND52:1; /*!< bit: 20 New Data 52 */
- uint32_t ND53:1; /*!< bit: 21 New Data 53 */
- uint32_t ND54:1; /*!< bit: 22 New Data 54 */
- uint32_t ND55:1; /*!< bit: 23 New Data 55 */
- uint32_t ND56:1; /*!< bit: 24 New Data 56 */
- uint32_t ND57:1; /*!< bit: 25 New Data 57 */
- uint32_t ND58:1; /*!< bit: 26 New Data 58 */
- uint32_t ND59:1; /*!< bit: 27 New Data 59 */
- uint32_t ND60:1; /*!< bit: 28 New Data 60 */
- uint32_t ND61:1; /*!< bit: 29 New Data 61 */
- uint32_t ND62:1; /*!< bit: 30 New Data 62 */
- uint32_t ND63:1; /*!< bit: 31 New Data 63 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_NDAT2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */
-#define CAN_NDAT2_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT2 reset_value) New Data 2 */
-
-#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */
-#define CAN_NDAT2_ND32 (0x1u << CAN_NDAT2_ND32_Pos)
-#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */
-#define CAN_NDAT2_ND33 (0x1u << CAN_NDAT2_ND33_Pos)
-#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */
-#define CAN_NDAT2_ND34 (0x1u << CAN_NDAT2_ND34_Pos)
-#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */
-#define CAN_NDAT2_ND35 (0x1u << CAN_NDAT2_ND35_Pos)
-#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */
-#define CAN_NDAT2_ND36 (0x1u << CAN_NDAT2_ND36_Pos)
-#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */
-#define CAN_NDAT2_ND37 (0x1u << CAN_NDAT2_ND37_Pos)
-#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */
-#define CAN_NDAT2_ND38 (0x1u << CAN_NDAT2_ND38_Pos)
-#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */
-#define CAN_NDAT2_ND39 (0x1u << CAN_NDAT2_ND39_Pos)
-#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */
-#define CAN_NDAT2_ND40 (0x1u << CAN_NDAT2_ND40_Pos)
-#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */
-#define CAN_NDAT2_ND41 (0x1u << CAN_NDAT2_ND41_Pos)
-#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */
-#define CAN_NDAT2_ND42 (0x1u << CAN_NDAT2_ND42_Pos)
-#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */
-#define CAN_NDAT2_ND43 (0x1u << CAN_NDAT2_ND43_Pos)
-#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */
-#define CAN_NDAT2_ND44 (0x1u << CAN_NDAT2_ND44_Pos)
-#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */
-#define CAN_NDAT2_ND45 (0x1u << CAN_NDAT2_ND45_Pos)
-#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */
-#define CAN_NDAT2_ND46 (0x1u << CAN_NDAT2_ND46_Pos)
-#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */
-#define CAN_NDAT2_ND47 (0x1u << CAN_NDAT2_ND47_Pos)
-#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */
-#define CAN_NDAT2_ND48 (0x1u << CAN_NDAT2_ND48_Pos)
-#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */
-#define CAN_NDAT2_ND49 (0x1u << CAN_NDAT2_ND49_Pos)
-#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */
-#define CAN_NDAT2_ND50 (0x1u << CAN_NDAT2_ND50_Pos)
-#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */
-#define CAN_NDAT2_ND51 (0x1u << CAN_NDAT2_ND51_Pos)
-#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */
-#define CAN_NDAT2_ND52 (0x1u << CAN_NDAT2_ND52_Pos)
-#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */
-#define CAN_NDAT2_ND53 (0x1u << CAN_NDAT2_ND53_Pos)
-#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */
-#define CAN_NDAT2_ND54 (0x1u << CAN_NDAT2_ND54_Pos)
-#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */
-#define CAN_NDAT2_ND55 (0x1u << CAN_NDAT2_ND55_Pos)
-#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */
-#define CAN_NDAT2_ND56 (0x1u << CAN_NDAT2_ND56_Pos)
-#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */
-#define CAN_NDAT2_ND57 (0x1u << CAN_NDAT2_ND57_Pos)
-#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */
-#define CAN_NDAT2_ND58 (0x1u << CAN_NDAT2_ND58_Pos)
-#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */
-#define CAN_NDAT2_ND59 (0x1u << CAN_NDAT2_ND59_Pos)
-#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */
-#define CAN_NDAT2_ND60 (0x1u << CAN_NDAT2_ND60_Pos)
-#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */
-#define CAN_NDAT2_ND61 (0x1u << CAN_NDAT2_ND61_Pos)
-#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */
-#define CAN_NDAT2_ND62 (0x1u << CAN_NDAT2_ND62_Pos)
-#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */
-#define CAN_NDAT2_ND63 (0x1u << CAN_NDAT2_ND63_Pos)
-#define CAN_NDAT2_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT2) MASK Register */
-
-/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */
- uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */
- uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0C_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */
-#define CAN_RXF0C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */
-
-#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */
-#define CAN_RXF0C_F0SA_Msk (0xFFFFu << CAN_RXF0C_F0SA_Pos)
-#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos))
-#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */
-#define CAN_RXF0C_F0S_Msk (0x7Fu << CAN_RXF0C_F0S_Pos)
-#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos))
-#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */
-#define CAN_RXF0C_F0WM_Msk (0x7Fu << CAN_RXF0C_F0WM_Pos)
-#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos))
-#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */
-#define CAN_RXF0C_F0OM (0x1u << CAN_RXF0C_F0OM_Pos)
-#define CAN_RXF0C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF0C) MASK Register */
-
-/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */
- uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0S_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */
-#define CAN_RXF0S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */
-
-#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */
-#define CAN_RXF0S_F0FL_Msk (0x7Fu << CAN_RXF0S_F0FL_Pos)
-#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos))
-#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */
-#define CAN_RXF0S_F0GI_Msk (0x3Fu << CAN_RXF0S_F0GI_Pos)
-#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos))
-#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */
-#define CAN_RXF0S_F0PI_Msk (0x3Fu << CAN_RXF0S_F0PI_Pos)
-#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos))
-#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */
-#define CAN_RXF0S_F0F (0x1u << CAN_RXF0S_F0F_Pos)
-#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */
-#define CAN_RXF0S_RF0L (0x1u << CAN_RXF0S_RF0L_Pos)
-#define CAN_RXF0S_MASK 0x033F3F7Fu /**< \brief (CAN_RXF0S) MASK Register */
-
-/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0A_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */
-#define CAN_RXF0A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */
-
-#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */
-#define CAN_RXF0A_F0AI_Msk (0x3Fu << CAN_RXF0A_F0AI_Pos)
-#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos))
-#define CAN_RXF0A_MASK 0x0000003Fu /**< \brief (CAN_RXF0A) MASK Register */
-
-/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */
-#define CAN_RXBC_RESETVALUE 0x00000000u /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */
-
-#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */
-#define CAN_RXBC_RBSA_Msk (0xFFFFu << CAN_RXBC_RBSA_Pos)
-#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos))
-#define CAN_RXBC_MASK 0x0000FFFFu /**< \brief (CAN_RXBC) MASK Register */
-
-/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */
- uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */
- uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1C_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */
-#define CAN_RXF1C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */
-
-#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */
-#define CAN_RXF1C_F1SA_Msk (0xFFFFu << CAN_RXF1C_F1SA_Pos)
-#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos))
-#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */
-#define CAN_RXF1C_F1S_Msk (0x7Fu << CAN_RXF1C_F1S_Pos)
-#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos))
-#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */
-#define CAN_RXF1C_F1WM_Msk (0x7Fu << CAN_RXF1C_F1WM_Pos)
-#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos))
-#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */
-#define CAN_RXF1C_F1OM (0x1u << CAN_RXF1C_F1OM_Pos)
-#define CAN_RXF1C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF1C) MASK Register */
-
-/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */
- uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */
- uint32_t :4; /*!< bit: 26..29 Reserved */
- uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1S_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */
-#define CAN_RXF1S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */
-
-#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */
-#define CAN_RXF1S_F1FL_Msk (0x7Fu << CAN_RXF1S_F1FL_Pos)
-#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos))
-#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */
-#define CAN_RXF1S_F1GI_Msk (0x3Fu << CAN_RXF1S_F1GI_Pos)
-#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos))
-#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */
-#define CAN_RXF1S_F1PI_Msk (0x3Fu << CAN_RXF1S_F1PI_Pos)
-#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos))
-#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */
-#define CAN_RXF1S_F1F (0x1u << CAN_RXF1S_F1F_Pos)
-#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */
-#define CAN_RXF1S_RF1L (0x1u << CAN_RXF1S_RF1L_Pos)
-#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */
-#define CAN_RXF1S_DMS_Msk (0x3u << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos))
-#define CAN_RXF1S_DMS_IDLE_Val 0x0u /**< \brief (CAN_RXF1S) Idle state */
-#define CAN_RXF1S_DMS_DBGA_Val 0x1u /**< \brief (CAN_RXF1S) Debug message A received */
-#define CAN_RXF1S_DMS_DBGB_Val 0x2u /**< \brief (CAN_RXF1S) Debug message A/B received */
-#define CAN_RXF1S_DMS_DBGC_Val 0x3u /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */
-#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_MASK 0xC33F3F7Fu /**< \brief (CAN_RXF1S) MASK Register */
-
-/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1A_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */
-#define CAN_RXF1A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */
-
-#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */
-#define CAN_RXF1A_F1AI_Msk (0x3Fu << CAN_RXF1A_F1AI_Pos)
-#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos))
-#define CAN_RXF1A_MASK 0x0000003Fu /**< \brief (CAN_RXF1A) MASK Register */
-
-/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */
- uint32_t :21; /*!< bit: 11..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */
-#define CAN_RXESC_RESETVALUE 0x00000000u /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */
-
-#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */
-#define CAN_RXESC_F0DS_Msk (0x7u << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos))
-#define CAN_RXESC_F0DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */
-#define CAN_RXESC_F0DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */
-#define CAN_RXESC_F0DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */
-#define CAN_RXESC_F0DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */
-#define CAN_RXESC_F0DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */
-#define CAN_RXESC_F0DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */
-#define CAN_RXESC_F0DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */
-#define CAN_RXESC_F0DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */
-#define CAN_RXESC_F1DS_Msk (0x7u << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos))
-#define CAN_RXESC_F1DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */
-#define CAN_RXESC_F1DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */
-#define CAN_RXESC_F1DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */
-#define CAN_RXESC_F1DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */
-#define CAN_RXESC_F1DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */
-#define CAN_RXESC_F1DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */
-#define CAN_RXESC_F1DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */
-#define CAN_RXESC_F1DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */
-#define CAN_RXESC_RBDS_Msk (0x7u << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos))
-#define CAN_RXESC_RBDS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */
-#define CAN_RXESC_RBDS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */
-#define CAN_RXESC_RBDS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */
-#define CAN_RXESC_RBDS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */
-#define CAN_RXESC_RBDS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */
-#define CAN_RXESC_RBDS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */
-#define CAN_RXESC_RBDS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */
-#define CAN_RXESC_RBDS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_MASK 0x00000777u /**< \brief (CAN_RXESC) MASK Register */
-
-/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */
- uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */
- uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */
-#define CAN_TXBC_RESETVALUE 0x00000000u /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */
-
-#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */
-#define CAN_TXBC_TBSA_Msk (0xFFFFu << CAN_TXBC_TBSA_Pos)
-#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos))
-#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */
-#define CAN_TXBC_NDTB_Msk (0x3Fu << CAN_TXBC_NDTB_Pos)
-#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos))
-#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */
-#define CAN_TXBC_TFQS_Msk (0x3Fu << CAN_TXBC_TFQS_Pos)
-#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos))
-#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */
-#define CAN_TXBC_TFQM (0x1u << CAN_TXBC_TFQM_Pos)
-#define CAN_TXBC_MASK 0x7F3FFFFFu /**< \brief (CAN_TXBC) MASK Register */
-
-/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */
- uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXFQS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */
-#define CAN_TXFQS_RESETVALUE 0x00000000u /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */
-
-#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */
-#define CAN_TXFQS_TFFL_Msk (0x3Fu << CAN_TXFQS_TFFL_Pos)
-#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos))
-#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */
-#define CAN_TXFQS_TFGI_Msk (0x1Fu << CAN_TXFQS_TFGI_Pos)
-#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos))
-#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */
-#define CAN_TXFQS_TFQPI_Msk (0x1Fu << CAN_TXFQS_TFQPI_Pos)
-#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos))
-#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */
-#define CAN_TXFQS_TFQF (0x1u << CAN_TXFQS_TFQF_Pos)
-#define CAN_TXFQS_MASK 0x003F1F3Fu /**< \brief (CAN_TXFQS) MASK Register */
-
-/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */
-#define CAN_TXESC_RESETVALUE 0x00000000u /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */
-
-#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */
-#define CAN_TXESC_TBDS_Msk (0x7u << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos))
-#define CAN_TXESC_TBDS_DATA8_Val 0x0u /**< \brief (CAN_TXESC) 8 byte data field */
-#define CAN_TXESC_TBDS_DATA12_Val 0x1u /**< \brief (CAN_TXESC) 12 byte data field */
-#define CAN_TXESC_TBDS_DATA16_Val 0x2u /**< \brief (CAN_TXESC) 16 byte data field */
-#define CAN_TXESC_TBDS_DATA20_Val 0x3u /**< \brief (CAN_TXESC) 20 byte data field */
-#define CAN_TXESC_TBDS_DATA24_Val 0x4u /**< \brief (CAN_TXESC) 24 byte data field */
-#define CAN_TXESC_TBDS_DATA32_Val 0x5u /**< \brief (CAN_TXESC) 32 byte data field */
-#define CAN_TXESC_TBDS_DATA48_Val 0x6u /**< \brief (CAN_TXESC) 48 byte data field */
-#define CAN_TXESC_TBDS_DATA64_Val 0x7u /**< \brief (CAN_TXESC) 64 byte data field */
-#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_MASK 0x00000007u /**< \brief (CAN_TXESC) MASK Register */
-
-/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */
- uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */
- uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */
- uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */
- uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */
- uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */
- uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */
- uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */
- uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */
- uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */
- uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */
- uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */
- uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */
- uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */
- uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */
- uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */
- uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */
- uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */
- uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */
- uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */
- uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */
- uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */
- uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */
- uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */
- uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */
- uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */
- uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */
- uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */
- uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */
- uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */
- uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */
- uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBRP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */
-#define CAN_TXBRP_RESETVALUE 0x00000000u /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */
-
-#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */
-#define CAN_TXBRP_TRP0 (0x1u << CAN_TXBRP_TRP0_Pos)
-#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */
-#define CAN_TXBRP_TRP1 (0x1u << CAN_TXBRP_TRP1_Pos)
-#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */
-#define CAN_TXBRP_TRP2 (0x1u << CAN_TXBRP_TRP2_Pos)
-#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */
-#define CAN_TXBRP_TRP3 (0x1u << CAN_TXBRP_TRP3_Pos)
-#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */
-#define CAN_TXBRP_TRP4 (0x1u << CAN_TXBRP_TRP4_Pos)
-#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */
-#define CAN_TXBRP_TRP5 (0x1u << CAN_TXBRP_TRP5_Pos)
-#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */
-#define CAN_TXBRP_TRP6 (0x1u << CAN_TXBRP_TRP6_Pos)
-#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */
-#define CAN_TXBRP_TRP7 (0x1u << CAN_TXBRP_TRP7_Pos)
-#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */
-#define CAN_TXBRP_TRP8 (0x1u << CAN_TXBRP_TRP8_Pos)
-#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */
-#define CAN_TXBRP_TRP9 (0x1u << CAN_TXBRP_TRP9_Pos)
-#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */
-#define CAN_TXBRP_TRP10 (0x1u << CAN_TXBRP_TRP10_Pos)
-#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */
-#define CAN_TXBRP_TRP11 (0x1u << CAN_TXBRP_TRP11_Pos)
-#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */
-#define CAN_TXBRP_TRP12 (0x1u << CAN_TXBRP_TRP12_Pos)
-#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */
-#define CAN_TXBRP_TRP13 (0x1u << CAN_TXBRP_TRP13_Pos)
-#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */
-#define CAN_TXBRP_TRP14 (0x1u << CAN_TXBRP_TRP14_Pos)
-#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */
-#define CAN_TXBRP_TRP15 (0x1u << CAN_TXBRP_TRP15_Pos)
-#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */
-#define CAN_TXBRP_TRP16 (0x1u << CAN_TXBRP_TRP16_Pos)
-#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */
-#define CAN_TXBRP_TRP17 (0x1u << CAN_TXBRP_TRP17_Pos)
-#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */
-#define CAN_TXBRP_TRP18 (0x1u << CAN_TXBRP_TRP18_Pos)
-#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */
-#define CAN_TXBRP_TRP19 (0x1u << CAN_TXBRP_TRP19_Pos)
-#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */
-#define CAN_TXBRP_TRP20 (0x1u << CAN_TXBRP_TRP20_Pos)
-#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */
-#define CAN_TXBRP_TRP21 (0x1u << CAN_TXBRP_TRP21_Pos)
-#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */
-#define CAN_TXBRP_TRP22 (0x1u << CAN_TXBRP_TRP22_Pos)
-#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */
-#define CAN_TXBRP_TRP23 (0x1u << CAN_TXBRP_TRP23_Pos)
-#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */
-#define CAN_TXBRP_TRP24 (0x1u << CAN_TXBRP_TRP24_Pos)
-#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */
-#define CAN_TXBRP_TRP25 (0x1u << CAN_TXBRP_TRP25_Pos)
-#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */
-#define CAN_TXBRP_TRP26 (0x1u << CAN_TXBRP_TRP26_Pos)
-#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */
-#define CAN_TXBRP_TRP27 (0x1u << CAN_TXBRP_TRP27_Pos)
-#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */
-#define CAN_TXBRP_TRP28 (0x1u << CAN_TXBRP_TRP28_Pos)
-#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */
-#define CAN_TXBRP_TRP29 (0x1u << CAN_TXBRP_TRP29_Pos)
-#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */
-#define CAN_TXBRP_TRP30 (0x1u << CAN_TXBRP_TRP30_Pos)
-#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */
-#define CAN_TXBRP_TRP31 (0x1u << CAN_TXBRP_TRP31_Pos)
-#define CAN_TXBRP_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBRP) MASK Register */
-
-/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t AR0:1; /*!< bit: 0 Add Request 0 */
- uint32_t AR1:1; /*!< bit: 1 Add Request 1 */
- uint32_t AR2:1; /*!< bit: 2 Add Request 2 */
- uint32_t AR3:1; /*!< bit: 3 Add Request 3 */
- uint32_t AR4:1; /*!< bit: 4 Add Request 4 */
- uint32_t AR5:1; /*!< bit: 5 Add Request 5 */
- uint32_t AR6:1; /*!< bit: 6 Add Request 6 */
- uint32_t AR7:1; /*!< bit: 7 Add Request 7 */
- uint32_t AR8:1; /*!< bit: 8 Add Request 8 */
- uint32_t AR9:1; /*!< bit: 9 Add Request 9 */
- uint32_t AR10:1; /*!< bit: 10 Add Request 10 */
- uint32_t AR11:1; /*!< bit: 11 Add Request 11 */
- uint32_t AR12:1; /*!< bit: 12 Add Request 12 */
- uint32_t AR13:1; /*!< bit: 13 Add Request 13 */
- uint32_t AR14:1; /*!< bit: 14 Add Request 14 */
- uint32_t AR15:1; /*!< bit: 15 Add Request 15 */
- uint32_t AR16:1; /*!< bit: 16 Add Request 16 */
- uint32_t AR17:1; /*!< bit: 17 Add Request 17 */
- uint32_t AR18:1; /*!< bit: 18 Add Request 18 */
- uint32_t AR19:1; /*!< bit: 19 Add Request 19 */
- uint32_t AR20:1; /*!< bit: 20 Add Request 20 */
- uint32_t AR21:1; /*!< bit: 21 Add Request 21 */
- uint32_t AR22:1; /*!< bit: 22 Add Request 22 */
- uint32_t AR23:1; /*!< bit: 23 Add Request 23 */
- uint32_t AR24:1; /*!< bit: 24 Add Request 24 */
- uint32_t AR25:1; /*!< bit: 25 Add Request 25 */
- uint32_t AR26:1; /*!< bit: 26 Add Request 26 */
- uint32_t AR27:1; /*!< bit: 27 Add Request 27 */
- uint32_t AR28:1; /*!< bit: 28 Add Request 28 */
- uint32_t AR29:1; /*!< bit: 29 Add Request 29 */
- uint32_t AR30:1; /*!< bit: 30 Add Request 30 */
- uint32_t AR31:1; /*!< bit: 31 Add Request 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */
-#define CAN_TXBAR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */
-
-#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */
-#define CAN_TXBAR_AR0 (0x1u << CAN_TXBAR_AR0_Pos)
-#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */
-#define CAN_TXBAR_AR1 (0x1u << CAN_TXBAR_AR1_Pos)
-#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */
-#define CAN_TXBAR_AR2 (0x1u << CAN_TXBAR_AR2_Pos)
-#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */
-#define CAN_TXBAR_AR3 (0x1u << CAN_TXBAR_AR3_Pos)
-#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */
-#define CAN_TXBAR_AR4 (0x1u << CAN_TXBAR_AR4_Pos)
-#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */
-#define CAN_TXBAR_AR5 (0x1u << CAN_TXBAR_AR5_Pos)
-#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */
-#define CAN_TXBAR_AR6 (0x1u << CAN_TXBAR_AR6_Pos)
-#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */
-#define CAN_TXBAR_AR7 (0x1u << CAN_TXBAR_AR7_Pos)
-#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */
-#define CAN_TXBAR_AR8 (0x1u << CAN_TXBAR_AR8_Pos)
-#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */
-#define CAN_TXBAR_AR9 (0x1u << CAN_TXBAR_AR9_Pos)
-#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */
-#define CAN_TXBAR_AR10 (0x1u << CAN_TXBAR_AR10_Pos)
-#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */
-#define CAN_TXBAR_AR11 (0x1u << CAN_TXBAR_AR11_Pos)
-#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */
-#define CAN_TXBAR_AR12 (0x1u << CAN_TXBAR_AR12_Pos)
-#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */
-#define CAN_TXBAR_AR13 (0x1u << CAN_TXBAR_AR13_Pos)
-#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */
-#define CAN_TXBAR_AR14 (0x1u << CAN_TXBAR_AR14_Pos)
-#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */
-#define CAN_TXBAR_AR15 (0x1u << CAN_TXBAR_AR15_Pos)
-#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */
-#define CAN_TXBAR_AR16 (0x1u << CAN_TXBAR_AR16_Pos)
-#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */
-#define CAN_TXBAR_AR17 (0x1u << CAN_TXBAR_AR17_Pos)
-#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */
-#define CAN_TXBAR_AR18 (0x1u << CAN_TXBAR_AR18_Pos)
-#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */
-#define CAN_TXBAR_AR19 (0x1u << CAN_TXBAR_AR19_Pos)
-#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */
-#define CAN_TXBAR_AR20 (0x1u << CAN_TXBAR_AR20_Pos)
-#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */
-#define CAN_TXBAR_AR21 (0x1u << CAN_TXBAR_AR21_Pos)
-#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */
-#define CAN_TXBAR_AR22 (0x1u << CAN_TXBAR_AR22_Pos)
-#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */
-#define CAN_TXBAR_AR23 (0x1u << CAN_TXBAR_AR23_Pos)
-#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */
-#define CAN_TXBAR_AR24 (0x1u << CAN_TXBAR_AR24_Pos)
-#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */
-#define CAN_TXBAR_AR25 (0x1u << CAN_TXBAR_AR25_Pos)
-#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */
-#define CAN_TXBAR_AR26 (0x1u << CAN_TXBAR_AR26_Pos)
-#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */
-#define CAN_TXBAR_AR27 (0x1u << CAN_TXBAR_AR27_Pos)
-#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */
-#define CAN_TXBAR_AR28 (0x1u << CAN_TXBAR_AR28_Pos)
-#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */
-#define CAN_TXBAR_AR29 (0x1u << CAN_TXBAR_AR29_Pos)
-#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */
-#define CAN_TXBAR_AR30 (0x1u << CAN_TXBAR_AR30_Pos)
-#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */
-#define CAN_TXBAR_AR31 (0x1u << CAN_TXBAR_AR31_Pos)
-#define CAN_TXBAR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBAR) MASK Register */
-
-/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */
- uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */
- uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */
- uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */
- uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */
- uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */
- uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */
- uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */
- uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */
- uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */
- uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */
- uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */
- uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */
- uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */
- uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */
- uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */
- uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */
- uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */
- uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */
- uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */
- uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */
- uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */
- uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */
- uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */
- uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */
- uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */
- uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */
- uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */
- uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */
- uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */
- uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */
- uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */
-#define CAN_TXBCR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */
-
-#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */
-#define CAN_TXBCR_CR0 (0x1u << CAN_TXBCR_CR0_Pos)
-#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */
-#define CAN_TXBCR_CR1 (0x1u << CAN_TXBCR_CR1_Pos)
-#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */
-#define CAN_TXBCR_CR2 (0x1u << CAN_TXBCR_CR2_Pos)
-#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */
-#define CAN_TXBCR_CR3 (0x1u << CAN_TXBCR_CR3_Pos)
-#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */
-#define CAN_TXBCR_CR4 (0x1u << CAN_TXBCR_CR4_Pos)
-#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */
-#define CAN_TXBCR_CR5 (0x1u << CAN_TXBCR_CR5_Pos)
-#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */
-#define CAN_TXBCR_CR6 (0x1u << CAN_TXBCR_CR6_Pos)
-#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */
-#define CAN_TXBCR_CR7 (0x1u << CAN_TXBCR_CR7_Pos)
-#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */
-#define CAN_TXBCR_CR8 (0x1u << CAN_TXBCR_CR8_Pos)
-#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */
-#define CAN_TXBCR_CR9 (0x1u << CAN_TXBCR_CR9_Pos)
-#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */
-#define CAN_TXBCR_CR10 (0x1u << CAN_TXBCR_CR10_Pos)
-#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */
-#define CAN_TXBCR_CR11 (0x1u << CAN_TXBCR_CR11_Pos)
-#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */
-#define CAN_TXBCR_CR12 (0x1u << CAN_TXBCR_CR12_Pos)
-#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */
-#define CAN_TXBCR_CR13 (0x1u << CAN_TXBCR_CR13_Pos)
-#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */
-#define CAN_TXBCR_CR14 (0x1u << CAN_TXBCR_CR14_Pos)
-#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */
-#define CAN_TXBCR_CR15 (0x1u << CAN_TXBCR_CR15_Pos)
-#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */
-#define CAN_TXBCR_CR16 (0x1u << CAN_TXBCR_CR16_Pos)
-#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */
-#define CAN_TXBCR_CR17 (0x1u << CAN_TXBCR_CR17_Pos)
-#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */
-#define CAN_TXBCR_CR18 (0x1u << CAN_TXBCR_CR18_Pos)
-#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */
-#define CAN_TXBCR_CR19 (0x1u << CAN_TXBCR_CR19_Pos)
-#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */
-#define CAN_TXBCR_CR20 (0x1u << CAN_TXBCR_CR20_Pos)
-#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */
-#define CAN_TXBCR_CR21 (0x1u << CAN_TXBCR_CR21_Pos)
-#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */
-#define CAN_TXBCR_CR22 (0x1u << CAN_TXBCR_CR22_Pos)
-#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */
-#define CAN_TXBCR_CR23 (0x1u << CAN_TXBCR_CR23_Pos)
-#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */
-#define CAN_TXBCR_CR24 (0x1u << CAN_TXBCR_CR24_Pos)
-#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */
-#define CAN_TXBCR_CR25 (0x1u << CAN_TXBCR_CR25_Pos)
-#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */
-#define CAN_TXBCR_CR26 (0x1u << CAN_TXBCR_CR26_Pos)
-#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */
-#define CAN_TXBCR_CR27 (0x1u << CAN_TXBCR_CR27_Pos)
-#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */
-#define CAN_TXBCR_CR28 (0x1u << CAN_TXBCR_CR28_Pos)
-#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */
-#define CAN_TXBCR_CR29 (0x1u << CAN_TXBCR_CR29_Pos)
-#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */
-#define CAN_TXBCR_CR30 (0x1u << CAN_TXBCR_CR30_Pos)
-#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */
-#define CAN_TXBCR_CR31 (0x1u << CAN_TXBCR_CR31_Pos)
-#define CAN_TXBCR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCR) MASK Register */
-
-/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */
- uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */
- uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */
- uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */
- uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */
- uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */
- uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */
- uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */
- uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */
- uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */
- uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */
- uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */
- uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */
- uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */
- uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */
- uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */
- uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */
- uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */
- uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */
- uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */
- uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */
- uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */
- uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */
- uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */
- uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */
- uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */
- uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */
- uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */
- uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */
- uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */
- uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */
- uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBTO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */
-#define CAN_TXBTO_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */
-
-#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */
-#define CAN_TXBTO_TO0 (0x1u << CAN_TXBTO_TO0_Pos)
-#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */
-#define CAN_TXBTO_TO1 (0x1u << CAN_TXBTO_TO1_Pos)
-#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */
-#define CAN_TXBTO_TO2 (0x1u << CAN_TXBTO_TO2_Pos)
-#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */
-#define CAN_TXBTO_TO3 (0x1u << CAN_TXBTO_TO3_Pos)
-#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */
-#define CAN_TXBTO_TO4 (0x1u << CAN_TXBTO_TO4_Pos)
-#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */
-#define CAN_TXBTO_TO5 (0x1u << CAN_TXBTO_TO5_Pos)
-#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */
-#define CAN_TXBTO_TO6 (0x1u << CAN_TXBTO_TO6_Pos)
-#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */
-#define CAN_TXBTO_TO7 (0x1u << CAN_TXBTO_TO7_Pos)
-#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */
-#define CAN_TXBTO_TO8 (0x1u << CAN_TXBTO_TO8_Pos)
-#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */
-#define CAN_TXBTO_TO9 (0x1u << CAN_TXBTO_TO9_Pos)
-#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */
-#define CAN_TXBTO_TO10 (0x1u << CAN_TXBTO_TO10_Pos)
-#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */
-#define CAN_TXBTO_TO11 (0x1u << CAN_TXBTO_TO11_Pos)
-#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */
-#define CAN_TXBTO_TO12 (0x1u << CAN_TXBTO_TO12_Pos)
-#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */
-#define CAN_TXBTO_TO13 (0x1u << CAN_TXBTO_TO13_Pos)
-#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */
-#define CAN_TXBTO_TO14 (0x1u << CAN_TXBTO_TO14_Pos)
-#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */
-#define CAN_TXBTO_TO15 (0x1u << CAN_TXBTO_TO15_Pos)
-#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */
-#define CAN_TXBTO_TO16 (0x1u << CAN_TXBTO_TO16_Pos)
-#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */
-#define CAN_TXBTO_TO17 (0x1u << CAN_TXBTO_TO17_Pos)
-#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */
-#define CAN_TXBTO_TO18 (0x1u << CAN_TXBTO_TO18_Pos)
-#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */
-#define CAN_TXBTO_TO19 (0x1u << CAN_TXBTO_TO19_Pos)
-#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */
-#define CAN_TXBTO_TO20 (0x1u << CAN_TXBTO_TO20_Pos)
-#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */
-#define CAN_TXBTO_TO21 (0x1u << CAN_TXBTO_TO21_Pos)
-#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */
-#define CAN_TXBTO_TO22 (0x1u << CAN_TXBTO_TO22_Pos)
-#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */
-#define CAN_TXBTO_TO23 (0x1u << CAN_TXBTO_TO23_Pos)
-#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */
-#define CAN_TXBTO_TO24 (0x1u << CAN_TXBTO_TO24_Pos)
-#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */
-#define CAN_TXBTO_TO25 (0x1u << CAN_TXBTO_TO25_Pos)
-#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */
-#define CAN_TXBTO_TO26 (0x1u << CAN_TXBTO_TO26_Pos)
-#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */
-#define CAN_TXBTO_TO27 (0x1u << CAN_TXBTO_TO27_Pos)
-#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */
-#define CAN_TXBTO_TO28 (0x1u << CAN_TXBTO_TO28_Pos)
-#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */
-#define CAN_TXBTO_TO29 (0x1u << CAN_TXBTO_TO29_Pos)
-#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */
-#define CAN_TXBTO_TO30 (0x1u << CAN_TXBTO_TO30_Pos)
-#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */
-#define CAN_TXBTO_TO31 (0x1u << CAN_TXBTO_TO31_Pos)
-#define CAN_TXBTO_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTO) MASK Register */
-
-/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */
- uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */
- uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */
- uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */
- uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */
- uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */
- uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */
- uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */
- uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */
- uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */
- uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */
- uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */
- uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */
- uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */
- uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */
- uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */
- uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */
- uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */
- uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */
- uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */
- uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */
- uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */
- uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */
- uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */
- uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */
- uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */
- uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */
- uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */
- uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */
- uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */
- uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */
- uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBCF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */
-#define CAN_TXBCF_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */
-
-#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */
-#define CAN_TXBCF_CF0 (0x1u << CAN_TXBCF_CF0_Pos)
-#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */
-#define CAN_TXBCF_CF1 (0x1u << CAN_TXBCF_CF1_Pos)
-#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */
-#define CAN_TXBCF_CF2 (0x1u << CAN_TXBCF_CF2_Pos)
-#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */
-#define CAN_TXBCF_CF3 (0x1u << CAN_TXBCF_CF3_Pos)
-#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */
-#define CAN_TXBCF_CF4 (0x1u << CAN_TXBCF_CF4_Pos)
-#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */
-#define CAN_TXBCF_CF5 (0x1u << CAN_TXBCF_CF5_Pos)
-#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */
-#define CAN_TXBCF_CF6 (0x1u << CAN_TXBCF_CF6_Pos)
-#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */
-#define CAN_TXBCF_CF7 (0x1u << CAN_TXBCF_CF7_Pos)
-#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */
-#define CAN_TXBCF_CF8 (0x1u << CAN_TXBCF_CF8_Pos)
-#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */
-#define CAN_TXBCF_CF9 (0x1u << CAN_TXBCF_CF9_Pos)
-#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */
-#define CAN_TXBCF_CF10 (0x1u << CAN_TXBCF_CF10_Pos)
-#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */
-#define CAN_TXBCF_CF11 (0x1u << CAN_TXBCF_CF11_Pos)
-#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */
-#define CAN_TXBCF_CF12 (0x1u << CAN_TXBCF_CF12_Pos)
-#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */
-#define CAN_TXBCF_CF13 (0x1u << CAN_TXBCF_CF13_Pos)
-#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */
-#define CAN_TXBCF_CF14 (0x1u << CAN_TXBCF_CF14_Pos)
-#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */
-#define CAN_TXBCF_CF15 (0x1u << CAN_TXBCF_CF15_Pos)
-#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */
-#define CAN_TXBCF_CF16 (0x1u << CAN_TXBCF_CF16_Pos)
-#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */
-#define CAN_TXBCF_CF17 (0x1u << CAN_TXBCF_CF17_Pos)
-#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */
-#define CAN_TXBCF_CF18 (0x1u << CAN_TXBCF_CF18_Pos)
-#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */
-#define CAN_TXBCF_CF19 (0x1u << CAN_TXBCF_CF19_Pos)
-#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */
-#define CAN_TXBCF_CF20 (0x1u << CAN_TXBCF_CF20_Pos)
-#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */
-#define CAN_TXBCF_CF21 (0x1u << CAN_TXBCF_CF21_Pos)
-#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */
-#define CAN_TXBCF_CF22 (0x1u << CAN_TXBCF_CF22_Pos)
-#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */
-#define CAN_TXBCF_CF23 (0x1u << CAN_TXBCF_CF23_Pos)
-#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */
-#define CAN_TXBCF_CF24 (0x1u << CAN_TXBCF_CF24_Pos)
-#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */
-#define CAN_TXBCF_CF25 (0x1u << CAN_TXBCF_CF25_Pos)
-#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */
-#define CAN_TXBCF_CF26 (0x1u << CAN_TXBCF_CF26_Pos)
-#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */
-#define CAN_TXBCF_CF27 (0x1u << CAN_TXBCF_CF27_Pos)
-#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */
-#define CAN_TXBCF_CF28 (0x1u << CAN_TXBCF_CF28_Pos)
-#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */
-#define CAN_TXBCF_CF29 (0x1u << CAN_TXBCF_CF29_Pos)
-#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */
-#define CAN_TXBCF_CF30 (0x1u << CAN_TXBCF_CF30_Pos)
-#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */
-#define CAN_TXBCF_CF31 (0x1u << CAN_TXBCF_CF31_Pos)
-#define CAN_TXBCF_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCF) MASK Register */
-
-/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */
- uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */
- uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */
- uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */
- uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */
- uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */
- uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */
- uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */
- uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */
- uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */
- uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */
- uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */
- uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */
- uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */
- uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */
- uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */
- uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */
- uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */
- uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */
- uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */
- uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */
- uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */
- uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */
- uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */
- uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */
- uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */
- uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */
- uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */
- uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */
- uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */
- uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */
- uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBTIE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */
-#define CAN_TXBTIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */
-
-#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */
-#define CAN_TXBTIE_TIE0 (0x1u << CAN_TXBTIE_TIE0_Pos)
-#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */
-#define CAN_TXBTIE_TIE1 (0x1u << CAN_TXBTIE_TIE1_Pos)
-#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */
-#define CAN_TXBTIE_TIE2 (0x1u << CAN_TXBTIE_TIE2_Pos)
-#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */
-#define CAN_TXBTIE_TIE3 (0x1u << CAN_TXBTIE_TIE3_Pos)
-#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */
-#define CAN_TXBTIE_TIE4 (0x1u << CAN_TXBTIE_TIE4_Pos)
-#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */
-#define CAN_TXBTIE_TIE5 (0x1u << CAN_TXBTIE_TIE5_Pos)
-#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */
-#define CAN_TXBTIE_TIE6 (0x1u << CAN_TXBTIE_TIE6_Pos)
-#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */
-#define CAN_TXBTIE_TIE7 (0x1u << CAN_TXBTIE_TIE7_Pos)
-#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */
-#define CAN_TXBTIE_TIE8 (0x1u << CAN_TXBTIE_TIE8_Pos)
-#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */
-#define CAN_TXBTIE_TIE9 (0x1u << CAN_TXBTIE_TIE9_Pos)
-#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */
-#define CAN_TXBTIE_TIE10 (0x1u << CAN_TXBTIE_TIE10_Pos)
-#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */
-#define CAN_TXBTIE_TIE11 (0x1u << CAN_TXBTIE_TIE11_Pos)
-#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */
-#define CAN_TXBTIE_TIE12 (0x1u << CAN_TXBTIE_TIE12_Pos)
-#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */
-#define CAN_TXBTIE_TIE13 (0x1u << CAN_TXBTIE_TIE13_Pos)
-#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */
-#define CAN_TXBTIE_TIE14 (0x1u << CAN_TXBTIE_TIE14_Pos)
-#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */
-#define CAN_TXBTIE_TIE15 (0x1u << CAN_TXBTIE_TIE15_Pos)
-#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */
-#define CAN_TXBTIE_TIE16 (0x1u << CAN_TXBTIE_TIE16_Pos)
-#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */
-#define CAN_TXBTIE_TIE17 (0x1u << CAN_TXBTIE_TIE17_Pos)
-#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */
-#define CAN_TXBTIE_TIE18 (0x1u << CAN_TXBTIE_TIE18_Pos)
-#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */
-#define CAN_TXBTIE_TIE19 (0x1u << CAN_TXBTIE_TIE19_Pos)
-#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */
-#define CAN_TXBTIE_TIE20 (0x1u << CAN_TXBTIE_TIE20_Pos)
-#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */
-#define CAN_TXBTIE_TIE21 (0x1u << CAN_TXBTIE_TIE21_Pos)
-#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */
-#define CAN_TXBTIE_TIE22 (0x1u << CAN_TXBTIE_TIE22_Pos)
-#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */
-#define CAN_TXBTIE_TIE23 (0x1u << CAN_TXBTIE_TIE23_Pos)
-#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */
-#define CAN_TXBTIE_TIE24 (0x1u << CAN_TXBTIE_TIE24_Pos)
-#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */
-#define CAN_TXBTIE_TIE25 (0x1u << CAN_TXBTIE_TIE25_Pos)
-#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */
-#define CAN_TXBTIE_TIE26 (0x1u << CAN_TXBTIE_TIE26_Pos)
-#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */
-#define CAN_TXBTIE_TIE27 (0x1u << CAN_TXBTIE_TIE27_Pos)
-#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */
-#define CAN_TXBTIE_TIE28 (0x1u << CAN_TXBTIE_TIE28_Pos)
-#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */
-#define CAN_TXBTIE_TIE29 (0x1u << CAN_TXBTIE_TIE29_Pos)
-#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */
-#define CAN_TXBTIE_TIE30 (0x1u << CAN_TXBTIE_TIE30_Pos)
-#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */
-#define CAN_TXBTIE_TIE31 (0x1u << CAN_TXBTIE_TIE31_Pos)
-#define CAN_TXBTIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTIE) MASK Register */
-
-/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */
- uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */
- uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */
- uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */
- uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */
- uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */
- uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */
- uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */
- uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */
- uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */
- uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */
- uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */
- uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */
- uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */
- uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */
- uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */
- uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */
- uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */
- uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */
- uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */
- uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */
- uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */
- uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */
- uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */
- uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */
- uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */
- uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */
- uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */
- uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */
- uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */
- uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */
- uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBCIE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */
-#define CAN_TXBCIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */
-
-#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */
-#define CAN_TXBCIE_CFIE0 (0x1u << CAN_TXBCIE_CFIE0_Pos)
-#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */
-#define CAN_TXBCIE_CFIE1 (0x1u << CAN_TXBCIE_CFIE1_Pos)
-#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */
-#define CAN_TXBCIE_CFIE2 (0x1u << CAN_TXBCIE_CFIE2_Pos)
-#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */
-#define CAN_TXBCIE_CFIE3 (0x1u << CAN_TXBCIE_CFIE3_Pos)
-#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */
-#define CAN_TXBCIE_CFIE4 (0x1u << CAN_TXBCIE_CFIE4_Pos)
-#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */
-#define CAN_TXBCIE_CFIE5 (0x1u << CAN_TXBCIE_CFIE5_Pos)
-#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */
-#define CAN_TXBCIE_CFIE6 (0x1u << CAN_TXBCIE_CFIE6_Pos)
-#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */
-#define CAN_TXBCIE_CFIE7 (0x1u << CAN_TXBCIE_CFIE7_Pos)
-#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */
-#define CAN_TXBCIE_CFIE8 (0x1u << CAN_TXBCIE_CFIE8_Pos)
-#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */
-#define CAN_TXBCIE_CFIE9 (0x1u << CAN_TXBCIE_CFIE9_Pos)
-#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */
-#define CAN_TXBCIE_CFIE10 (0x1u << CAN_TXBCIE_CFIE10_Pos)
-#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */
-#define CAN_TXBCIE_CFIE11 (0x1u << CAN_TXBCIE_CFIE11_Pos)
-#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */
-#define CAN_TXBCIE_CFIE12 (0x1u << CAN_TXBCIE_CFIE12_Pos)
-#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */
-#define CAN_TXBCIE_CFIE13 (0x1u << CAN_TXBCIE_CFIE13_Pos)
-#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */
-#define CAN_TXBCIE_CFIE14 (0x1u << CAN_TXBCIE_CFIE14_Pos)
-#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */
-#define CAN_TXBCIE_CFIE15 (0x1u << CAN_TXBCIE_CFIE15_Pos)
-#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */
-#define CAN_TXBCIE_CFIE16 (0x1u << CAN_TXBCIE_CFIE16_Pos)
-#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */
-#define CAN_TXBCIE_CFIE17 (0x1u << CAN_TXBCIE_CFIE17_Pos)
-#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */
-#define CAN_TXBCIE_CFIE18 (0x1u << CAN_TXBCIE_CFIE18_Pos)
-#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */
-#define CAN_TXBCIE_CFIE19 (0x1u << CAN_TXBCIE_CFIE19_Pos)
-#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */
-#define CAN_TXBCIE_CFIE20 (0x1u << CAN_TXBCIE_CFIE20_Pos)
-#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */
-#define CAN_TXBCIE_CFIE21 (0x1u << CAN_TXBCIE_CFIE21_Pos)
-#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */
-#define CAN_TXBCIE_CFIE22 (0x1u << CAN_TXBCIE_CFIE22_Pos)
-#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */
-#define CAN_TXBCIE_CFIE23 (0x1u << CAN_TXBCIE_CFIE23_Pos)
-#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */
-#define CAN_TXBCIE_CFIE24 (0x1u << CAN_TXBCIE_CFIE24_Pos)
-#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */
-#define CAN_TXBCIE_CFIE25 (0x1u << CAN_TXBCIE_CFIE25_Pos)
-#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */
-#define CAN_TXBCIE_CFIE26 (0x1u << CAN_TXBCIE_CFIE26_Pos)
-#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */
-#define CAN_TXBCIE_CFIE27 (0x1u << CAN_TXBCIE_CFIE27_Pos)
-#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */
-#define CAN_TXBCIE_CFIE28 (0x1u << CAN_TXBCIE_CFIE28_Pos)
-#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */
-#define CAN_TXBCIE_CFIE29 (0x1u << CAN_TXBCIE_CFIE29_Pos)
-#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */
-#define CAN_TXBCIE_CFIE30 (0x1u << CAN_TXBCIE_CFIE30_Pos)
-#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */
-#define CAN_TXBCIE_CFIE31 (0x1u << CAN_TXBCIE_CFIE31_Pos)
-#define CAN_TXBCIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCIE) MASK Register */
-
-/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */
- uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */
-#define CAN_TXEFC_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */
-
-#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */
-#define CAN_TXEFC_EFSA_Msk (0xFFFFu << CAN_TXEFC_EFSA_Pos)
-#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos))
-#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */
-#define CAN_TXEFC_EFS_Msk (0x3Fu << CAN_TXEFC_EFS_Pos)
-#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos))
-#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */
-#define CAN_TXEFC_EFWM_Msk (0x3Fu << CAN_TXEFC_EFWM_Pos)
-#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos))
-#define CAN_TXEFC_MASK 0x3F3FFFFFu /**< \brief (CAN_TXEFC) MASK Register */
-
-/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */
- uint32_t :3; /*!< bit: 21..23 Reserved */
- uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */
- uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */
-#define CAN_TXEFS_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */
-
-#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */
-#define CAN_TXEFS_EFFL_Msk (0x3Fu << CAN_TXEFS_EFFL_Pos)
-#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos))
-#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */
-#define CAN_TXEFS_EFGI_Msk (0x1Fu << CAN_TXEFS_EFGI_Pos)
-#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos))
-#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */
-#define CAN_TXEFS_EFPI_Msk (0x1Fu << CAN_TXEFS_EFPI_Pos)
-#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos))
-#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */
-#define CAN_TXEFS_EFF (0x1u << CAN_TXEFS_EFF_Pos)
-#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */
-#define CAN_TXEFS_TEFL (0x1u << CAN_TXEFS_TEFL_Pos)
-#define CAN_TXEFS_MASK 0x031F1F3Fu /**< \brief (CAN_TXEFS) MASK Register */
-
-/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */
- uint32_t :27; /*!< bit: 5..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */
-#define CAN_TXEFA_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */
-
-#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */
-#define CAN_TXEFA_EFAI_Msk (0x1Fu << CAN_TXEFA_EFAI_Pos)
-#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos))
-#define CAN_TXEFA_MASK 0x0000001Fu /**< \brief (CAN_TXEFA) MASK Register */
-
-/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */
-#define CAN_RXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */
-
-#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */
-#define CAN_RXBE_0_ID_Msk (0x1FFFFFFFu << CAN_RXBE_0_ID_Pos)
-#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos))
-#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */
-#define CAN_RXBE_0_RTR (0x1u << CAN_RXBE_0_RTR_Pos)
-#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */
-#define CAN_RXBE_0_XTD (0x1u << CAN_RXBE_0_XTD_Pos)
-#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */
-#define CAN_RXBE_0_ESI (0x1u << CAN_RXBE_0_ESI_Pos)
-#define CAN_RXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_0) MASK Register */
-
-/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
- uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */
-#define CAN_RXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */
-
-#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */
-#define CAN_RXBE_1_RXTS_Msk (0xFFFFu << CAN_RXBE_1_RXTS_Pos)
-#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos))
-#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */
-#define CAN_RXBE_1_DLC_Msk (0xFu << CAN_RXBE_1_DLC_Pos)
-#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos))
-#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */
-#define CAN_RXBE_1_BRS (0x1u << CAN_RXBE_1_BRS_Pos)
-#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */
-#define CAN_RXBE_1_FDF (0x1u << CAN_RXBE_1_FDF_Pos)
-#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */
-#define CAN_RXBE_1_FIDX_Msk (0x7Fu << CAN_RXBE_1_FIDX_Pos)
-#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos))
-#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */
-#define CAN_RXBE_1_ANMF (0x1u << CAN_RXBE_1_ANMF_Pos)
-#define CAN_RXBE_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXBE_1) MASK Register */
-
-/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXBE_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */
-#define CAN_RXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */
-
-#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */
-#define CAN_RXBE_DATA_DB0_Msk (0xFFu << CAN_RXBE_DATA_DB0_Pos)
-#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos))
-#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */
-#define CAN_RXBE_DATA_DB1_Msk (0xFFu << CAN_RXBE_DATA_DB1_Pos)
-#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos))
-#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */
-#define CAN_RXBE_DATA_DB2_Msk (0xFFu << CAN_RXBE_DATA_DB2_Pos)
-#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos))
-#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */
-#define CAN_RXBE_DATA_DB3_Msk (0xFFu << CAN_RXBE_DATA_DB3_Pos)
-#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos))
-#define CAN_RXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_DATA) MASK Register */
-
-/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0E_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */
-#define CAN_RXF0E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */
-
-#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */
-#define CAN_RXF0E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF0E_0_ID_Pos)
-#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos))
-#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */
-#define CAN_RXF0E_0_RTR (0x1u << CAN_RXF0E_0_RTR_Pos)
-#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */
-#define CAN_RXF0E_0_XTD (0x1u << CAN_RXF0E_0_XTD_Pos)
-#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */
-#define CAN_RXF0E_0_ESI (0x1u << CAN_RXF0E_0_ESI_Pos)
-#define CAN_RXF0E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_0) MASK Register */
-
-/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
- uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0E_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */
-#define CAN_RXF0E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */
-
-#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */
-#define CAN_RXF0E_1_RXTS_Msk (0xFFFFu << CAN_RXF0E_1_RXTS_Pos)
-#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos))
-#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */
-#define CAN_RXF0E_1_DLC_Msk (0xFu << CAN_RXF0E_1_DLC_Pos)
-#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos))
-#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */
-#define CAN_RXF0E_1_BRS (0x1u << CAN_RXF0E_1_BRS_Pos)
-#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */
-#define CAN_RXF0E_1_FDF (0x1u << CAN_RXF0E_1_FDF_Pos)
-#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */
-#define CAN_RXF0E_1_FIDX_Msk (0x7Fu << CAN_RXF0E_1_FIDX_Pos)
-#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos))
-#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */
-#define CAN_RXF0E_1_ANMF (0x1u << CAN_RXF0E_1_ANMF_Pos)
-#define CAN_RXF0E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF0E_1) MASK Register */
-
-/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF0E_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */
-#define CAN_RXF0E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */
-
-#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */
-#define CAN_RXF0E_DATA_DB0_Msk (0xFFu << CAN_RXF0E_DATA_DB0_Pos)
-#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos))
-#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */
-#define CAN_RXF0E_DATA_DB1_Msk (0xFFu << CAN_RXF0E_DATA_DB1_Pos)
-#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos))
-#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */
-#define CAN_RXF0E_DATA_DB2_Msk (0xFFu << CAN_RXF0E_DATA_DB2_Pos)
-#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos))
-#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */
-#define CAN_RXF0E_DATA_DB3_Msk (0xFFu << CAN_RXF0E_DATA_DB3_Pos)
-#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos))
-#define CAN_RXF0E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_DATA) MASK Register */
-
-/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1E_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */
-#define CAN_RXF1E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */
-
-#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */
-#define CAN_RXF1E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF1E_0_ID_Pos)
-#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos))
-#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */
-#define CAN_RXF1E_0_RTR (0x1u << CAN_RXF1E_0_RTR_Pos)
-#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */
-#define CAN_RXF1E_0_XTD (0x1u << CAN_RXF1E_0_XTD_Pos)
-#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */
-#define CAN_RXF1E_0_ESI (0x1u << CAN_RXF1E_0_ESI_Pos)
-#define CAN_RXF1E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_0) MASK Register */
-
-/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
- uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1E_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */
-#define CAN_RXF1E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */
-
-#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */
-#define CAN_RXF1E_1_RXTS_Msk (0xFFFFu << CAN_RXF1E_1_RXTS_Pos)
-#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos))
-#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */
-#define CAN_RXF1E_1_DLC_Msk (0xFu << CAN_RXF1E_1_DLC_Pos)
-#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos))
-#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */
-#define CAN_RXF1E_1_BRS (0x1u << CAN_RXF1E_1_BRS_Pos)
-#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */
-#define CAN_RXF1E_1_FDF (0x1u << CAN_RXF1E_1_FDF_Pos)
-#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */
-#define CAN_RXF1E_1_FIDX_Msk (0x7Fu << CAN_RXF1E_1_FIDX_Pos)
-#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos))
-#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */
-#define CAN_RXF1E_1_ANMF (0x1u << CAN_RXF1E_1_ANMF_Pos)
-#define CAN_RXF1E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF1E_1) MASK Register */
-
-/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_RXF1E_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */
-#define CAN_RXF1E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */
-
-#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */
-#define CAN_RXF1E_DATA_DB0_Msk (0xFFu << CAN_RXF1E_DATA_DB0_Pos)
-#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos))
-#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */
-#define CAN_RXF1E_DATA_DB1_Msk (0xFFu << CAN_RXF1E_DATA_DB1_Pos)
-#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos))
-#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */
-#define CAN_RXF1E_DATA_DB2_Msk (0xFFu << CAN_RXF1E_DATA_DB2_Pos)
-#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos))
-#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */
-#define CAN_RXF1E_DATA_DB3_Msk (0xFFu << CAN_RXF1E_DATA_DB3_Pos)
-#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos))
-#define CAN_RXF1E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_DATA) MASK Register */
-
-/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */
- uint32_t :5; /*!< bit: 11..15 Reserved */
- uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */
- uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */
- uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_SIDFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */
-#define CAN_SIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */
-
-#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */
-#define CAN_SIDFE_0_SFID2_Msk (0x7FFu << CAN_SIDFE_0_SFID2_Pos)
-#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos))
-#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */
-#define CAN_SIDFE_0_SFID1_Msk (0x7FFu << CAN_SIDFE_0_SFID1_Pos)
-#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos))
-#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */
-#define CAN_SIDFE_0_SFEC_Msk (0x7u << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos))
-#define CAN_SIDFE_0_SFEC_DISABLE_Val 0x0u /**< \brief (CAN_SIDFE_0) Disable filter element */
-#define CAN_SIDFE_0_SFEC_STF0M_Val 0x1u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */
-#define CAN_SIDFE_0_SFEC_STF1M_Val 0x2u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */
-#define CAN_SIDFE_0_SFEC_REJECT_Val 0x3u /**< \brief (CAN_SIDFE_0) Reject ID if filter match */
-#define CAN_SIDFE_0_SFEC_PRIORITY_Val 0x4u /**< \brief (CAN_SIDFE_0) Set priority if filter match */
-#define CAN_SIDFE_0_SFEC_PRIF0M_Val 0x5u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */
-#define CAN_SIDFE_0_SFEC_PRIF1M_Val 0x6u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */
-#define CAN_SIDFE_0_SFEC_STRXBUF_Val 0x7u /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */
-#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */
-#define CAN_SIDFE_0_SFT_Msk (0x3u << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos))
-#define CAN_SIDFE_0_SFT_RANGE_Val 0x0u /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */
-#define CAN_SIDFE_0_SFT_DUAL_Val 0x1u /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */
-#define CAN_SIDFE_0_SFT_CLASSIC_Val 0x2u /**< \brief (CAN_SIDFE_0) Classic filter */
-#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_MASK 0xFFFF07FFu /**< \brief (CAN_SIDFE_0) MASK Register */
-
-/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */
-#define CAN_TXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */
-
-#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */
-#define CAN_TXBE_0_ID_Msk (0x1FFFFFFFu << CAN_TXBE_0_ID_Pos)
-#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos))
-#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */
-#define CAN_TXBE_0_RTR (0x1u << CAN_TXBE_0_RTR_Pos)
-#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */
-#define CAN_TXBE_0_XTD (0x1u << CAN_TXBE_0_XTD_Pos)
-#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */
-#define CAN_TXBE_0_ESI (0x1u << CAN_TXBE_0_ESI_Pos)
-#define CAN_TXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_0) MASK Register */
-
-/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t DLC:4; /*!< bit: 16..19 Identifier */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */
- uint32_t MM:8; /*!< bit: 24..31 Message Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */
-#define CAN_TXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */
-
-#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */
-#define CAN_TXBE_1_DLC_Msk (0xFu << CAN_TXBE_1_DLC_Pos)
-#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos))
-#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */
-#define CAN_TXBE_1_BRS (0x1u << CAN_TXBE_1_BRS_Pos)
-#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */
-#define CAN_TXBE_1_FDF (0x1u << CAN_TXBE_1_FDF_Pos)
-#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */
-#define CAN_TXBE_1_EFC (0x1u << CAN_TXBE_1_EFC_Pos)
-#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */
-#define CAN_TXBE_1_MM_Msk (0xFFu << CAN_TXBE_1_MM_Pos)
-#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos))
-#define CAN_TXBE_1_MASK 0xFFBF0000u /**< \brief (CAN_TXBE_1) MASK Register */
-
-/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
- uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
- uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
- uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXBE_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */
-#define CAN_TXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */
-
-#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */
-#define CAN_TXBE_DATA_DB0_Msk (0xFFu << CAN_TXBE_DATA_DB0_Pos)
-#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos))
-#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */
-#define CAN_TXBE_DATA_DB1_Msk (0xFFu << CAN_TXBE_DATA_DB1_Pos)
-#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos))
-#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */
-#define CAN_TXBE_DATA_DB2_Msk (0xFFu << CAN_TXBE_DATA_DB2_Pos)
-#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos))
-#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */
-#define CAN_TXBE_DATA_DB3_Msk (0xFFu << CAN_TXBE_DATA_DB3_Pos)
-#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos))
-#define CAN_TXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_DATA) MASK Register */
-
-/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t ID:29; /*!< bit: 0..28 Identifier */
- uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
- uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */
- uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */
-#define CAN_TXEFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */
-
-#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */
-#define CAN_TXEFE_0_ID_Msk (0x1FFFFFFFu << CAN_TXEFE_0_ID_Pos)
-#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos))
-#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */
-#define CAN_TXEFE_0_RTR (0x1u << CAN_TXEFE_0_RTR_Pos)
-#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */
-#define CAN_TXEFE_0_XTD (0x1u << CAN_TXEFE_0_XTD_Pos)
-#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */
-#define CAN_TXEFE_0_ESI (0x1u << CAN_TXEFE_0_ESI_Pos)
-#define CAN_TXEFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_0) MASK Register */
-
-/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */
- uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
- uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
- uint32_t FDF:1; /*!< bit: 21 FD Format */
- uint32_t ET:2; /*!< bit: 22..23 Event Type */
- uint32_t MM:8; /*!< bit: 24..31 Message Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_TXEFE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */
-#define CAN_TXEFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */
-
-#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */
-#define CAN_TXEFE_1_TXTS_Msk (0xFFFFu << CAN_TXEFE_1_TXTS_Pos)
-#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos))
-#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */
-#define CAN_TXEFE_1_DLC_Msk (0xFu << CAN_TXEFE_1_DLC_Pos)
-#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos))
-#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */
-#define CAN_TXEFE_1_BRS (0x1u << CAN_TXEFE_1_BRS_Pos)
-#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */
-#define CAN_TXEFE_1_FDF (0x1u << CAN_TXEFE_1_FDF_Pos)
-#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */
-#define CAN_TXEFE_1_ET_Msk (0x3u << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos))
-#define CAN_TXEFE_1_ET_TXE_Val 0x1u /**< \brief (CAN_TXEFE_1) Tx event */
-#define CAN_TXEFE_1_ET_TXC_Val 0x2u /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */
-#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */
-#define CAN_TXEFE_1_MM_Msk (0xFFu << CAN_TXEFE_1_MM_Pos)
-#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos))
-#define CAN_TXEFE_1_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_1) MASK Register */
-
-/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */
- uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */
-#define CAN_XIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */
-
-#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */
-#define CAN_XIDFE_0_EFID1_Msk (0x1FFFFFFFu << CAN_XIDFE_0_EFID1_Pos)
-#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos))
-#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */
-#define CAN_XIDFE_0_EFEC_Msk (0x7u << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos))
-#define CAN_XIDFE_0_EFEC_DISABLE_Val 0x0u /**< \brief (CAN_XIDFE_0) Disable filter element */
-#define CAN_XIDFE_0_EFEC_STF0M_Val 0x1u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */
-#define CAN_XIDFE_0_EFEC_STF1M_Val 0x2u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */
-#define CAN_XIDFE_0_EFEC_REJECT_Val 0x3u /**< \brief (CAN_XIDFE_0) Reject ID if filter match */
-#define CAN_XIDFE_0_EFEC_PRIORITY_Val 0x4u /**< \brief (CAN_XIDFE_0) Set priority if filter match */
-#define CAN_XIDFE_0_EFEC_PRIF0M_Val 0x5u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */
-#define CAN_XIDFE_0_EFEC_PRIF1M_Val 0x6u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */
-#define CAN_XIDFE_0_EFEC_STRXBUF_Val 0x7u /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */
-#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_XIDFE_0) MASK Register */
-
-/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */
- uint32_t :1; /*!< bit: 29 Reserved */
- uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CAN_XIDFE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */
-#define CAN_XIDFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */
-
-#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */
-#define CAN_XIDFE_1_EFID2_Msk (0x1FFFFFFFu << CAN_XIDFE_1_EFID2_Pos)
-#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos))
-#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */
-#define CAN_XIDFE_1_EFT_Msk (0x3u << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos))
-#define CAN_XIDFE_1_EFT_RANGEM_Val 0x0u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */
-#define CAN_XIDFE_1_EFT_DUAL_Val 0x1u /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */
-#define CAN_XIDFE_1_EFT_CLASSIC_Val 0x2u /**< \brief (CAN_XIDFE_1) Classic filter */
-#define CAN_XIDFE_1_EFT_RANGE_Val 0x3u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */
-#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_MASK 0xDFFFFFFFu /**< \brief (CAN_XIDFE_1) MASK Register */
-
-/** \brief CAN APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */
- __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */
- __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */
- __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */
- __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */
- __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */
- __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */
- __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */
- __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */
- __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */
- __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */
- __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */
- RoReg8 Reserved1[0x10];
- __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */
- __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */
- __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */
- RoReg8 Reserved2[0x4];
- __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */
- __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */
- __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */
- __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */
- RoReg8 Reserved3[0x20];
- __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */
- __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */
- __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */
- RoReg8 Reserved4[0x4];
- __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */
- __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */
- __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */
- __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */
- __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */
- __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */
- __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */
- __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */
- __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */
- __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */
- __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */
- __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */
- __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */
- __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */
- __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */
- __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */
- __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */
- __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */
- __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */
- __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */
- __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */
- __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */
- RoReg8 Reserved5[0x8];
- __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */
- __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */
- __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */
-} Can;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxbe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */
- __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */
- __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */
-} CanMramRxbe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxf0e hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */
- __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */
- __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */
-} CanMramRxf0e
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxf1e hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */
- __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */
- __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */
-} CanMramRxf1e
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_sidfe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */
-} CanMramSidfe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_txbe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */
- __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */
- __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */
-} CanMramTxbe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_txefe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */
- __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */
-} CanMramTxefe
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_xifde hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */
- __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */
-} CanMramXifde
-#ifdef __GNUC__
- __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_CAN_MRAM_RXBE
-
-#define SECTION_CAN_MRAM_RXF0E
-
-#define SECTION_CAN_MRAM_RXF1E
-
-#define SECTION_CAN_MRAM_SIDFE
-
-#define SECTION_CAN_MRAM_TXBE
-
-#define SECTION_CAN_MRAM_TXEFE
-
-#define SECTION_CAN_MRAM_XIFDE
-
-/*@}*/
-
-#endif /* _SAMD51_CAN_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h
deleted file mode 100644
index 890e81edf631..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for CCL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CCL_COMPONENT_
-#define _SAMD51_CCL_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR CCL */
-/* ========================================================================== */
-/** \addtogroup SAMD51_CCL Configurable Custom Logic */
-/*@{*/
-
-#define CCL_U2225
-#define REV_CCL 0x110
-
-/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} CCL_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
-#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
-
-#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
-#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
-#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
-#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
-#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */
-#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
-#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
-
-/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} CCL_SEQCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
-#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
-
-#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
-#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
-#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
-#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
-#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
-#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
-#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
-#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
-
-/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
- uint32_t :2; /*!< bit: 2.. 3 Reserved */
- uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
- uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
- uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
- uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
- uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */
- uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */
- uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CCL_LUTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
-#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
-
-#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
-#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
-#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
-#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
-#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
-#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
-#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
-#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
-#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
-#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
-#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
-#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
-#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
-#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
-#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
-#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
-#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
-#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
-#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
-#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
-#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
-#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
-#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
-#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
-#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
-#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
-#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
-#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
-#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
-#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
-#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
-#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
-#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
-#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
-#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
-#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
-#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
-#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
-#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
-#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
-
-/** \brief CCL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- RoReg8 Reserved1[0x3];
- __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
- RoReg8 Reserved2[0x2];
- __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
-} Ccl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_CCL_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h
deleted file mode 100644
index 92fa6813ef83..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for CMCC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CMCC_COMPONENT_
-#define _SAMD51_CMCC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR CMCC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */
-/*@{*/
-
-#define CMCC_U2015
-#define REV_CMCC 0x600
-
-/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */
- uint32_t :2; /*!< bit: 2.. 3 Reserved */
- uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */
- uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */
- uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */
- uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */
- uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */
- uint32_t :18; /*!< bit: 14..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_TYPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */
-#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
-
-#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
-#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
-#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */
-#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
-#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */
-#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
-#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
-#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */
-#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */
-#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */
-#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
-#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */
-#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
-#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */
-#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
-#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
-
-/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */
- uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_CFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */
-#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
-
-#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */
-#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
-#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */
-#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
-#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */
-#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
-
-/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */
-#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
-
-#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */
-#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
-#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
-
-/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_SR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */
-#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
-
-#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */
-#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
-#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
-
-/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_LCKWAY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
-#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
-
-#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */
-#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
-#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
-#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
-
-/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MAINT0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
-#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
-
-#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
-#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
-#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
-
-/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */
- uint32_t :16; /*!< bit: 12..27 Reserved */
- uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MAINT1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
-#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
-
-#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */
-#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
-#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
-#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */
-#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
-#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
-
-/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
-#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
-
-#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
-#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
-#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */
-#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */
-#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */
-#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
-
-/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
-#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
-
-#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
-#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
-#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
-
-/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
-#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
-
-#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
-#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
-#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
-
-/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} CMCC_MSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
-#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
-
-#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */
-#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
-#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
-#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
-
-/** \brief CMCC APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */
- __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
- __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
- __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */
- __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
- RoReg8 Reserved1[0xC];
- __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
- __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
- __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
- __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
- __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
- __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */
-} Cmcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_CMCC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h
deleted file mode 100644
index c67efda303e2..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h
+++ /dev/null
@@ -1,544 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for DAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DAC_COMPONENT_
-#define _SAMD51_DAC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR DAC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */
-/*@{*/
-
-#define DAC_U2502
-#define REV_DAC 0x100
-
-/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */
-#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
-
-#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
-#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
-#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */
-#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
-#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */
-
-/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */
- uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */
-#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */
-
-#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */
-#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
-#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
-#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
-#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */
-#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */
-#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */
-#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */
-#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */
-
-/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */
- uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */
- uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */
- uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */
- uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */
- uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */
- uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */
- uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */
- uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */
- uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */
- uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */
-#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
-
-#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
-#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
-#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
-#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
-#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
-#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
-#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
-#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
-#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
-#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
-#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
-#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
-#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
-#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
-#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
-#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
-#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
-#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
-#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
-#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
-#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
-#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */
-#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
-#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */
-#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
-#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */
-#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
-#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
-#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */
-
-/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
- uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
- uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
- uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
- uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
- uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
- uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
- uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
- uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
- uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
- uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
-#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
-#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
-#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
-#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
-#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
-#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
-#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
-#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
-#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
-#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
-#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
-#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
-#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
-#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
-#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
-#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
-#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */
-
-/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
- uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
- uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
- uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
- uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
- uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
- uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
- uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
- uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
- uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
- uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
-#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
-
-#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
-#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
-#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
-#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
-#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
-#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
-#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
-#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
-#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
-#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
-#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
-#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
-#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */
-#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
-#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */
-#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
-#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */
-#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
-#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
-#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */
-
-/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */
- __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */
- __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */
- __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */
- __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */
- __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */
- __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */
- __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */
- __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */
- __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */
- __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */
-#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
-#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */
-#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
-#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */
-#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
-#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
-#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
-#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
-#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
-#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
-#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
-#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
-#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
-#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */
-#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
-#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */
-#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
-#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */
-#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
-#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
-#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */
-#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
-#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */
-#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
-#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */
-#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
-#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
-#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */
-
-/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */
- uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */
- uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */
- uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */
- uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */
-#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
-
-#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
-#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)
-#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
-#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)
-#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */
-#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)
-#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
-#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
-#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)
-#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
-#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)
-#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */
-#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)
-#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
-#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */
-
-/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */
- uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */
- uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */
- uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */
- uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */
- uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */
- uint32_t :26; /*!< bit: 6..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DAC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
-#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */
-#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
-#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
-#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
-#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
-#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
-#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
-#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
-#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */
-#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
-#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
-#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
-#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
-#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
-#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
-#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
-#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
-#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
-#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
-
-/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */
- uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */
- uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */
- uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */
- uint16_t :1; /*!< bit: 12 Reserved */
- uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_DACCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */
-#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
-
-#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */
-#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
-#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */
-#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
-#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */
-#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
-#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */
-#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */
-#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */
-#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */
-#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
-#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */
-#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
-#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */
-#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
-#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */
-#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
-#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
-#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */
-#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
-#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
-#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */
-
-/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */
-#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */
-
-#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */
-#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
-#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
-#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
-
-/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_DATABUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
-#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
-
-#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
-#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
-#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
-#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
-
-/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DAC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */
-#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
-
-#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */
-#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
-#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */
-
-/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DAC_RESULT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */
-#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */
-
-#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */
-#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
-#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
-#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */
-
-/** \brief DAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
- __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */
- __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
- RoReg8 Reserved1[0x1];
- __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */
- __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
- __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
- __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
- __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x3];
- __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */
-} Dac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_DAC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h
deleted file mode 100644
index 295b31fe488a..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h
+++ /dev/null
@@ -1,1416 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for DMAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DMAC_COMPONENT_
-#define _SAMD51_DMAC_COMPONENT_
-
-/* ========================================================================== */
-/** SOFTWARE API DEFINITION FOR DMAC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_DMAC Direct Memory Access Controller */
-/*@{*/
-
-#define DMAC_U2503
-#define REV_DMAC 0x100
-
-/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
- uint16_t :6; /*!< bit: 2.. 7 Reserved */
- uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
- uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
- uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
- uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :8; /*!< bit: 0.. 7 Reserved */
- uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
-#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */
-
-#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
-#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
-#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
-#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
-#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
-#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
-#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
-#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
-#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
-#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
-#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
-#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
-#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
-#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
-#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
-#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */
-
-/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
- uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
- uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_CRCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
-#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
-
-#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
-#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
-#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
-#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
-#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
-#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
-#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
-#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
-#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
-#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
-#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
-#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */
-#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */
-#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */
-#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
-#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */
-#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */
-#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */
-#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */
-
-/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_CRCDATAIN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
-#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
-
-#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
-#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
-#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
-#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
-
-/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_CRCCHKSUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
-#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
-
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
-#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
-#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
-
-/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
- uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
- uint8_t CRCERR:1; /*!< bit: 2 CRC Error */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CRCSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
-#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
-
-#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
-#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
-#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
-#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
-#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */
-#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
-#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */
-
-/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
-#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
-
-#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
-#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
-#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */
-
-/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
- uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
- uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
- uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
- uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
- uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
- uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
- uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
- uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
- uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
- uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
- uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
- uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */
- uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */
- uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */
- uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */
- uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */
- uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */
- uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */
- uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */
- uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */
- uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */
- uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */
- uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */
- uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */
- uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */
- uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */
- uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */
- uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */
- uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */
- uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */
- uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_SWTRIGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
-#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
-
-#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
-#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
-
-/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */
- uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */
- uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
- uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */
- uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */
- uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
- uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */
- uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */
- uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
- uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */
- uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */
- uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_PRICTRL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
-#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
-
-#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
-#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
-#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */
-#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
-#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
-#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
-#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
-#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */
-#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
-#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
-#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
-#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
-#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */
-#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
-#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
-#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
-#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
-#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */
-#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
-#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
-#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */
-
-/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t TERR:1; /*!< bit: 8 Transfer Error */
- uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
- uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t CRCERR:1; /*!< bit: 12 CRC Error */
- uint16_t FERR:1; /*!< bit: 13 Fetch Error */
- uint16_t BUSY:1; /*!< bit: 14 Busy */
- uint16_t PEND:1; /*!< bit: 15 Pending */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_INTPEND_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
-#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
-
-#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
-#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
-#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
-#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
-#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
-#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
-#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
-#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
-#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
-#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */
-#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
-#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
-#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
-#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
-#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
-#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
-#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
-#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */
-
-/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
- uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
- uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
- uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
- uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
- uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
- uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
- uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
- uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
- uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
- uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
- uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
- uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */
- uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */
- uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */
- uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */
- uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */
- uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */
- uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */
- uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */
- uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */
- uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */
- uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */
- uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */
- uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */
- uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */
- uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */
- uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */
- uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */
- uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */
- uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */
- uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_INTSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
-#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
-
-#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
-#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
-#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
-#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
-#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
-#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
-#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
-#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
-#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
-#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
-#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
-#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
-#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
-#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
-#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
-#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
-#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
-#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
-#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
-#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
-#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
-#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
-#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
-#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
-#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
-#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
-#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
-#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
-#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
-#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
-#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
-#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
-#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
-#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
-#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
-
-/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
- uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
- uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
- uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
- uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
- uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
- uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
- uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
- uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
- uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
- uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
- uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
- uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */
- uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */
- uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */
- uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */
- uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */
- uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */
- uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */
- uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */
- uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */
- uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */
- uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */
- uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */
- uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */
- uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */
- uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */
- uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */
- uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */
- uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */
- uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */
- uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_BUSYCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
-#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
-
-#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
-#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
-#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
-#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
-#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
-#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
-#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
-#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
-#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
-#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
-#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
-#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
-#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
-#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
-#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
-#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
-#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
-#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
-#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
-#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
-#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
-#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
-#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
-#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
-#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */
-#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
-#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */
-#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
-#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */
-#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
-#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */
-#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
-#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */
-#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
-#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */
-#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
-#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */
-#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
-#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */
-#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
-#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */
-#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
-#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */
-#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
-#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */
-#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
-#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */
-#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
-#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */
-#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
-#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */
-#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
-#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */
-#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
-#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */
-#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
-#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */
-#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
-#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */
-#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
-#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */
-#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
-#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */
-#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
-#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
-#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
-#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
-#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */
-
-/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
- uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
- uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
- uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
- uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
- uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
- uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
- uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
- uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
- uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
- uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
- uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
- uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */
- uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */
- uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */
- uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */
- uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */
- uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */
- uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */
- uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */
- uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */
- uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */
- uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */
- uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */
- uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */
- uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */
- uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */
- uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */
- uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */
- uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */
- uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */
- uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_PENDCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
-#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
-
-#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
-#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
-#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
-#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
-#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
-#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
-#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
-#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
-#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
-#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
-#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
-#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
-#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
-#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
-#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
-#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
-#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
-#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
-#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
-#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
-#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
-#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
-#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
-#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
-#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */
-#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
-#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */
-#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
-#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */
-#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
-#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */
-#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
-#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */
-#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
-#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */
-#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
-#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */
-#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
-#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */
-#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
-#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */
-#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
-#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */
-#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
-#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */
-#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
-#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */
-#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
-#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */
-#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
-#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */
-#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
-#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */
-#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
-#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */
-#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
-#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */
-#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
-#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */
-#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
-#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */
-#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
-#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */
-#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
-#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
-#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
-#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
-#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */
-
-/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
- uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
- uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
- uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
- uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_ACTIVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
-#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
-
-#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
-#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
-#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
-#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
-#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
-#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
-#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
-#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
-#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
-#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
-#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
-#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
-#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
-#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
-#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
-
-/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_BASEADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
-#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
-
-#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
-#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
-#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
-#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
-
-/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_WRBADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
-#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
-
-#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
-#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
-#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
-#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
-
-/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */
- uint32_t :4; /*!< bit: 2.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */
- uint32_t :5; /*!< bit: 15..19 Reserved */
- uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */
- uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */
- uint32_t :2; /*!< bit: 30..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
-} DMAC_CHCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */
-#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */
-
-#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
-#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
-#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
-#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
-#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */
-#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
-#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */
-#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
-#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
-#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */
-#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
-#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */
-#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
-#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */
-#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */
-#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */
-#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */
-#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
-#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */
-#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */
-#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
-#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */
-#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */
-#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */
-#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */
-#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */
-
-/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */
-#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */
-
-#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */
-#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
-#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */
-#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
-#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */
-#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */
-
-/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHPRILVL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */
-#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */
-
-#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */
-#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
-#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */
-#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */
-#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */
-#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */
-#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */
-#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */
-#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */
-#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */
-#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */
-
-/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */
- uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */
- uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHEVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */
-#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */
-
-#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */
-#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
-#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */
-#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */
-#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */
-#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */
-#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */
-#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */
-#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */
-#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */
-#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */
-#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
-#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */
-#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */
-#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */
-#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
-#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */
-#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
-#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */
-
-/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */
-#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
-
-#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
-#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
-#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
-#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
-#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */
-
-/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */
-#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */
-
-#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
-#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
-#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
-#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
-#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */
-
-/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
- __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
- __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
- __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
-#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
-
-#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
-#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
-#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
-#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
-#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
-#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
-#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */
-
-/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint8_t PEND:1; /*!< bit: 0 Channel Pending */
- uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
- uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
- uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
-} DMAC_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */
-#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */
-
-#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
-#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
-#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
-#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
-#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
-#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
-#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */
-#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
-#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */
-
-/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
- struct {
- uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
- uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */
- uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
- uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
- uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
- uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
- uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} DMAC_BTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
-#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
-
-#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
-#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
-#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */
-#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
-#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */
-#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */
-#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */
-#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
-#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
-#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
-#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
-#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
-#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
-#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
-#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
-#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
-#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
-#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
-#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
-#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
-#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
-#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
-#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
-#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
-#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
-#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
-#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
-#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits
-#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM
-#define USB_EPT_NUM 8 // Number of USB end points
-#define USB_GCLK_ID 10 // Index of Generic Clock
-#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value
-#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value
-#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented
-#define USB_PIPE_NUM 8 // Number of USB pipes
-#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system
-#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...)
-#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode
-#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested
-#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode
-
-#endif /* _SAMD51_USB_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h
deleted file mode 100644
index 98a2ca13d719..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for WDT
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_WDT_INSTANCE_
-#define _SAMD51_WDT_INSTANCE_
-
-/* ========== Register definition for WDT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */
-#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */
-#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */
-#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */
-#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */
-#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */
-#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */
-#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */
-#else
-#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */
-#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */
-#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */
-#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */
-#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */
-#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
-#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */
-#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-
-#endif /* _SAMD51_WDT_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h
deleted file mode 100644
index d8fa56d5baae..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h
+++ /dev/null
@@ -1,1863 +0,0 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD51J18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51J18A_PIO_
-#define _SAMD51J18A_PIO_
-
-#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
-#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
-#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
-#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
-#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
-#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
-#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
-#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
-#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
-#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
-#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
-#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
-#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
-#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
-#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
-#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
-#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
-#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
-#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
-#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
-#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
-#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
-#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
-#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
-#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
-#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */
-#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
-#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */
-#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
-#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
-#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
-#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
-#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
-#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
-#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
-#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
-#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
-#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
-#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
-#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
-#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
-#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */
-#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
-#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */
-#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
-#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
-#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
-#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
-#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
-#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
-#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
-#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
-#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
-#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
-#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
-#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
-#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
-#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
-#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
-#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */
-#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
-#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */
-#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
-#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */
-#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
-#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */
-#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
-#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */
-#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
-#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */
-#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
-#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */
-#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
-#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */
-#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
-#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */
-#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
-#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */
-#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
-#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */
-#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
-#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */
-#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
-#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */
-#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
-#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */
-#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
-#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */
-#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
-#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */
-#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
-#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */
-#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
-#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */
-#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
-#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */
-#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
-#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */
-#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
-#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */
-#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
-#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */
-/* ========== PORT definition for CM4 peripheral ========== */
-#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
-#define MUX_PA30H_CM4_SWCLK _L_(7)
-#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
-#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30)
-#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
-#define MUX_PB30H_CM4_SWO _L_(7)
-#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
-#define PORT_PB30H_CM4_SWO (_UL_(1) << 30)
-/* ========== PORT definition for ANAREF peripheral ========== */
-#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
-#define MUX_PA03B_ANAREF_VREF0 _L_(1)
-#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
-#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3)
-#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
-#define MUX_PA04B_ANAREF_VREF1 _L_(1)
-#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
-#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4)
-#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
-#define MUX_PA06B_ANAREF_VREF2 _L_(1)
-#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
-#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6)
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
-#define MUX_PA30M_GCLK_IO0 _L_(12)
-#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
-#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30)
-#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
-#define MUX_PB14M_GCLK_IO0 _L_(12)
-#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
-#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14)
-#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
-#define MUX_PA14M_GCLK_IO0 _L_(12)
-#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
-#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14)
-#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
-#define MUX_PB22M_GCLK_IO0 _L_(12)
-#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
-#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22)
-#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
-#define MUX_PB15M_GCLK_IO1 _L_(12)
-#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
-#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15)
-#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
-#define MUX_PA15M_GCLK_IO1 _L_(12)
-#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
-#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15)
-#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
-#define MUX_PB23M_GCLK_IO1 _L_(12)
-#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
-#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23)
-#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
-#define MUX_PA27M_GCLK_IO1 _L_(12)
-#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
-#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27)
-#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
-#define MUX_PA16M_GCLK_IO2 _L_(12)
-#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
-#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16)
-#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
-#define MUX_PB16M_GCLK_IO2 _L_(12)
-#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
-#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16)
-#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
-#define MUX_PA17M_GCLK_IO3 _L_(12)
-#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
-#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17)
-#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
-#define MUX_PB17M_GCLK_IO3 _L_(12)
-#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
-#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17)
-#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
-#define MUX_PA10M_GCLK_IO4 _L_(12)
-#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
-#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10)
-#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
-#define MUX_PB10M_GCLK_IO4 _L_(12)
-#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
-#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10)
-#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
-#define MUX_PA11M_GCLK_IO5 _L_(12)
-#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
-#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11)
-#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
-#define MUX_PB11M_GCLK_IO5 _L_(12)
-#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
-#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11)
-#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
-#define MUX_PB12M_GCLK_IO6 _L_(12)
-#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
-#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12)
-#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
-#define MUX_PB13M_GCLK_IO7 _L_(12)
-#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
-#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0 _L_(0)
-#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
-#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
-#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0 _L_(0)
-#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0 _L_(0)
-#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0)
-#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
-#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0 _L_(0)
-#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16)
-#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
-#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1 _L_(0)
-#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
-#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1 _L_(0)
-#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1 _L_(0)
-#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1)
-#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
-#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1 _L_(0)
-#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17)
-#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2 _L_(0)
-#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
-#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2 _L_(0)
-#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2 _L_(0)
-#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2)
-#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3 _L_(0)
-#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
-#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3 _L_(0)
-#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3 _L_(0)
-#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3)
-#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4 _L_(0)
-#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
-#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4 _L_(0)
-#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20)
-#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
-#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4 _L_(0)
-#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4)
-#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5 _L_(0)
-#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
-#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5 _L_(0)
-#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21)
-#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
-#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5 _L_(0)
-#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5)
-#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6 _L_(0)
-#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
-#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6 _L_(0)
-#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6 _L_(0)
-#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6)
-#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
-#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6 _L_(0)
-#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22)
-#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7 _L_(0)
-#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
-#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7 _L_(0)
-#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7 _L_(0)
-#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7)
-#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
-#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7 _L_(0)
-#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23)
-#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT8 _L_(0)
-#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
-#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8 _L_(0)
-#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8)
-#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9 _L_(0)
-#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
-#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT9 _L_(0)
-#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
-#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9 _L_(0)
-#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9)
-#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10 _L_(0)
-#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10 _L_(0)
-#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10)
-#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11 _L_(0)
-#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT11 _L_(0)
-#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
-#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27)
-#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
-#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11 _L_(0)
-#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11)
-#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
-#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12 _L_(0)
-#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12)
-#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
-#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12 _L_(0)
-#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12)
-#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
-#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13 _L_(0)
-#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13)
-#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
-#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13 _L_(0)
-#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13)
-#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT14 _L_(0)
-#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
-#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14 _L_(0)
-#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14)
-#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
-#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14 _L_(0)
-#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30)
-#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14 _L_(0)
-#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15 _L_(0)
-#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT15 _L_(0)
-#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
-#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15 _L_(0)
-#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15)
-#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
-#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15 _L_(0)
-#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31)
-#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
-#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI _L_(0)
-#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
-#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
-#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
-#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
-#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
-#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
-#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
-#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
-#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
-#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
-#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
-#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
-#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
-#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
-#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
-#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
-#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
-#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
-#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
-#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
-#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
-#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
-#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
-#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
-#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
-#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
-#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
-#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
-#define MUX_PB22C_SERCOM1_PAD2 _L_(2)
-#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
-#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22)
-#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
-#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
-#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
-#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
-#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
-#define MUX_PB23C_SERCOM1_PAD3 _L_(2)
-#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
-#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23)
-/* ========== PORT definition for TC0 peripheral ========== */
-#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TC0_WO0 _L_(4)
-#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
-#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4)
-#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TC0_WO0 _L_(4)
-#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
-#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8)
-#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TC0_WO0 _L_(4)
-#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
-#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30)
-#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TC0_WO1 _L_(4)
-#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
-#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5)
-#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TC0_WO1 _L_(4)
-#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
-#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9)
-#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TC0_WO1 _L_(4)
-#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
-#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31)
-/* ========== PORT definition for TC1 peripheral ========== */
-#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TC1_WO0 _L_(4)
-#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
-#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6)
-#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TC1_WO0 _L_(4)
-#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
-#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10)
-#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TC1_WO1 _L_(4)
-#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
-#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7)
-#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TC1_WO1 _L_(4)
-#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
-#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */
-#define MUX_PA24H_USB_DM _L_(7)
-#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
-#define PORT_PA24H_USB_DM (_UL_(1) << 24)
-#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */
-#define MUX_PA25H_USB_DP _L_(7)
-#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
-#define PORT_PA25H_USB_DP (_UL_(1) << 25)
-#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
-#define MUX_PA23H_USB_SOF_1KHZ _L_(7)
-#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
-#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23)
-#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
-#define MUX_PB22H_USB_SOF_1KHZ _L_(7)
-#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
-#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD0 _L_(3)
-#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
-#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9)
-#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0 _L_(2)
-#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12)
-#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD1 _L_(3)
-#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
-#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8)
-#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1 _L_(2)
-#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13)
-#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
-#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
-#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
-#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
-#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
-#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
-#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
-#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD0 _L_(3)
-#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
-#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17)
-#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
-#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
-#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD1 _L_(3)
-#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
-#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16)
-#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
-#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
-#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
-#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
-#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2 _L_(3)
-#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20)
-#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
-#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
-#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
-#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
-#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3 _L_(3)
-#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21)
-#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
-#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
-#define MUX_PA20G_TCC0_WO0 _L_(6)
-#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
-#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20)
-#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
-#define MUX_PB12G_TCC0_WO0 _L_(6)
-#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
-#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12)
-#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
-#define MUX_PA08F_TCC0_WO0 _L_(5)
-#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
-#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8)
-#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
-#define MUX_PA21G_TCC0_WO1 _L_(6)
-#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
-#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21)
-#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
-#define MUX_PB13G_TCC0_WO1 _L_(6)
-#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
-#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13)
-#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
-#define MUX_PA09F_TCC0_WO1 _L_(5)
-#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
-#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9)
-#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
-#define MUX_PA22G_TCC0_WO2 _L_(6)
-#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
-#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22)
-#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
-#define MUX_PB14G_TCC0_WO2 _L_(6)
-#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
-#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14)
-#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2 _L_(5)
-#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
-#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
-#define MUX_PA23G_TCC0_WO3 _L_(6)
-#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
-#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23)
-#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
-#define MUX_PB15G_TCC0_WO3 _L_(6)
-#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
-#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15)
-#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3 _L_(5)
-#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
-#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
-#define MUX_PA16G_TCC0_WO4 _L_(6)
-#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
-#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16)
-#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
-#define MUX_PB16G_TCC0_WO4 _L_(6)
-#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
-#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16)
-#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4 _L_(5)
-#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10)
-#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
-#define MUX_PA17G_TCC0_WO5 _L_(6)
-#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
-#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17)
-#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
-#define MUX_PB17G_TCC0_WO5 _L_(6)
-#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
-#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17)
-#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5 _L_(5)
-#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11)
-#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
-#define MUX_PA18G_TCC0_WO6 _L_(6)
-#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
-#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18)
-#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
-#define MUX_PB30G_TCC0_WO6 _L_(6)
-#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
-#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30)
-#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6 _L_(5)
-#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12)
-#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
-#define MUX_PA19G_TCC0_WO7 _L_(6)
-#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
-#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19)
-#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
-#define MUX_PB31G_TCC0_WO7 _L_(6)
-#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
-#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31)
-#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7 _L_(5)
-#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
-#define MUX_PB10G_TCC1_WO0 _L_(6)
-#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
-#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10)
-#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
-#define MUX_PA16F_TCC1_WO0 _L_(5)
-#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
-#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16)
-#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
-#define MUX_PB11G_TCC1_WO1 _L_(6)
-#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
-#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11)
-#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
-#define MUX_PA17F_TCC1_WO1 _L_(5)
-#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
-#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17)
-#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
-#define MUX_PA12G_TCC1_WO2 _L_(6)
-#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
-#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12)
-#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
-#define MUX_PA14G_TCC1_WO2 _L_(6)
-#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
-#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14)
-#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC1_WO2 _L_(5)
-#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
-#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18)
-#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
-#define MUX_PA13G_TCC1_WO3 _L_(6)
-#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
-#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13)
-#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
-#define MUX_PA15G_TCC1_WO3 _L_(6)
-#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
-#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15)
-#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC1_WO3 _L_(5)
-#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
-#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19)
-#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
-#define MUX_PA08G_TCC1_WO4 _L_(6)
-#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
-#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8)
-#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
-#define MUX_PA20F_TCC1_WO4 _L_(5)
-#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
-#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20)
-#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
-#define MUX_PA09G_TCC1_WO5 _L_(6)
-#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
-#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9)
-#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
-#define MUX_PA21F_TCC1_WO5 _L_(5)
-#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
-#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21)
-#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
-#define MUX_PA10G_TCC1_WO6 _L_(6)
-#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
-#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10)
-#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
-#define MUX_PA22F_TCC1_WO6 _L_(5)
-#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
-#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22)
-#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
-#define MUX_PA11G_TCC1_WO7 _L_(6)
-#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
-#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11)
-#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
-#define MUX_PA23F_TCC1_WO7 _L_(5)
-#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
-#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23)
-/* ========== PORT definition for TC2 peripheral ========== */
-#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TC2_WO0 _L_(4)
-#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
-#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12)
-#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TC2_WO0 _L_(4)
-#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
-#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16)
-#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TC2_WO0 _L_(4)
-#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
-#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0)
-#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TC2_WO1 _L_(4)
-#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
-#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1)
-#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TC2_WO1 _L_(4)
-#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
-#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13)
-#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TC2_WO1 _L_(4)
-#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
-#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0 _L_(4)
-#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18)
-#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0 _L_(4)
-#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14)
-#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1 _L_(4)
-#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15)
-#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1 _L_(4)
-#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19)
-/* ========== PORT definition for TAL peripheral ========== */
-#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */
-#define MUX_PA27H_TAL_BRK _L_(7)
-#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK)
-#define PORT_PA27H_TAL_BRK (_UL_(1) << 27)
-#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */
-#define MUX_PB31H_TAL_BRK _L_(7)
-#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK)
-#define PORT_PB31H_TAL_BRK (_UL_(1) << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
-#define MUX_PA14F_TCC2_WO0 _L_(5)
-#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
-#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14)
-#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
-#define MUX_PA30F_TCC2_WO0 _L_(5)
-#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
-#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30)
-#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
-#define MUX_PA15F_TCC2_WO1 _L_(5)
-#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
-#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15)
-#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
-#define MUX_PA31F_TCC2_WO1 _L_(5)
-#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
-#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31)
-#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC2_WO2 _L_(5)
-#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
-#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24)
-#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
-#define MUX_PB02F_TCC2_WO2 _L_(5)
-#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
-#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
-#define MUX_PB12F_TCC3_WO0 _L_(5)
-#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
-#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12)
-#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
-#define MUX_PB16F_TCC3_WO0 _L_(5)
-#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
-#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16)
-#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
-#define MUX_PB13F_TCC3_WO1 _L_(5)
-#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
-#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13)
-#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
-#define MUX_PB17F_TCC3_WO1 _L_(5)
-#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
-#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0 _L_(4)
-#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22)
-#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0 _L_(4)
-#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8)
-#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0 _L_(4)
-#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12)
-#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1 _L_(4)
-#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23)
-#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1 _L_(4)
-#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9)
-#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1 _L_(4)
-#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0 _L_(4)
-#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24)
-#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0 _L_(4)
-#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10)
-#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0 _L_(4)
-#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14)
-#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1 _L_(4)
-#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25)
-#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1 _L_(4)
-#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11)
-#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1 _L_(4)
-#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15)
-/* ========== PORT definition for PDEC peripheral ========== */
-#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
-#define MUX_PB23G_PDEC_QDI0 _L_(6)
-#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
-#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23)
-#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
-#define MUX_PA24G_PDEC_QDI0 _L_(6)
-#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
-#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24)
-#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
-#define MUX_PA25G_PDEC_QDI1 _L_(6)
-#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
-#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25)
-#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
-#define MUX_PB22G_PDEC_QDI2 _L_(6)
-#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
-#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0 _L_(1)
-#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
-#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1 _L_(1)
-#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
-#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2 _L_(1)
-#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
-#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3 _L_(1)
-#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
-#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
-#define MUX_PA12M_AC_CMP0 _L_(12)
-#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
-#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12)
-#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
-#define MUX_PA18M_AC_CMP0 _L_(12)
-#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
-#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18)
-#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
-#define MUX_PA13M_AC_CMP1 _L_(12)
-#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
-#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13)
-#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
-#define MUX_PA19M_AC_CMP1 _L_(12)
-#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
-#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19)
-/* ========== PORT definition for QSPI peripheral ========== */
-#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
-#define MUX_PB11H_QSPI_CS _L_(7)
-#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
-#define PORT_PB11H_QSPI_CS (_UL_(1) << 11)
-#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
-#define MUX_PA08H_QSPI_DATA0 _L_(7)
-#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
-#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8)
-#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
-#define MUX_PA09H_QSPI_DATA1 _L_(7)
-#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
-#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9)
-#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
-#define MUX_PA10H_QSPI_DATA2 _L_(7)
-#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
-#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10)
-#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
-#define MUX_PA11H_QSPI_DATA3 _L_(7)
-#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
-#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11)
-#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
-#define MUX_PB10H_QSPI_SCK _L_(7)
-#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
-#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10)
-/* ========== PORT definition for CCL peripheral ========== */
-#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
-#define MUX_PA04N_CCL_IN0 _L_(13)
-#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
-#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4)
-#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
-#define MUX_PA16N_CCL_IN0 _L_(13)
-#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
-#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16)
-#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
-#define MUX_PB22N_CCL_IN0 _L_(13)
-#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
-#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22)
-#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
-#define MUX_PA05N_CCL_IN1 _L_(13)
-#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
-#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5)
-#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
-#define MUX_PA17N_CCL_IN1 _L_(13)
-#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
-#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17)
-#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
-#define MUX_PB00N_CCL_IN1 _L_(13)
-#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
-#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0)
-#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
-#define MUX_PA06N_CCL_IN2 _L_(13)
-#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
-#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6)
-#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
-#define MUX_PA18N_CCL_IN2 _L_(13)
-#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
-#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18)
-#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
-#define MUX_PB01N_CCL_IN2 _L_(13)
-#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
-#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1)
-#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
-#define MUX_PA08N_CCL_IN3 _L_(13)
-#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
-#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8)
-#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
-#define MUX_PA30N_CCL_IN3 _L_(13)
-#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
-#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30)
-#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
-#define MUX_PA09N_CCL_IN4 _L_(13)
-#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
-#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9)
-#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
-#define MUX_PA10N_CCL_IN5 _L_(13)
-#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
-#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10)
-#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
-#define MUX_PA22N_CCL_IN6 _L_(13)
-#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
-#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22)
-#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
-#define MUX_PB06N_CCL_IN6 _L_(13)
-#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
-#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6)
-#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
-#define MUX_PA23N_CCL_IN7 _L_(13)
-#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
-#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23)
-#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
-#define MUX_PB07N_CCL_IN7 _L_(13)
-#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
-#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7)
-#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
-#define MUX_PA24N_CCL_IN8 _L_(13)
-#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
-#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24)
-#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
-#define MUX_PB08N_CCL_IN8 _L_(13)
-#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
-#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8)
-#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
-#define MUX_PB14N_CCL_IN9 _L_(13)
-#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
-#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14)
-#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
-#define MUX_PB15N_CCL_IN10 _L_(13)
-#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
-#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15)
-#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
-#define MUX_PB10N_CCL_IN11 _L_(13)
-#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
-#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10)
-#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
-#define MUX_PB16N_CCL_IN11 _L_(13)
-#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
-#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16)
-#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
-#define MUX_PA07N_CCL_OUT0 _L_(13)
-#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
-#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7)
-#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
-#define MUX_PA19N_CCL_OUT0 _L_(13)
-#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
-#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19)
-#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
-#define MUX_PB02N_CCL_OUT0 _L_(13)
-#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
-#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2)
-#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
-#define MUX_PB23N_CCL_OUT0 _L_(13)
-#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
-#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23)
-#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
-#define MUX_PA11N_CCL_OUT1 _L_(13)
-#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
-#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11)
-#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
-#define MUX_PA31N_CCL_OUT1 _L_(13)
-#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
-#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31)
-#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
-#define MUX_PB11N_CCL_OUT1 _L_(13)
-#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
-#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11)
-#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
-#define MUX_PA25N_CCL_OUT2 _L_(13)
-#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
-#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25)
-#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
-#define MUX_PB09N_CCL_OUT2 _L_(13)
-#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
-#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9)
-#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
-#define MUX_PB17N_CCL_OUT3 _L_(13)
-#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
-#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD0 _L_(3)
-#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
-#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13)
-#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0 _L_(3)
-#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8)
-#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0 _L_(2)
-#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12)
-#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD1 _L_(3)
-#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
-#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12)
-#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1 _L_(3)
-#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9)
-#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1 _L_(2)
-#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13)
-#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2 _L_(3)
-#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14)
-#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2 _L_(3)
-#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10)
-#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2 _L_(2)
-#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14)
-#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3 _L_(3)
-#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11)
-#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3 _L_(3)
-#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15)
-#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3 _L_(2)
-#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD0 _L_(3)
-#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
-#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23)
-#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0 _L_(3)
-#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2)
-#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD0 _L_(3)
-#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
-#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31)
-#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0 _L_(2)
-#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16)
-#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD1 _L_(3)
-#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
-#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22)
-#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1 _L_(3)
-#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3)
-#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD1 _L_(3)
-#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
-#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30)
-#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1 _L_(2)
-#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17)
-#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2 _L_(3)
-#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24)
-#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2 _L_(3)
-#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0)
-#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2 _L_(3)
-#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22)
-#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2 _L_(2)
-#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20)
-#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3 _L_(3)
-#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25)
-#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3 _L_(3)
-#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1)
-#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3 _L_(3)
-#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23)
-#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3 _L_(2)
-#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21)
-/* ========== PORT definition for TCC4 peripheral ========== */
-#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
-#define MUX_PB14F_TCC4_WO0 _L_(5)
-#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
-#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14)
-#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
-#define MUX_PB30F_TCC4_WO0 _L_(5)
-#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
-#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30)
-#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
-#define MUX_PB15F_TCC4_WO1 _L_(5)
-#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
-#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15)
-#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
-#define MUX_PB31F_TCC4_WO1 _L_(5)
-#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
-#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31)
-/* ========== PORT definition for ADC0 peripheral ========== */
-#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC0_AIN0 _L_(1)
-#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
-#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
-#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC0_AIN1 _L_(1)
-#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
-#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
-#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC0_AIN2 _L_(1)
-#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
-#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8)
-#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC0_AIN3 _L_(1)
-#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
-#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9)
-#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC0_AIN4 _L_(1)
-#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
-#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
-#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC0_AIN5 _L_(1)
-#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
-#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
-#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC0_AIN6 _L_(1)
-#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
-#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
-#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC0_AIN7 _L_(1)
-#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
-#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
-#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
-#define MUX_PA08B_ADC0_AIN8 _L_(1)
-#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
-#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
-#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
-#define MUX_PA09B_ADC0_AIN9 _L_(1)
-#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
-#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
-#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
-#define MUX_PA10B_ADC0_AIN10 _L_(1)
-#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
-#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
-#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
-#define MUX_PA11B_ADC0_AIN11 _L_(1)
-#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
-#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
-#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
-#define MUX_PB00B_ADC0_AIN12 _L_(1)
-#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
-#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0)
-#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
-#define MUX_PB01B_ADC0_AIN13 _L_(1)
-#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
-#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1)
-#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
-#define MUX_PB02B_ADC0_AIN14 _L_(1)
-#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
-#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2)
-#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
-#define MUX_PB03B_ADC0_AIN15 _L_(1)
-#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
-#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3)
-#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
-#define MUX_PA03O_ADC0_DRV0 _L_(14)
-#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
-#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3)
-#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
-#define MUX_PB08O_ADC0_DRV1 _L_(14)
-#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
-#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8)
-#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
-#define MUX_PB09O_ADC0_DRV2 _L_(14)
-#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
-#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9)
-#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
-#define MUX_PA04O_ADC0_DRV3 _L_(14)
-#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
-#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4)
-#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
-#define MUX_PA06O_ADC0_DRV4 _L_(14)
-#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
-#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6)
-#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
-#define MUX_PA07O_ADC0_DRV5 _L_(14)
-#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
-#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7)
-#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
-#define MUX_PA08O_ADC0_DRV6 _L_(14)
-#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
-#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8)
-#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
-#define MUX_PA09O_ADC0_DRV7 _L_(14)
-#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
-#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9)
-#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
-#define MUX_PA10O_ADC0_DRV8 _L_(14)
-#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
-#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10)
-#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
-#define MUX_PA11O_ADC0_DRV9 _L_(14)
-#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
-#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11)
-#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
-#define MUX_PA16O_ADC0_DRV10 _L_(14)
-#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
-#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16)
-#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
-#define MUX_PA17O_ADC0_DRV11 _L_(14)
-#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
-#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17)
-#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
-#define MUX_PA18O_ADC0_DRV12 _L_(14)
-#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
-#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18)
-#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
-#define MUX_PA19O_ADC0_DRV13 _L_(14)
-#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
-#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19)
-#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
-#define MUX_PA20O_ADC0_DRV14 _L_(14)
-#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
-#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20)
-#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
-#define MUX_PA21O_ADC0_DRV15 _L_(14)
-#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
-#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21)
-#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
-#define MUX_PA22O_ADC0_DRV16 _L_(14)
-#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
-#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22)
-#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
-#define MUX_PA23O_ADC0_DRV17 _L_(14)
-#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
-#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23)
-#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
-#define MUX_PA27O_ADC0_DRV18 _L_(14)
-#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
-#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27)
-#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
-#define MUX_PA30O_ADC0_DRV19 _L_(14)
-#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
-#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30)
-#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
-#define MUX_PB02O_ADC0_DRV20 _L_(14)
-#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
-#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2)
-#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
-#define MUX_PB03O_ADC0_DRV21 _L_(14)
-#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
-#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3)
-#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
-#define MUX_PB04O_ADC0_DRV22 _L_(14)
-#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
-#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4)
-#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
-#define MUX_PB05O_ADC0_DRV23 _L_(14)
-#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
-#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5)
-#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
-#define MUX_PB06O_ADC0_DRV24 _L_(14)
-#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
-#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6)
-#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
-#define MUX_PB07O_ADC0_DRV25 _L_(14)
-#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
-#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7)
-#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
-#define MUX_PB12O_ADC0_DRV26 _L_(14)
-#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
-#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12)
-#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
-#define MUX_PB13O_ADC0_DRV27 _L_(14)
-#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
-#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13)
-#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
-#define MUX_PB14O_ADC0_DRV28 _L_(14)
-#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
-#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14)
-#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
-#define MUX_PB15O_ADC0_DRV29 _L_(14)
-#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
-#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15)
-#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
-#define MUX_PB00O_ADC0_DRV30 _L_(14)
-#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
-#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0)
-#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
-#define MUX_PB01O_ADC0_DRV31 _L_(14)
-#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
-#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1)
-#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
-#define MUX_PA03B_ADC0_PTCXY0 _L_(1)
-#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
-#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3)
-#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
-#define MUX_PB08B_ADC0_PTCXY1 _L_(1)
-#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
-#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8)
-#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
-#define MUX_PB09B_ADC0_PTCXY2 _L_(1)
-#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
-#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9)
-#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
-#define MUX_PA04B_ADC0_PTCXY3 _L_(1)
-#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
-#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4)
-#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
-#define MUX_PA06B_ADC0_PTCXY4 _L_(1)
-#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
-#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6)
-#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
-#define MUX_PA07B_ADC0_PTCXY5 _L_(1)
-#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
-#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7)
-#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
-#define MUX_PA08B_ADC0_PTCXY6 _L_(1)
-#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
-#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8)
-#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
-#define MUX_PA09B_ADC0_PTCXY7 _L_(1)
-#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
-#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9)
-#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
-#define MUX_PA10B_ADC0_PTCXY8 _L_(1)
-#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
-#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10)
-#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
-#define MUX_PA11B_ADC0_PTCXY9 _L_(1)
-#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
-#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11)
-#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
-#define MUX_PA16B_ADC0_PTCXY10 _L_(1)
-#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
-#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16)
-#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
-#define MUX_PA17B_ADC0_PTCXY11 _L_(1)
-#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
-#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17)
-#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
-#define MUX_PA19B_ADC0_PTCXY13 _L_(1)
-#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
-#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19)
-#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
-#define MUX_PA20B_ADC0_PTCXY14 _L_(1)
-#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
-#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20)
-#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
-#define MUX_PA21B_ADC0_PTCXY15 _L_(1)
-#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
-#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21)
-#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
-#define MUX_PA22B_ADC0_PTCXY16 _L_(1)
-#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
-#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22)
-#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
-#define MUX_PA23B_ADC0_PTCXY17 _L_(1)
-#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
-#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23)
-#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
-#define MUX_PA27B_ADC0_PTCXY18 _L_(1)
-#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
-#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27)
-#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
-#define MUX_PA30B_ADC0_PTCXY19 _L_(1)
-#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
-#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30)
-#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
-#define MUX_PB02B_ADC0_PTCXY20 _L_(1)
-#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
-#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2)
-#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
-#define MUX_PB03B_ADC0_PTCXY21 _L_(1)
-#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
-#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3)
-#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
-#define MUX_PB04B_ADC0_PTCXY22 _L_(1)
-#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
-#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4)
-#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
-#define MUX_PB05B_ADC0_PTCXY23 _L_(1)
-#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
-#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5)
-#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
-#define MUX_PB06B_ADC0_PTCXY24 _L_(1)
-#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
-#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6)
-#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
-#define MUX_PB07B_ADC0_PTCXY25 _L_(1)
-#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
-#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7)
-#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
-#define MUX_PB12B_ADC0_PTCXY26 _L_(1)
-#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
-#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12)
-#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
-#define MUX_PB13B_ADC0_PTCXY27 _L_(1)
-#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
-#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13)
-#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
-#define MUX_PB14B_ADC0_PTCXY28 _L_(1)
-#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
-#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14)
-#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
-#define MUX_PB15B_ADC0_PTCXY29 _L_(1)
-#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
-#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15)
-#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
-#define MUX_PB00B_ADC0_PTCXY30 _L_(1)
-#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
-#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0)
-#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
-#define MUX_PB01B_ADC0_PTCXY31 _L_(1)
-#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
-#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1)
-/* ========== PORT definition for ADC1 peripheral ========== */
-#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
-#define MUX_PB08B_ADC1_AIN0 _L_(1)
-#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
-#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8)
-#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
-#define MUX_PB09B_ADC1_AIN1 _L_(1)
-#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
-#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9)
-#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
-#define MUX_PA08B_ADC1_AIN2 _L_(1)
-#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
-#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8)
-#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
-#define MUX_PA09B_ADC1_AIN3 _L_(1)
-#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
-#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9)
-#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
-#define MUX_PB04B_ADC1_AIN6 _L_(1)
-#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
-#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4)
-#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
-#define MUX_PB05B_ADC1_AIN7 _L_(1)
-#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
-#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5)
-#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
-#define MUX_PB06B_ADC1_AIN8 _L_(1)
-#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
-#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6)
-#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
-#define MUX_PB07B_ADC1_AIN9 _L_(1)
-#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
-#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT0 _L_(1)
-#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
-#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2)
-#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
-#define MUX_PA05B_DAC_VOUT1 _L_(1)
-#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
-#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
-#define MUX_PA09J_I2S_FS0 _L_(9)
-#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
-#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9)
-#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
-#define MUX_PA20J_I2S_FS0 _L_(9)
-#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
-#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20)
-#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
-#define MUX_PA23J_I2S_FS1 _L_(9)
-#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
-#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23)
-#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
-#define MUX_PB11J_I2S_FS1 _L_(9)
-#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
-#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11)
-#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
-#define MUX_PA08J_I2S_MCK0 _L_(9)
-#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
-#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8)
-#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
-#define MUX_PB17J_I2S_MCK0 _L_(9)
-#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
-#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17)
-#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
-#define MUX_PB13J_I2S_MCK1 _L_(9)
-#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
-#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13)
-#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
-#define MUX_PA10J_I2S_SCK0 _L_(9)
-#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
-#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10)
-#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
-#define MUX_PB16J_I2S_SCK0 _L_(9)
-#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
-#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16)
-#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
-#define MUX_PB12J_I2S_SCK1 _L_(9)
-#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
-#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12)
-#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
-#define MUX_PA22J_I2S_SDI _L_(9)
-#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
-#define PORT_PA22J_I2S_SDI (_UL_(1) << 22)
-#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
-#define MUX_PB10J_I2S_SDI _L_(9)
-#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
-#define PORT_PB10J_I2S_SDI (_UL_(1) << 10)
-#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
-#define MUX_PA11J_I2S_SDO _L_(9)
-#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
-#define PORT_PA11J_I2S_SDO (_UL_(1) << 11)
-#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
-#define MUX_PA21J_I2S_SDO _L_(9)
-#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
-#define PORT_PA21J_I2S_SDO (_UL_(1) << 21)
-/* ========== PORT definition for PCC peripheral ========== */
-#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
-#define MUX_PA14K_PCC_CLK _L_(10)
-#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
-#define PORT_PA14K_PCC_CLK (_UL_(1) << 14)
-#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
-#define MUX_PA16K_PCC_DATA0 _L_(10)
-#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
-#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16)
-#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
-#define MUX_PA17K_PCC_DATA1 _L_(10)
-#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
-#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17)
-#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
-#define MUX_PA18K_PCC_DATA2 _L_(10)
-#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
-#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18)
-#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
-#define MUX_PA19K_PCC_DATA3 _L_(10)
-#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
-#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19)
-#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
-#define MUX_PA20K_PCC_DATA4 _L_(10)
-#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
-#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20)
-#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
-#define MUX_PA21K_PCC_DATA5 _L_(10)
-#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
-#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21)
-#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
-#define MUX_PA22K_PCC_DATA6 _L_(10)
-#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
-#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22)
-#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
-#define MUX_PA23K_PCC_DATA7 _L_(10)
-#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
-#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23)
-#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
-#define MUX_PB14K_PCC_DATA8 _L_(10)
-#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
-#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14)
-#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
-#define MUX_PB15K_PCC_DATA9 _L_(10)
-#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
-#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15)
-#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
-#define MUX_PA12K_PCC_DEN1 _L_(10)
-#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
-#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12)
-#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
-#define MUX_PA13K_PCC_DEN2 _L_(10)
-#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
-#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13)
-/* ========== PORT definition for SDHC0 peripheral ========== */
-#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
-#define MUX_PA06I_SDHC0_SDCD _L_(8)
-#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
-#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6)
-#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
-#define MUX_PA12I_SDHC0_SDCD _L_(8)
-#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
-#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12)
-#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
-#define MUX_PB12I_SDHC0_SDCD _L_(8)
-#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
-#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12)
-#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
-#define MUX_PB11I_SDHC0_SDCK _L_(8)
-#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
-#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11)
-#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
-#define MUX_PA08I_SDHC0_SDCMD _L_(8)
-#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
-#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8)
-#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
-#define MUX_PA09I_SDHC0_SDDAT0 _L_(8)
-#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
-#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9)
-#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
-#define MUX_PA10I_SDHC0_SDDAT1 _L_(8)
-#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
-#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10)
-#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
-#define MUX_PA11I_SDHC0_SDDAT2 _L_(8)
-#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
-#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11)
-#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
-#define MUX_PB10I_SDHC0_SDDAT3 _L_(8)
-#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
-#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10)
-#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
-#define MUX_PA07I_SDHC0_SDWP _L_(8)
-#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
-#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7)
-#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
-#define MUX_PA13I_SDHC0_SDWP _L_(8)
-#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
-#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13)
-#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
-#define MUX_PB13I_SDHC0_SDWP _L_(8)
-#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
-#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13)
-
-#endif /* _SAMD51J18A_PIO_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h
deleted file mode 100644
index 9009b6d653b6..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
- * \file
- *
- * \brief Top level header file
- *
- * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
- *
- * \license_start
- *
- * \page License
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \license_stop
- *
- */
-
-#ifndef _SAM_
-#define _SAM_
-
-#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__)
- #include "samd51g18a.h"
-#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__)
- #include "samd51g19a.h"
-#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__)
- #include "samd51j18a.h"
-#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__)
- #include "samd51j19a.h"
-#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__)
- #include "samd51j20a.h"
-#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__)
- #include "samd51n19a.h"
-#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__)
- #include "samd51n20a.h"
-#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__)
- #include "samd51p19a.h"
-#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__)
- #include "samd51p20a.h"
-#else
- #error Library does not support the specified device
-#endif
-
-#endif /* _SAM_ */
-
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h
deleted file mode 100644
index d08ac64cb86a..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/**
- * \file
- *
- * \brief Top header file for SAMD51
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_
-#define _SAMD51_
-
-/**
- * \defgroup SAMD51_definitions SAMD51 Device Definitions
- * \brief SAMD51 CMSIS Definitions.
- */
-
-#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__)
- #include "samd51g18a.h"
-#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__)
- #include "samd51g19a.h"
-#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__)
- #include "samd51j18a.h"
-#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__)
- #include "samd51j19a.h"
-#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__)
- #include "samd51j20a.h"
-#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__)
- #include "samd51n19a.h"
-#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__)
- #include "samd51n20a.h"
-#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__)
- #include "samd51p19a.h"
-#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__)
- #include "samd51p20a.h"
-#else
- #error Library does not support the specified device.
-#endif
-
-#endif /* _SAMD51_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h
deleted file mode 100644
index 5cfccdfc8491..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h
+++ /dev/null
@@ -1,1079 +0,0 @@
-/**
- * \file
- *
- * \brief Header file for SAMD51J18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51J18A_
-#define _SAMD51J18A_
-
-/**
- * \ingroup SAMD51_definitions
- * \addtogroup SAMD51J18A_definitions SAMD51J18A definitions
- * This file defines all structures and symbols for SAMD51J18A:
- * - registers and bitfields
- * - peripheral base address
- * - peripheral ID
- * - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
-#else
-typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
-typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
- #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
-#define _L_(x) x ## L /**< C code: Long integer literal constant value */
-#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x) x /**< Assembler: Long integer literal constant value */
-#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/** CMSIS DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M4 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
- /****** SAMD51J18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD51J18A Power Manager (PM) */
- MCLK_IRQn = 1, /**< 1 SAMD51J18A Main Clock (MCLK) */
- OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
- OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
- OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
- OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
- OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
- OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J18A 32kHz Oscillators Control (OSC32KCTRL) */
- SUPC_0_IRQn = 8, /**< 8 SAMD51J18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
- SUPC_1_IRQn = 9, /**< 9 SAMD51J18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */
- WDT_IRQn = 10, /**< 10 SAMD51J18A Watchdog Timer (WDT) */
- RTC_IRQn = 11, /**< 11 SAMD51J18A Real-Time Counter (RTC) */
- EIC_0_IRQn = 12, /**< 12 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_0 */
- EIC_1_IRQn = 13, /**< 13 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_1 */
- EIC_2_IRQn = 14, /**< 14 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_2 */
- EIC_3_IRQn = 15, /**< 15 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_3 */
- EIC_4_IRQn = 16, /**< 16 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_4 */
- EIC_5_IRQn = 17, /**< 17 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_5 */
- EIC_6_IRQn = 18, /**< 18 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_6 */
- EIC_7_IRQn = 19, /**< 19 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_7 */
- EIC_8_IRQn = 20, /**< 20 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_8 */
- EIC_9_IRQn = 21, /**< 21 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_9 */
- EIC_10_IRQn = 22, /**< 22 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_10 */
- EIC_11_IRQn = 23, /**< 23 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_11 */
- EIC_12_IRQn = 24, /**< 24 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_12 */
- EIC_13_IRQn = 25, /**< 25 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_13 */
- EIC_14_IRQn = 26, /**< 26 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_14 */
- EIC_15_IRQn = 27, /**< 27 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_15 */
- FREQM_IRQn = 28, /**< 28 SAMD51J18A Frequency Meter (FREQM) */
- NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
- NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
- DMAC_0_IRQn = 31, /**< 31 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
- DMAC_1_IRQn = 32, /**< 32 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
- DMAC_2_IRQn = 33, /**< 33 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
- DMAC_3_IRQn = 34, /**< 34 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
- DMAC_4_IRQn = 35, /**< 35 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
- EVSYS_0_IRQn = 36, /**< 36 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */
- EVSYS_1_IRQn = 37, /**< 37 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */
- EVSYS_2_IRQn = 38, /**< 38 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */
- EVSYS_3_IRQn = 39, /**< 39 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */
- EVSYS_4_IRQn = 40, /**< 40 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
- PAC_IRQn = 41, /**< 41 SAMD51J18A Peripheral Access Controller (PAC) */
- TAL_0_IRQn = 42, /**< 42 SAMD51J18A Trigger Allocator (TAL): TAL_BRK */
- TAL_1_IRQn = 43, /**< 43 SAMD51J18A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */
- RAMECC_IRQn = 45, /**< 45 SAMD51J18A RAM ECC (RAMECC) */
- SERCOM0_0_IRQn = 46, /**< 46 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */
- SERCOM0_1_IRQn = 47, /**< 47 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */
- SERCOM0_2_IRQn = 48, /**< 48 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */
- SERCOM0_3_IRQn = 49, /**< 49 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
- SERCOM1_0_IRQn = 50, /**< 50 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */
- SERCOM1_1_IRQn = 51, /**< 51 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */
- SERCOM1_2_IRQn = 52, /**< 52 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */
- SERCOM1_3_IRQn = 53, /**< 53 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
- SERCOM2_0_IRQn = 54, /**< 54 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */
- SERCOM2_1_IRQn = 55, /**< 55 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */
- SERCOM2_2_IRQn = 56, /**< 56 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */
- SERCOM2_3_IRQn = 57, /**< 57 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
- SERCOM3_0_IRQn = 58, /**< 58 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */
- SERCOM3_1_IRQn = 59, /**< 59 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */
- SERCOM3_2_IRQn = 60, /**< 60 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */
- SERCOM3_3_IRQn = 61, /**< 61 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
- SERCOM4_0_IRQn = 62, /**< 62 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */
- SERCOM4_1_IRQn = 63, /**< 63 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */
- SERCOM4_2_IRQn = 64, /**< 64 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */
- SERCOM4_3_IRQn = 65, /**< 65 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
- SERCOM5_0_IRQn = 66, /**< 66 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */
- SERCOM5_1_IRQn = 67, /**< 67 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */
- SERCOM5_2_IRQn = 68, /**< 68 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */
- SERCOM5_3_IRQn = 69, /**< 69 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
- USB_0_IRQn = 80, /**< 80 SAMD51J18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
- USB_1_IRQn = 81, /**< 81 SAMD51J18A Universal Serial Bus (USB): USB_SOF_HSOF */
- USB_2_IRQn = 82, /**< 82 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
- USB_3_IRQn = 83, /**< 83 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
- TCC0_0_IRQn = 85, /**< 85 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
- TCC0_1_IRQn = 86, /**< 86 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */
- TCC0_2_IRQn = 87, /**< 87 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */
- TCC0_3_IRQn = 88, /**< 88 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */
- TCC0_4_IRQn = 89, /**< 89 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */
- TCC0_5_IRQn = 90, /**< 90 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */
- TCC0_6_IRQn = 91, /**< 91 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */
- TCC1_0_IRQn = 92, /**< 92 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
- TCC1_1_IRQn = 93, /**< 93 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */
- TCC1_2_IRQn = 94, /**< 94 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */
- TCC1_3_IRQn = 95, /**< 95 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */
- TCC1_4_IRQn = 96, /**< 96 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */
- TCC2_0_IRQn = 97, /**< 97 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
- TCC2_1_IRQn = 98, /**< 98 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */
- TCC2_2_IRQn = 99, /**< 99 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */
- TCC2_3_IRQn = 100, /**< 100 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */
- TCC3_0_IRQn = 101, /**< 101 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
- TCC3_1_IRQn = 102, /**< 102 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_0 */
- TCC3_2_IRQn = 103, /**< 103 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_1 */
- TCC4_0_IRQn = 104, /**< 104 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
- TCC4_1_IRQn = 105, /**< 105 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_0 */
- TCC4_2_IRQn = 106, /**< 106 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_1 */
- TC0_IRQn = 107, /**< 107 SAMD51J18A Basic Timer Counter 0 (TC0) */
- TC1_IRQn = 108, /**< 108 SAMD51J18A Basic Timer Counter 1 (TC1) */
- TC2_IRQn = 109, /**< 109 SAMD51J18A Basic Timer Counter 2 (TC2) */
- TC3_IRQn = 110, /**< 110 SAMD51J18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 111, /**< 111 SAMD51J18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 112, /**< 112 SAMD51J18A Basic Timer Counter 5 (TC5) */
- PDEC_0_IRQn = 115, /**< 115 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
- PDEC_1_IRQn = 116, /**< 116 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_0 */
- PDEC_2_IRQn = 117, /**< 117 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_1 */
- ADC0_0_IRQn = 118, /**< 118 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */
- ADC0_1_IRQn = 119, /**< 119 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */
- ADC1_0_IRQn = 120, /**< 120 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */
- ADC1_1_IRQn = 121, /**< 121 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */
- AC_IRQn = 122, /**< 122 SAMD51J18A Analog Comparators (AC) */
- DAC_0_IRQn = 123, /**< 123 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
- DAC_1_IRQn = 124, /**< 124 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */
- DAC_2_IRQn = 125, /**< 125 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */
- DAC_3_IRQn = 126, /**< 126 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */
- DAC_4_IRQn = 127, /**< 127 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */
- I2S_IRQn = 128, /**< 128 SAMD51J18A Inter-IC Sound Interface (I2S) */
- PCC_IRQn = 129, /**< 129 SAMD51J18A Parallel Capture Controller (PCC) */
- AES_IRQn = 130, /**< 130 SAMD51J18A Advanced Encryption Standard (AES) */
- TRNG_IRQn = 131, /**< 131 SAMD51J18A True Random Generator (TRNG) */
- ICM_IRQn = 132, /**< 132 SAMD51J18A Integrity Check Monitor (ICM) */
- PUKCC_IRQn = 133, /**< 133 SAMD51J18A PUblic-Key Cryptography Controller (PUKCC) */
- QSPI_IRQn = 134, /**< 134 SAMD51J18A Quad SPI interface (QSPI) */
- SDHC0_IRQn = 135, /**< 135 SAMD51J18A SD/MMC Host Controller 0 (SDHC0) */
-
- PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pvReservedM9;
- void* pvReservedM8;
- void* pvReservedM7;
- void* pvReservedM6;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pvReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnMCLK_Handler; /* 1 Main Clock */
- void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
- void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
- void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
- void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
- void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
- void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
- void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
- void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
- void* pfnWDT_Handler; /* 10 Watchdog Timer */
- void* pfnRTC_Handler; /* 11 Real-Time Counter */
- void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
- void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
- void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
- void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
- void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
- void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
- void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
- void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
- void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
- void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
- void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
- void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
- void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
- void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
- void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
- void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
- void* pfnFREQM_Handler; /* 28 Frequency Meter */
- void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
- void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
- void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
- void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
- void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
- void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
- void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
- void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
- void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
- void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
- void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
- void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
- void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
- void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */
- void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */
- void* pvReserved44;
- void* pfnRAMECC_Handler; /* 45 RAM ECC */
- void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
- void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
- void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
- void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
- void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
- void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
- void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
- void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
- void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
- void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
- void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
- void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
- void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
- void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
- void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
- void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
- void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
- void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
- void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
- void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
- void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
- void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
- void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
- void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
- void* pvReserved70;
- void* pvReserved71;
- void* pvReserved72;
- void* pvReserved73;
- void* pvReserved74;
- void* pvReserved75;
- void* pvReserved76;
- void* pvReserved77;
- void* pvReserved78;
- void* pvReserved79;
- void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
- void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
- void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
- void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
- void* pvReserved84;
- void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
- void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
- void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
- void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
- void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
- void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
- void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
- void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
- void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
- void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
- void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
- void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
- void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
- void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
- void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
- void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
- void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
- void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
- void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
- void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
- void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
- void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
- void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
- void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
- void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
- void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
- void* pvReserved113;
- void* pvReserved114;
- void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
- void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
- void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
- void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
- void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
- void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
- void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
- void* pfnAC_Handler; /* 122 Analog Comparators */
- void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
- void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
- void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
- void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
- void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
- void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
- void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
- void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
- void* pfnTRNG_Handler; /* 131 True Random Generator */
- void* pfnICM_Handler; /* 132 Integrity Check Monitor */
- void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
- void* pfnQSPI_Handler; /* 134 Quad SPI interface */
- void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
- void* pvReserved136;
-} DeviceVectors;
-
-/* Cortex-M4 processor handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void PM_Handler ( void );
-void MCLK_Handler ( void );
-void OSCCTRL_0_Handler ( void );
-void OSCCTRL_1_Handler ( void );
-void OSCCTRL_2_Handler ( void );
-void OSCCTRL_3_Handler ( void );
-void OSCCTRL_4_Handler ( void );
-void OSC32KCTRL_Handler ( void );
-void SUPC_0_Handler ( void );
-void SUPC_1_Handler ( void );
-void WDT_Handler ( void );
-void RTC_Handler ( void );
-void EIC_0_Handler ( void );
-void EIC_1_Handler ( void );
-void EIC_2_Handler ( void );
-void EIC_3_Handler ( void );
-void EIC_4_Handler ( void );
-void EIC_5_Handler ( void );
-void EIC_6_Handler ( void );
-void EIC_7_Handler ( void );
-void EIC_8_Handler ( void );
-void EIC_9_Handler ( void );
-void EIC_10_Handler ( void );
-void EIC_11_Handler ( void );
-void EIC_12_Handler ( void );
-void EIC_13_Handler ( void );
-void EIC_14_Handler ( void );
-void EIC_15_Handler ( void );
-void FREQM_Handler ( void );
-void NVMCTRL_0_Handler ( void );
-void NVMCTRL_1_Handler ( void );
-void DMAC_0_Handler ( void );
-void DMAC_1_Handler ( void );
-void DMAC_2_Handler ( void );
-void DMAC_3_Handler ( void );
-void DMAC_4_Handler ( void );
-void EVSYS_0_Handler ( void );
-void EVSYS_1_Handler ( void );
-void EVSYS_2_Handler ( void );
-void EVSYS_3_Handler ( void );
-void EVSYS_4_Handler ( void );
-void PAC_Handler ( void );
-void TAL_0_Handler ( void );
-void TAL_1_Handler ( void );
-void RAMECC_Handler ( void );
-void SERCOM0_0_Handler ( void );
-void SERCOM0_1_Handler ( void );
-void SERCOM0_2_Handler ( void );
-void SERCOM0_3_Handler ( void );
-void SERCOM1_0_Handler ( void );
-void SERCOM1_1_Handler ( void );
-void SERCOM1_2_Handler ( void );
-void SERCOM1_3_Handler ( void );
-void SERCOM2_0_Handler ( void );
-void SERCOM2_1_Handler ( void );
-void SERCOM2_2_Handler ( void );
-void SERCOM2_3_Handler ( void );
-void SERCOM3_0_Handler ( void );
-void SERCOM3_1_Handler ( void );
-void SERCOM3_2_Handler ( void );
-void SERCOM3_3_Handler ( void );
-void SERCOM4_0_Handler ( void );
-void SERCOM4_1_Handler ( void );
-void SERCOM4_2_Handler ( void );
-void SERCOM4_3_Handler ( void );
-void SERCOM5_0_Handler ( void );
-void SERCOM5_1_Handler ( void );
-void SERCOM5_2_Handler ( void );
-void SERCOM5_3_Handler ( void );
-void USB_0_Handler ( void );
-void USB_1_Handler ( void );
-void USB_2_Handler ( void );
-void USB_3_Handler ( void );
-void TCC0_0_Handler ( void );
-void TCC0_1_Handler ( void );
-void TCC0_2_Handler ( void );
-void TCC0_3_Handler ( void );
-void TCC0_4_Handler ( void );
-void TCC0_5_Handler ( void );
-void TCC0_6_Handler ( void );
-void TCC1_0_Handler ( void );
-void TCC1_1_Handler ( void );
-void TCC1_2_Handler ( void );
-void TCC1_3_Handler ( void );
-void TCC1_4_Handler ( void );
-void TCC2_0_Handler ( void );
-void TCC2_1_Handler ( void );
-void TCC2_2_Handler ( void );
-void TCC2_3_Handler ( void );
-void TCC3_0_Handler ( void );
-void TCC3_1_Handler ( void );
-void TCC3_2_Handler ( void );
-void TCC4_0_Handler ( void );
-void TCC4_1_Handler ( void );
-void TCC4_2_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC3_Handler ( void );
-void TC4_Handler ( void );
-void TC5_Handler ( void );
-void PDEC_0_Handler ( void );
-void PDEC_1_Handler ( void );
-void PDEC_2_Handler ( void );
-void ADC0_0_Handler ( void );
-void ADC0_1_Handler ( void );
-void ADC1_0_Handler ( void );
-void ADC1_1_Handler ( void );
-void AC_Handler ( void );
-void DAC_0_Handler ( void );
-void DAC_1_Handler ( void );
-void DAC_2_Handler ( void );
-void DAC_3_Handler ( void );
-void DAC_4_Handler ( void );
-void I2S_Handler ( void );
-void PCC_Handler ( void );
-void AES_Handler ( void );
-void TRNG_Handler ( void );
-void ICM_Handler ( void );
-void PUKCC_Handler ( void );
-void QSPI_Handler ( void );
-void SDHC0_Handler ( void );
-
-/*
- * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN 1
-#define __CM4_REV 1 /*!< Core revision r0p1 */
-#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
-#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
-#define __VTOR_PRESENT 1 /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd51.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/aes.h"
-#include "component/ccl.h"
-#include "component/cmcc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/freqm.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/icm.h"
-#include "component/i2s.h"
-#include "component/mclk.h"
-#include "component/nvmctrl.h"
-#include "component/oscctrl.h"
-#include "component/osc32kctrl.h"
-#include "component/pac.h"
-#include "component/pcc.h"
-#include "component/pdec.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/qspi.h"
-#include "component/ramecc.h"
-#include "component/rstc.h"
-#include "component/rtc.h"
-#include "component/sdhc.h"
-#include "component/sercom.h"
-#include "component/supc.h"
-#include "component/tal.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/trng.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc0.h"
-#include "instance/adc1.h"
-#include "instance/aes.h"
-#include "instance/ccl.h"
-#include "instance/cmcc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/freqm.h"
-#include "instance/gclk.h"
-#include "instance/hmatrix.h"
-#include "instance/icm.h"
-#include "instance/i2s.h"
-#include "instance/mclk.h"
-#include "instance/nvmctrl.h"
-#include "instance/oscctrl.h"
-#include "instance/osc32kctrl.h"
-#include "instance/pac.h"
-#include "instance/pcc.h"
-#include "instance/pdec.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/qspi.h"
-#include "instance/ramecc.h"
-#include "instance/rstc.h"
-#include "instance/rtc.h"
-#include "instance/sdhc0.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/supc.h"
-#include "instance/tal.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/tcc4.h"
-#include "instance/trng.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/** PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
-#define ID_PM 1 /**< \brief Power Manager (PM) */
-#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
-#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
-#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
-#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
-#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
-#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
-#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
-#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
-#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
-#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
-#define ID_PORT 36 /**< \brief Port Module (PORT) */
-#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
-#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
-#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */
-#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
-#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */
-#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
-#define ID_AC 72 /**< \brief Analog Comparators (AC) */
-#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
-#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
-#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
-#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
-#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
-#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
-
-// Peripheral instances on HPB3 bridge
-#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */
-#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
-#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
-#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
-#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */
-#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
-
-// Peripheral instances on AHB (as if on bridge 4)
-#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
-
-#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/** BASE ADDRESS DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC (0x42002000) /**< \brief (AC) APB Base Address */
-#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
-#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
-#define AES (0x42002400) /**< \brief (AES) APB Base Address */
-#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
-#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
-#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
-#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
-#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
-#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
-#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
-#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
-#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
-#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
-#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
-#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */
-#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
-#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */
-#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */
-#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */
-#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */
-#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */
-#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */
-#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */
-#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */
-#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */
-#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */
-#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
-#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */
-#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */
-#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */
-#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */
-#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */
-#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */
-#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */
-#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
-#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
-#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
-#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
-#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
-#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
-#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
-#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
-#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */
-#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
-#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
-#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
-#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
-#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
-#define PM (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
-#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
-#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
-#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
-#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
-#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
-#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
-#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
-#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
-#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
-#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
-#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */
-#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
-#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
-#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
-#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
-#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */
-#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */
-#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
-#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
-#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
-#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */
-#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */
-#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
-#define USB (0x41000000) /**< \brief (USB) APB Base Address */
-#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
-#define AC_INSTS { AC } /**< \brief (AC) Instances List */
-
-#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
-#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
-#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
-#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
-
-#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
-#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
-#define AES_INSTS { AES } /**< \brief (AES) Instances List */
-
-#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
-#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
-#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
-
-#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
-#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
-#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
-#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
-
-#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
-#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
-
-#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
-
-#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
-#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
-
-#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
-#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
-
-#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
-
-#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
-#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
-#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
-
-#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
-
-#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
-
-#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
-#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
-#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
-
-#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
-#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
-
-#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
-#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
-#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
-
-#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */
-#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */
-#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */
-#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */
-#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */
-#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */
-#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */
-#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */
-#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */
-#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */
-#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
-#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */
-#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */
-#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */
-#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */
-#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */
-#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */
-#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */
-#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
-#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
-#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
-#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
-#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
-#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
-#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
-#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
-#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */
-#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
-
-#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
-#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
-#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
-
-#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
-#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
-#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
-
-#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
-#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
-#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
-
-#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
-#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
-#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
-
-#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
-#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
-#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
-
-#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
-#define PM_INSTS { PM } /**< \brief (PM) Instances List */
-
-#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
-#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
-#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
-
-#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
-#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
-#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
-#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
-
-#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
-#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
-#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
-#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
-
-#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
-#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
-#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
-
-#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
-#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
-#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
-
-#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
-#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
-
-#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
-#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */
-#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
-
-#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
-#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
-#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
-
-#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */
-#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */
-#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */
-
-#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
-#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
-#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
-#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
-#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */
-#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */
-#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
-
-#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
-#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */
-#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
-
-#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
-#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
-#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
-
-#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
-#define USB_INSTS { USB } /**< \brief (USB) Instances List */
-
-#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
-#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/** PORT DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd51j18a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/** MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-
-#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */
-#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */
-#define FLASH_PAGE_SIZE 512
-#define FLASH_NB_OF_PAGES 512
-#define FLASH_USER_PAGE_SIZE 512
-#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
-#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
-
-#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
-#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
-#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
-#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
-#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
-#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
-#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
-#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
-#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
-#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
-#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
-#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
-#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
-#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
-#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
-#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
-#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE _UL_(0x60060006)
-#define ADC0_TOUCH_LINES_NUM 32
-#define PORT_GROUPS 2
-
-/* ************************************************************************** */
-/** ELECTRICAL DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD51J18A_H */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h
deleted file mode 100644
index cfbd2b921b44..000000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
- * \file
- *
- * \brief Low-level initialization functions called upon chip startup
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SYSTEM_SAMD51_H_INCLUDED_
-#define _SYSTEM_SAMD51_H_INCLUDED_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-void SystemInit(void);
-void SystemCoreClockUpdate(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_SAMD51_H_INCLUDED */
diff --git a/lib/python/qmk/cli/__init__.py b/lib/python/qmk/cli/__init__.py
index 0baf19a629df..2d63dfb4477b 100644
--- a/lib/python/qmk/cli/__init__.py
+++ b/lib/python/qmk/cli/__init__.py
@@ -207,8 +207,8 @@ def _eprint(errmsg):
# Ubuntu 24.04: 3.12
# void: 3.12
-if sys.version_info[0] != 3 or sys.version_info[1] < 7:
- _eprint('Error: Your Python is too old! Please upgrade to Python 3.7 or later.')
+if sys.version_info[0] != 3 or sys.version_info[1] < 9:
+ _eprint('Error: Your Python is too old! Please upgrade to Python 3.9 or later.')
exit(127)
milc_version = __VERSION__.split('.')
diff --git a/lib/python/qmk/cli/new/keyboard.py b/lib/python/qmk/cli/new/keyboard.py
index b84b130f8ec5..bd02acf9c844 100644
--- a/lib/python/qmk/cli/new/keyboard.py
+++ b/lib/python/qmk/cli/new/keyboard.py
@@ -8,7 +8,7 @@
from dotty_dict import dotty
from milc import cli
-from milc.questions import choice, question
+from milc.questions import choice, question, yesno
from qmk.git import git_get_username
from qmk.json_schema import load_jsonschema
@@ -131,60 +131,70 @@ def _question(*args, **kwargs):
return ret
-def prompt_keyboard():
- prompt = """{fg_yellow}Name Your Keyboard Project{style_reset_all}
-For more infomation, see:
-https://docs.qmk.fm/hardware_keyboard_guidelines#naming-your-keyboard-project
+def prompt_heading_subheading(heading, subheading):
+ cli.log.info(f"{{fg_yellow}}{heading}{{style_reset_all}}")
+ cli.log.info(subheading)
+
-Keyboard Name? """
+def prompt_keyboard():
+ prompt_heading_subheading("Name Your Keyboard Project", """For more information, see:
+https://docs.qmk.fm/hardware_keyboard_guidelines#naming-your-keyboard-project""")
errmsg = 'Keyboard already exists! Please choose a different name:'
- return _question(prompt, reprompt=errmsg, validate=lambda x: not keyboard(x).exists())
+ return _question("Keyboard Name?", reprompt=errmsg, validate=lambda x: not keyboard(x).exists())
def prompt_user():
- prompt = """
-{fg_yellow}Attribution{style_reset_all}
-Used for maintainer, copyright, etc
+ prompt_heading_subheading("Attribution", "Used for maintainer, copyright, etc.")
-Your GitHub Username? """
- return question(prompt, default=git_get_username())
+ return question("Your GitHub Username?", default=git_get_username())
def prompt_name(def_name):
- prompt = """
-{fg_yellow}More Attribution{style_reset_all}
-Used for maintainer, copyright, etc
+ prompt_heading_subheading("More Attribution", "Used for maintainer, copyright, etc.")
-Your Real Name? """
- return question(prompt, default=def_name)
+ return question("Your Real Name?", default=def_name)
def prompt_layout():
- prompt = """
-{fg_yellow}Pick Base Layout{style_reset_all}
-As a starting point, one of the common layouts can be used to bootstrap the process
+ prompt_heading_subheading("Pick Base Layout", """As a starting point, one of the common layouts can be used to
+bootstrap the process""")
-Default Layout? """
# avoid overwhelming user - remove some?
filtered_layouts = [x for x in available_layouts if not any(xs in x for xs in ['_split', '_blocker', '_tsangan', '_f13'])]
filtered_layouts.append("none of the above")
- return choice(prompt, filtered_layouts, default=len(filtered_layouts) - 1)
+ return choice("Default Layout?", filtered_layouts, default=len(filtered_layouts) - 1)
+
+
+def prompt_mcu_type():
+ prompt_heading_subheading(
+ "What Powers Your Project", """Is your board using a separate development board, such as a Pro Micro,
+or is the microcontroller integrated onto the PCB?
+
+For more information, see:
+https://docs.qmk.fm/compatible_microcontrollers"""
+ )
+
+ return yesno("Using a Development Board?")
+
+
+def prompt_dev_board():
+ prompt_heading_subheading("Select Development Board", """For more information, see:
+https://docs.qmk.fm/compatible_microcontrollers""")
+
+ return choice("Development Board?", dev_boards, default=dev_boards.index("promicro"))
def prompt_mcu():
- prompt = """
-{fg_yellow}What Powers Your Project{style_reset_all}
-For more infomation, see:
-https://docs.qmk.fm/#/compatible_microcontrollers
+ prompt_heading_subheading("Select Microcontroller", """For more information, see:
+https://docs.qmk.fm/compatible_microcontrollers""")
-MCU? """
# remove any options strictly used for compatibility
- filtered_mcu = [x for x in (dev_boards + mcu_types) if not any(xs in x for xs in ['cortex', 'unknown'])]
+ filtered_mcu = [x for x in mcu_types if not any(xs in x for xs in ['cortex', 'unknown'])]
- return choice(prompt, filtered_mcu, default=filtered_mcu.index("atmega32u4"))
+ return choice("Microcontroller?", filtered_mcu, default=filtered_mcu.index("atmega32u4"))
@cli.argument('-kb', '--keyboard', help='Specify the name for the new keyboard directory', arg_only=True, type=keyboard_name)
@@ -211,7 +221,11 @@ def new_keyboard(cli):
user_name = cli.config.new_keyboard.name if cli.config.new_keyboard.name else prompt_user()
real_name = cli.args.realname or cli.config.new_keyboard.name if cli.args.realname or cli.config.new_keyboard.name else prompt_name(user_name)
default_layout = cli.args.layout if cli.args.layout else prompt_layout()
- mcu = cli.args.type if cli.args.type else prompt_mcu()
+
+ if cli.args.type:
+ mcu = cli.args.type
+ else:
+ mcu = prompt_dev_board() if prompt_mcu_type() else prompt_mcu()
config = {}
if mcu in dev_boards:
diff --git a/lib/python/qmk/cli/painter/convert_graphics.py b/lib/python/qmk/cli/painter/convert_graphics.py
index 553c26aa5d55..f74d655fd578 100644
--- a/lib/python/qmk/cli/painter/convert_graphics.py
+++ b/lib/python/qmk/cli/painter/convert_graphics.py
@@ -60,9 +60,7 @@ def painter_convert_graphics(cli):
return
# Work out the text substitutions for rendering the output data
- args_str = " ".join((f"--{arg} {getattr(cli.args, arg.replace('-', '_'))}" for arg in ["input", "output", "format", "no-rle", "no-deltas"]))
- command = f"qmk painter-convert-graphics {args_str}"
- subs = generate_subs(cli, out_bytes, image_metadata=metadata, command=command)
+ subs = generate_subs(cli, out_bytes, image_metadata=metadata, command_name="painter_convert_graphics")
# Render and write the header file
header_text = render_header(subs)
diff --git a/lib/python/qmk/cli/painter/make_font.py b/lib/python/qmk/cli/painter/make_font.py
index 19db8449316f..3e18fd74a56d 100644
--- a/lib/python/qmk/cli/painter/make_font.py
+++ b/lib/python/qmk/cli/painter/make_font.py
@@ -61,10 +61,8 @@ def painter_convert_font_image(cli):
return
# Work out the text substitutions for rendering the output data
- args_str = " ".join((f"--{arg} {getattr(cli.args, arg.replace('-', '_'))}" for arg in ["input", "output", "no-ascii", "unicode-glyphs", "format", "no-rle"]))
- command = f"qmk painter-convert-font-image {args_str}"
metadata = {"glyphs": _generate_font_glyphs_list(not cli.args.no_ascii, cli.args.unicode_glyphs)}
- subs = generate_subs(cli, out_bytes, font_metadata=metadata, command=command)
+ subs = generate_subs(cli, out_bytes, font_metadata=metadata, command_name="painter_convert_font_image")
# Render and write the header file
header_text = render_header(subs)
diff --git a/lib/python/qmk/commands.py b/lib/python/qmk/commands.py
index 97d9c5032c8f..a05b3641b5ca 100644
--- a/lib/python/qmk/commands.py
+++ b/lib/python/qmk/commands.py
@@ -55,7 +55,7 @@ def parse_configurator_json(configurator_file):
cli.log.error(f'Invalid JSON keymap: {configurator_file} : {e.message}')
maybe_exit(1)
- keyboard = user_keymap['keyboard']
+ keyboard = user_keymap.get('keyboard', None)
aliases = keyboard_alias_definitions()
while keyboard in aliases:
diff --git a/lib/python/qmk/constants.py b/lib/python/qmk/constants.py
index b6f46180b298..e055d3fbc95e 100644
--- a/lib/python/qmk/constants.py
+++ b/lib/python/qmk/constants.py
@@ -22,7 +22,7 @@
MAX_KEYBOARD_SUBFOLDERS = 5
# Supported processor types
-CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK64FX512', 'MK66FX1M0', 'RP2040', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32H723', 'STM32H733', 'STM32L412', 'STM32L422', 'STM32L432', 'STM32L433', 'STM32L442', 'STM32L443', 'GD32VF103', 'WB32F3G71', 'WB32FQ95'
+CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK64FX512', 'MK66FX1M0', 'RP2040', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32H723', 'STM32H733', 'STM32L412', 'STM32L422', 'STM32L432', 'STM32L433', 'STM32L442', 'STM32L443', 'GD32VF103', 'WB32F3G71', 'WB32FQ95', 'AT32F415'
LUFA_PROCESSORS = 'at90usb162', 'atmega16u2', 'atmega32u2', 'atmega16u4', 'atmega32u4', 'at90usb646', 'at90usb647', 'at90usb1286', 'at90usb1287', None
VUSB_PROCESSORS = 'atmega32a', 'atmega328p', 'atmega328', 'attiny85'
@@ -55,6 +55,7 @@
"GD32VF103": "gd32v-dfu",
"WB32F3G71": "wb32-dfu",
"WB32FQ95": "wb32-dfu",
+ "AT32F415": "at32-dfu",
"atmega16u2": "atmel-dfu",
"atmega32u2": "atmel-dfu",
"atmega16u4": "atmel-dfu",
@@ -93,6 +94,7 @@
'apm32-dfu': {("314b", "0106")},
'gd32v-dfu': {("28e9", "0189")},
'wb32-dfu': {("342d", "dfa0")},
+ 'at32-dfu': {("2e3c", "df11")},
'bootloadhid': {("16c0", "05df")},
'usbasploader': {("16c0", "05dc")},
'usbtinyisp': {("1782", "0c9f")},
diff --git a/lib/python/qmk/info.py b/lib/python/qmk/info.py
index 82082f5cf0d8..5dae353538ad 100644
--- a/lib/python/qmk/info.py
+++ b/lib/python/qmk/info.py
@@ -901,9 +901,6 @@ def arm_processor_rules(info_data, rules):
info_data['platform'] = 'STM32'
elif 'MCU_SERIES' in rules:
info_data['platform'] = rules['MCU_SERIES']
- elif 'ARM_ATSAM' in rules:
- info_data['platform'] = 'ARM_ATSAM'
- info_data['platform_key'] = 'arm_atsam'
return info_data
diff --git a/lib/python/qmk/keymap.py b/lib/python/qmk/keymap.py
index 97c358788a5e..9dd043c4a898 100644
--- a/lib/python/qmk/keymap.py
+++ b/lib/python/qmk/keymap.py
@@ -29,38 +29,40 @@
* This file was generated by qmk json2c. You may or may not want to
* edit it directly.
*/
-const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
-__KEYMAP_GOES_HERE__
-};
-#if defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
-const uint16_t PROGMEM encoder_map[][NUM_ENCODERS][NUM_DIRECTIONS] = {
+__KEYMAP_GOES_HERE__
__ENCODER_MAP_GOES_HERE__
-};
-#endif // defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
-
__MACRO_OUTPUT_GOES_HERE__
+
+#ifdef OTHER_KEYMAP_C
+# include OTHER_KEYMAP_C
+#endif // OTHER_KEYMAP_C
"""
def _generate_keymap_table(keymap_json):
- lines = []
+ lines = ['const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {']
for layer_num, layer in enumerate(keymap_json['layers']):
if layer_num != 0:
lines[-1] = lines[-1] + ','
layer = map(_strip_any, layer)
layer_keys = ', '.join(layer)
lines.append(' [%s] = %s(%s)' % (layer_num, keymap_json['layout'], layer_keys))
+ lines.append('};')
return lines
def _generate_encodermap_table(keymap_json):
- lines = []
+ lines = [
+ '#if defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)',
+ 'const uint16_t PROGMEM encoder_map[][NUM_ENCODERS][NUM_DIRECTIONS] = {',
+ ]
for layer_num, layer in enumerate(keymap_json['encoders']):
if layer_num != 0:
lines[-1] = lines[-1] + ','
encoder_keycode_txt = ', '.join([f'ENCODER_CCW_CW({_strip_any(e["ccw"])}, {_strip_any(e["cw"])})' for e in layer])
lines.append(' [%s] = {%s}' % (layer_num, encoder_keycode_txt))
+ lines.extend(['};', '#endif // defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)'])
return lines
@@ -271,8 +273,11 @@ def generate_c(keymap_json):
A sequence of strings containing macros to implement for this keyboard.
"""
new_keymap = DEFAULT_KEYMAP_C
- layer_txt = _generate_keymap_table(keymap_json)
- keymap = '\n'.join(layer_txt)
+
+ keymap = ''
+ if 'layers' in keymap_json and keymap_json['layers'] is not None:
+ layer_txt = _generate_keymap_table(keymap_json)
+ keymap = '\n'.join(layer_txt)
new_keymap = new_keymap.replace('__KEYMAP_GOES_HERE__', keymap)
encodermap = ''
diff --git a/lib/python/qmk/painter.py b/lib/python/qmk/painter.py
index 512a486ce870..ed0372c163ee 100644
--- a/lib/python/qmk/painter.py
+++ b/lib/python/qmk/painter.py
@@ -3,6 +3,7 @@
import datetime
import math
import re
+from pathlib import Path
from string import Template
from PIL import Image, ImageOps
@@ -137,10 +138,31 @@ def _render_image_metadata(metadata):
return "\n".join(lines)
-def generate_subs(cli, out_bytes, *, font_metadata=None, image_metadata=None, command):
+def command_args_str(cli, command_name):
+ """Given a command name, introspect milc to get the arguments passed in."""
+
+ args = {}
+ max_length = 0
+ for arg_name, was_passed in cli.args_passed[command_name].items():
+ max_length = max(max_length, len(arg_name))
+
+ val = getattr(cli.args, arg_name.replace("-", "_"))
+
+ # do not leak full paths, keep just file name
+ if isinstance(val, Path):
+ val = val.name
+
+ args[arg_name] = val
+
+ return "\n".join(f"// {arg_name.ljust(max_length)} | {val}" for arg_name, val in args.items())
+
+
+def generate_subs(cli, out_bytes, *, font_metadata=None, image_metadata=None, command_name):
if font_metadata is not None and image_metadata is not None:
raise ValueError("Cant generate subs for font and image at the same time")
+ args = command_args_str(cli, command_name)
+
subs = {
"year": datetime.date.today().strftime("%Y"),
"input_file": cli.args.input.name,
@@ -148,7 +170,8 @@ def generate_subs(cli, out_bytes, *, font_metadata=None, image_metadata=None, co
"byte_count": len(out_bytes),
"bytes_lines": render_bytes(out_bytes),
"format": cli.args.format,
- "generator_command": command,
+ "generator_command": command_name.replace("_", "-"),
+ "command_args": args,
}
if font_metadata is not None:
@@ -167,7 +190,7 @@ def generate_subs(cli, out_bytes, *, font_metadata=None, image_metadata=None, co
subs.update({
"generated_type": "image",
"var_prefix": "gfx",
- "generator_command": command,
+ "generator_command": command_name,
"metadata": _render_image_metadata(image_metadata),
})
@@ -183,7 +206,8 @@ def generate_subs(cli, out_bytes, *, font_metadata=None, image_metadata=None, co
// Copyright ${year} QMK -- generated source code only, ${generated_type} retains original copyright
// SPDX-License-Identifier: GPL-2.0-or-later
-// This file was auto-generated by `${generator_command}`
+// This file was auto-generated by `${generator_command}` with arguments:
+${command_args}
"""
diff --git a/lib/python/qmk/search.py b/lib/python/qmk/search.py
index 6517bb4951d6..c7bce344ad19 100644
--- a/lib/python/qmk/search.py
+++ b/lib/python/qmk/search.py
@@ -239,11 +239,11 @@ def _filter_keymap_targets(target_list: List[KeyboardKeymapDesc], filters: List[
valid_targets = parallel_map(_load_keymap_info, target_list)
function_re = re.compile(r'^(?P[a-zA-Z]+)\((?P[a-zA-Z0-9_\.]+)(,\s*(?P[^#]+))?\)$')
- equals_re = re.compile(r'^(?P[a-zA-Z0-9_\.]+)\s*=\s*(?P[^#]+)$')
+ comparison_re = re.compile(r'^(?P[a-zA-Z0-9_\.]+)\s*(?P[\<\>\!=]=|\<|\>)\s*(?P[^#]+)$')
for filter_expr in filters:
function_match = function_re.match(filter_expr)
- equals_match = equals_re.match(filter_expr)
+ comparison_match = comparison_re.match(filter_expr)
if function_match is not None:
func_name = function_match.group('function').lower()
@@ -259,23 +259,43 @@ def _filter_keymap_targets(target_list: List[KeyboardKeymapDesc], filters: List[
value_str = f", {{fg_cyan}}{value}{{fg_reset}}" if value is not None else ""
cli.log.info(f'Filtering on condition: {{fg_green}}{func_name}{{fg_reset}}({{fg_cyan}}{key}{{fg_reset}}{value_str})...')
- elif equals_match is not None:
- key = equals_match.group('key')
- value = equals_match.group('value')
- cli.log.info(f'Filtering on condition: {{fg_cyan}}{key}{{fg_reset}} == {{fg_cyan}}{value}{{fg_reset}}...')
+ elif comparison_match is not None:
+ key = comparison_match.group('key')
+ op = comparison_match.group('op')
+ value = comparison_match.group('value')
+ cli.log.info(f'Filtering on condition: {{fg_cyan}}{key}{{fg_reset}} {op} {{fg_cyan}}{value}{{fg_reset}}...')
- def _make_filter(k, v):
+ def _make_filter(k, o, v):
expr = fnmatch.translate(v)
rule = re.compile(f'^{expr}$', re.IGNORECASE)
def f(e: KeyboardKeymapDesc):
lhs = e.dotty.get(k)
- lhs = str(False if lhs is None else lhs)
- return rule.search(lhs) is not None
+ rhs = v
+
+ if o in ['<', '>', '<=', '>=']:
+ lhs = int(False if lhs is None else lhs)
+ rhs = int(rhs)
+
+ if o == '<':
+ return lhs < rhs
+ elif o == '>':
+ return lhs > rhs
+ elif o == '<=':
+ return lhs <= rhs
+ elif o == '>=':
+ return lhs >= rhs
+ else:
+ lhs = str(False if lhs is None else lhs)
+
+ if o == '!=':
+ return rule.search(lhs) is None
+ elif o == '==':
+ return rule.search(lhs) is not None
return f
- valid_targets = filter(_make_filter(key, value), valid_targets)
+ valid_targets = filter(_make_filter(key, op, value), valid_targets)
else:
cli.log.warning(f'Unrecognized filter expression: {filter_expr}')
continue
diff --git a/lib/python/qmk/tests/test_cli_commands.py b/lib/python/qmk/tests/test_cli_commands.py
index f18bd12f8201..dd659fe0f27e 100644
--- a/lib/python/qmk/tests/test_cli_commands.py
+++ b/lib/python/qmk/tests/test_cli_commands.py
@@ -152,17 +152,16 @@ def test_json2c():
* This file was generated by qmk json2c. You may or may not want to
* edit it directly.
*/
+
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[0] = LAYOUT_ortho_1x1(KC_A)
};
-#if defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
-const uint16_t PROGMEM encoder_map[][NUM_ENCODERS][NUM_DIRECTIONS] = {
-
-};
-#endif // defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
+#ifdef OTHER_KEYMAP_C
+# include OTHER_KEYMAP_C
+#endif // OTHER_KEYMAP_C
"""
@@ -190,28 +189,21 @@ def test_json2c_stdin():
* This file was generated by qmk json2c. You may or may not want to
* edit it directly.
*/
+
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[0] = LAYOUT_ortho_1x1(KC_A)
};
-#if defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
-const uint16_t PROGMEM encoder_map[][NUM_ENCODERS][NUM_DIRECTIONS] = {
-
-};
-#endif // defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
+#ifdef OTHER_KEYMAP_C
+# include OTHER_KEYMAP_C
+#endif // OTHER_KEYMAP_C
"""
-def test_json2c_wrong_json():
- result = check_subcommand('json2c', 'keyboards/handwired/pytest/info.json')
- check_returncode(result, [1])
- assert 'Invalid JSON keymap' in result.stdout
-
-
def test_json2c_no_json():
result = check_subcommand('json2c', 'keyboards/handwired/pytest/basic/keymaps/default/keymap.c')
check_returncode(result, [1])
@@ -390,7 +382,7 @@ def test_find_contains():
def test_find_multiple_conditions():
# this is intended to match at least 'crkbd/rev1'
result = check_subcommand(
- 'find', '-f', 'exists(rgb_matrix.split_count)', '-f', 'contains(matrix_pins.cols, B1)', '-f', 'length(matrix_pins.cols, 6)', '-f', 'absent(eeprom.driver)', '-f', 'ws2812.pin=D3', '-p', 'rgb_matrix.split_count', '-p', 'matrix_pins.cols', '-p',
+ 'find', '-f', 'exists(rgb_matrix.split_count)', '-f', 'contains(matrix_pins.cols, B1)', '-f', 'length(matrix_pins.cols, 6)', '-f', 'absent(eeprom.driver)', '-f', 'ws2812.pin == D3', '-p', 'rgb_matrix.split_count', '-p', 'matrix_pins.cols', '-p',
'eeprom.driver', '-p', 'ws2812.pin'
)
check_returncode(result)
diff --git a/lib/python/qmk/tests/test_qmk_keymap.py b/lib/python/qmk/tests/test_qmk_keymap.py
index 7482848eff10..80cc679b007c 100644
--- a/lib/python/qmk/tests/test_qmk_keymap.py
+++ b/lib/python/qmk/tests/test_qmk_keymap.py
@@ -20,17 +20,16 @@ def test_generate_c_pytest_basic():
* This file was generated by qmk json2c. You may or may not want to
* edit it directly.
*/
+
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[0] = LAYOUT(KC_A)
};
-#if defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
-const uint16_t PROGMEM encoder_map[][NUM_ENCODERS][NUM_DIRECTIONS] = {
-
-};
-#endif // defined(ENCODER_ENABLE) && defined(ENCODER_MAP_ENABLE)
+#ifdef OTHER_KEYMAP_C
+# include OTHER_KEYMAP_C
+#endif // OTHER_KEYMAP_C
"""
diff --git a/platforms/arm_atsam/_pin_defs.h b/platforms/arm_atsam/_pin_defs.h
deleted file mode 100644
index 5b50b2391003..000000000000
--- a/platforms/arm_atsam/_pin_defs.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#pragma once
-
-#include "samd51j18a.h"
-
-#define A00 PIN_PA00
-#define A01 PIN_PA01
-#define A02 PIN_PA02
-#define A03 PIN_PA03
-#define A04 PIN_PA04
-#define A05 PIN_PA05
-#define A06 PIN_PA06
-#define A07 PIN_PA07
-#define A08 PIN_PA08
-#define A09 PIN_PA09
-#define A10 PIN_PA10
-#define A11 PIN_PA11
-#define A12 PIN_PA12
-#define A13 PIN_PA13
-#define A14 PIN_PA14
-#define A15 PIN_PA15
-#define A16 PIN_PA16
-#define A17 PIN_PA17
-#define A18 PIN_PA18
-#define A19 PIN_PA19
-#define A20 PIN_PA20
-#define A21 PIN_PA21
-#define A22 PIN_PA22
-#define A23 PIN_PA23
-#define A24 PIN_PA24
-#define A25 PIN_PA25
-#define A26 PIN_PA26
-#define A27 PIN_PA27
-#define A28 PIN_PA28
-#define A29 PIN_PA29
-#define A30 PIN_PA30
-#define A31 PIN_PA31
-
-#define B00 PIN_PB00
-#define B01 PIN_PB01
-#define B02 PIN_PB02
-#define B03 PIN_PB03
-#define B04 PIN_PB04
-#define B05 PIN_PB05
-#define B06 PIN_PB06
-#define B07 PIN_PB07
-#define B08 PIN_PB08
-#define B09 PIN_PB09
-#define B10 PIN_PB10
-#define B11 PIN_PB11
-#define B12 PIN_PB12
-#define B13 PIN_PB13
-#define B14 PIN_PB14
-#define B15 PIN_PB15
-#define B16 PIN_PB16
-#define B17 PIN_PB17
-#define B18 PIN_PB18
-#define B19 PIN_PB19
-#define B20 PIN_PB20
-#define B21 PIN_PB21
-#define B22 PIN_PB22
-#define B23 PIN_PB23
-#define B24 PIN_PB24
-#define B25 PIN_PB25
-#define B26 PIN_PB26
-#define B27 PIN_PB27
-#define B28 PIN_PB28
-#define B29 PIN_PB29
-#define B30 PIN_PB30
-#define B31 PIN_PB31
diff --git a/platforms/arm_atsam/_timer.h b/platforms/arm_atsam/_timer.h
deleted file mode 100644
index 77402b612a87..000000000000
--- a/platforms/arm_atsam/_timer.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 Simon Arlott
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#pragma once
-
-// The platform is 32-bit, so prefer 32-bit timers to avoid overflow
-#define FAST_TIMER_T_SIZE 32
diff --git a/platforms/arm_atsam/_util.h b/platforms/arm_atsam/_util.h
deleted file mode 100644
index 38aa9f447288..000000000000
--- a/platforms/arm_atsam/_util.h
+++ /dev/null
@@ -1,9 +0,0 @@
-// Copyright 2023 Nick Brassel (@tzarc)
-// SPDX-License-Identifier: GPL-2.0-or-later
-#pragma once
-
-#define RESIDENT_IN_RAM(funcname) __attribute__((section(".ramfunc." #funcname), noinline)) funcname
-
-#if __has_include_next("_util.h")
-# include_next "_util.h"
-#endif
diff --git a/platforms/arm_atsam/_wait.h b/platforms/arm_atsam/_wait.h
deleted file mode 100644
index 41b686b56c84..000000000000
--- a/platforms/arm_atsam/_wait.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#pragma once
-
-#include "clks.h"
-
-#define wait_ms(ms) CLK_delay_ms(ms)
-#define wait_us(us) CLK_delay_us(us)
-#define waitInputPinDelay()
diff --git a/platforms/arm_atsam/atomic_util.h b/platforms/arm_atsam/atomic_util.h
deleted file mode 100644
index 848542d23a04..000000000000
--- a/platforms/arm_atsam/atomic_util.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#pragma once
-
-#include "samd51j18a.h"
-
-static __inline__ uint8_t __interrupt_disable__(void) {
- __disable_irq();
-
- return 1;
-}
-
-static __inline__ void __interrupt_enable__(const uint8_t *__s) {
- __enable_irq();
-
- __asm__ volatile("" ::: "memory");
- (void)__s;
-}
-
-#define ATOMIC_BLOCK(type) for (type, __ToDo = __interrupt_disable__(); __ToDo; __ToDo = 0)
-#define ATOMIC_FORCEON uint8_t sreg_save __attribute__((__cleanup__(__interrupt_enable__))) = 0
-
-#define ATOMIC_BLOCK_RESTORESTATE _Static_assert(0, "ATOMIC_BLOCK_RESTORESTATE not implemented")
-#define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK(ATOMIC_FORCEON)
diff --git a/platforms/arm_atsam/bootloader.mk b/platforms/arm_atsam/bootloader.mk
deleted file mode 100644
index 7e503bdca9d7..000000000000
--- a/platforms/arm_atsam/bootloader.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright 2017 Jack Humbert
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see .
-
-# If it's possible that multiple bootloaders can be used for one project,
-# you can leave this unset, and the correct size will be selected
-# automatically.
-#
-# Sets the bootloader defined in the keyboard's/keymap's rules.mk
-#
-# Current options for ARM (ATSAM):
-# md-boot Atmel SAM-BA (only used by Drop boards)
-#
-# If you need to provide your own implementation, you can set inside `rules.mk`
-# `BOOTLOADER = custom` -- you'll need to provide your own implementations. See
-# the respective file under `platforms//bootloaders/custom.c` to see
-# which functions may be overridden.
-
-FIRMWARE_FORMAT?=bin
-
-ifeq ($(strip $(BOOTLOADER)), custom)
- OPT_DEFS += -DBOOTLOADER_CUSTOM
- BOOTLOADER_TYPE = custom
-endif
-
-ifeq ($(strip $(BOOTLOADER)), md-boot)
- OPT_DEFS += -DBOOTLOADER_MD_BOOT
- BOOTLOADER_TYPE = md_boot
-endif
-
-ifeq ($(strip $(BOOTLOADER_TYPE)),)
- ifneq ($(strip $(BOOTLOADER)),)
- $(call CATASTROPHIC_ERROR,Invalid BOOTLOADER,Invalid bootloader specified. Please set an appropriate bootloader in your rules.mk or info.json.)
- else
- $(call CATASTROPHIC_ERROR,Invalid BOOTLOADER,No bootloader specified. Please set an appropriate bootloader in your rules.mk or info.json.)
- endif
-endif
diff --git a/platforms/arm_atsam/bootloaders/md_boot.c b/platforms/arm_atsam/bootloaders/md_boot.c
deleted file mode 100644
index 1cf7aec62ccf..000000000000
--- a/platforms/arm_atsam/bootloaders/md_boot.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2017 Fred Sundvik
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-
-#include "bootloader.h"
-
-#include "samd51j18a.h"
-
-// WARNING: These are only for CTRL bootloader release "v2.18Jun 22 2018 17:28:08" for bootloader_jump support
-extern uint32_t _eram;
-#define BOOTLOADER_MAGIC 0x3B9ACA00
-#define MAGIC_ADDR (uint32_t *)((intptr_t)(&_eram) - 4)
-
-// CTRL keyboards released with bootloader version below must use RAM method. Otherwise use WDT method.
-void bootloader_jump(void) {
-#ifdef KEYBOARD_massdrop_ctrl
- uint8_t ver_ram_method[] = "v2.18Jun 22 2018 17:28:08"; // The version to match (NULL terminated by compiler)
- uint8_t *ver_check = ver_ram_method; // Pointer to version match string for traversal
- uint8_t *ver_rom = (uint8_t *)0x21A0; // Pointer to address in ROM where this specific bootloader version would exist
-
- while (*ver_check && *ver_rom == *ver_check) { // While there are check version characters to match and bootloader's version matches check's version
- ver_check++; // Move check version pointer to next character
- ver_rom++; // Move ROM version pointer to next character
- }
-
- if (!*ver_check) { // If check version pointer is NULL, all characters have matched
- *MAGIC_ADDR = BOOTLOADER_MAGIC; // Set magic number into RAM
- NVIC_SystemReset(); // Perform system reset
- while (1)
- ; // Won't get here
- }
-#endif
-
- // Set watchdog timer to reset. Directs the bootloader to stay in programming mode.
- WDT->CTRLA.bit.ENABLE = 0;
-
- while (WDT->SYNCBUSY.bit.ENABLE)
- ;
- while (WDT->CTRLA.bit.ENABLE)
- ;
-
- WDT->CONFIG.bit.WINDOW = 0;
- WDT->CONFIG.bit.PER = 0;
- WDT->EWCTRL.bit.EWOFFSET = 0;
- WDT->CTRLA.bit.ENABLE = 1;
-
- while (WDT->SYNCBUSY.bit.ENABLE)
- ;
- while (!WDT->CTRLA.bit.ENABLE)
- ;
- while (1)
- ; // Wait on timeout
-}
-
-__attribute__((weak)) void mcu_reset(void) {
- NVIC_SystemReset();
-}
diff --git a/platforms/arm_atsam/eeprom_samd.c b/platforms/arm_atsam/eeprom_samd.c
deleted file mode 100644
index 9c42041f2da4..000000000000
--- a/platforms/arm_atsam/eeprom_samd.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2017 Fred Sundvik
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#include "eeprom.h"
-#include "debug.h"
-#include "util.h"
-#include "samd51j18a.h"
-#include "core_cm4.h"
-#include "component/nvmctrl.h"
-#include "eeprom_samd.h"
-
-#ifndef BUSY_RETRIES
-# define BUSY_RETRIES 10000
-#endif
-
-// #define DEBUG_EEPROM_OUTPUT
-
-/*
- * Debug print utils
- */
-#if defined(DEBUG_EEPROM_OUTPUT)
-# define eeprom_printf(fmt, ...) xprintf(fmt, ##__VA_ARGS__);
-#else /* NO_DEBUG */
-# define eeprom_printf(fmt, ...)
-#endif /* NO_DEBUG */
-
-__attribute__((aligned(4))) static uint8_t buffer[EEPROM_SIZE] = {0};
-volatile uint8_t * SmartEEPROM8 = (uint8_t *)SEEPROM_ADDR;
-
-static inline bool eeprom_is_busy(void) {
- int timeout = BUSY_RETRIES;
- while (NVMCTRL->SEESTAT.bit.BUSY && timeout-- > 0)
- ;
-
- return NVMCTRL->SEESTAT.bit.BUSY;
-}
-
-static uint32_t get_virtual_eeprom_size(void) {
- // clang-format off
- static const uint32_t VIRTUAL_EEPROM_MAP[11][8] = {
- /* 4 8 16 32 64 128 256 512 */
- /* 0*/ { 0, 0, 0, 0, 0, 0, 0, 0 },
- /* 1*/ { 512, 1024, 2048, 4096, 4096, 4096, 4096, 4096 },
- /* 2*/ { 512, 1024, 2048, 4096, 8192, 8192, 8192, 8192 },
- /* 3*/ { 512, 1024, 2048, 4096, 8192, 16384, 16384, 16384 },
- /* 4*/ { 512, 1024, 2048, 4096, 8192, 16384, 16384, 16384 },
- /* 5*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
- /* 6*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
- /* 7*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
- /* 8*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
- /* 9*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 },
- /*10*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 },
- };
- // clang-format on
-
- static uint32_t virtual_eeprom_size = UINT32_MAX;
- if (virtual_eeprom_size == UINT32_MAX) {
- virtual_eeprom_size = VIRTUAL_EEPROM_MAP[NVMCTRL->SEESTAT.bit.PSZ][NVMCTRL->SEESTAT.bit.SBLK];
- }
- // eeprom_printf("get_virtual_eeprom_size:: %d:%d:%d\n", NVMCTRL->SEESTAT.bit.PSZ, NVMCTRL->SEESTAT.bit.SBLK, virtual_eeprom_size);
- return virtual_eeprom_size;
-}
-
-uint8_t eeprom_read_byte(const uint8_t *addr) {
- uintptr_t offset = (uintptr_t)addr;
- if (offset >= MAX(EEPROM_SIZE, get_virtual_eeprom_size())) {
- eeprom_printf("eeprom_read_byte:: out of bounds\n");
- return 0x0;
- }
-
- if (get_virtual_eeprom_size() == 0) {
- return buffer[offset];
- }
-
- if (eeprom_is_busy()) {
- eeprom_printf("eeprom_write_byte:: timeout\n");
- return 0x0;
- }
-
- return SmartEEPROM8[offset];
-}
-
-void eeprom_write_byte(uint8_t *addr, uint8_t value) {
- uintptr_t offset = (uintptr_t)addr;
- if (offset >= MAX(EEPROM_SIZE, get_virtual_eeprom_size())) {
- eeprom_printf("eeprom_write_byte:: out of bounds\n");
- return;
- }
-
- if (get_virtual_eeprom_size() == 0) {
- buffer[offset] = value;
- return;
- }
-
- if (eeprom_is_busy()) {
- eeprom_printf("eeprom_write_byte:: timeout\n");
- return;
- }
-
- SmartEEPROM8[offset] = value;
-}
-
-uint16_t eeprom_read_word(const uint16_t *addr) {
- const uint8_t *p = (const uint8_t *)addr;
- return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8);
-}
-
-uint32_t eeprom_read_dword(const uint32_t *addr) {
- const uint8_t *p = (const uint8_t *)addr;
- return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
-}
-
-void eeprom_read_block(void *buf, const void *addr, size_t len) {
- const uint8_t *p = (const uint8_t *)addr;
- uint8_t * dest = (uint8_t *)buf;
- while (len--) {
- *dest++ = eeprom_read_byte(p++);
- }
-}
-
-void eeprom_write_word(uint16_t *addr, uint16_t value) {
- uint8_t *p = (uint8_t *)addr;
- eeprom_write_byte(p++, value);
- eeprom_write_byte(p, value >> 8);
-}
-
-void eeprom_write_dword(uint32_t *addr, uint32_t value) {
- uint8_t *p = (uint8_t *)addr;
- eeprom_write_byte(p++, value);
- eeprom_write_byte(p++, value >> 8);
- eeprom_write_byte(p++, value >> 16);
- eeprom_write_byte(p, value >> 24);
-}
-
-void eeprom_write_block(const void *buf, void *addr, size_t len) {
- uint8_t * p = (uint8_t *)addr;
- const uint8_t *src = (const uint8_t *)buf;
- while (len--) {
- eeprom_write_byte(p++, *src++);
- }
-}
-
-void eeprom_update_byte(uint8_t *addr, uint8_t value) {
- eeprom_write_byte(addr, value);
-}
-
-void eeprom_update_word(uint16_t *addr, uint16_t value) {
- uint8_t *p = (uint8_t *)addr;
- eeprom_write_byte(p++, value);
- eeprom_write_byte(p, value >> 8);
-}
-
-void eeprom_update_dword(uint32_t *addr, uint32_t value) {
- uint8_t *p = (uint8_t *)addr;
- eeprom_write_byte(p++, value);
- eeprom_write_byte(p++, value >> 8);
- eeprom_write_byte(p++, value >> 16);
- eeprom_write_byte(p, value >> 24);
-}
-
-void eeprom_update_block(const void *buf, void *addr, size_t len) {
- uint8_t * p = (uint8_t *)addr;
- const uint8_t *src = (const uint8_t *)buf;
- while (len--) {
- eeprom_write_byte(p++, *src++);
- }
-}
diff --git a/platforms/arm_atsam/eeprom_samd.h b/platforms/arm_atsam/eeprom_samd.h
deleted file mode 100644
index 878e72865cf4..000000000000
--- a/platforms/arm_atsam/eeprom_samd.h
+++ /dev/null
@@ -1,8 +0,0 @@
-// Copyright 2022 Nick Brassel (@tzarc)
-// SPDX-License-Identifier: GPL-2.0-or-later
-#pragma once
-
-#ifndef EEPROM_SIZE
-# include "eeconfig.h"
-# define EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO
-#endif
diff --git a/platforms/arm_atsam/flash.mk b/platforms/arm_atsam/flash.mk
deleted file mode 100644
index 8068c08d579d..000000000000
--- a/platforms/arm_atsam/flash.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-# Hey Emacs, this is a -*- makefile -*-
-##############################################################################
-# Architecture or project specific options
-#
-
-MDLOADER_CLI ?= mdloader
-
-define EXEC_MDLOADER
- $(MDLOADER_CLI) --first --download $(BUILD_DIR)/$(TARGET).bin --restart
-endef
-
-mdloader: bin
- $(call EXEC_MDLOADER)
-
-flash: bin
- $(SILENT) || printf "Flashing for bootloader: $(BLUE)$(BOOTLOADER)$(NO_COLOR)\n"
-ifneq ($(strip $(PROGRAM_CMD)),)
- $(UNSYNC_OUTPUT_CMD) && $(PROGRAM_CMD)
-else ifeq ($(strip $(ARM_ATSAM)),SAMD51J18A)
- $(UNSYNC_OUTPUT_CMD) && $(call EXEC_MDLOADER)
-else
- $(PRINT_OK); $(SILENT) || printf "$(MSG_FLASH_ARCH)"
-endif
diff --git a/platforms/arm_atsam/gpio.h b/platforms/arm_atsam/gpio.h
deleted file mode 100644
index fd8caeab0bcb..000000000000
--- a/platforms/arm_atsam/gpio.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#pragma once
-
-#include
-#include "samd51j18a.h"
-
-#include "pin_defs.h"
-
-typedef uint8_t pin_t;
-
-#define SAMD_PORT(pin) (((pin)&0x20) >> 5)
-#define SAMD_PIN(pin) ((pin)&0x1f)
-#define SAMD_PIN_MASK(pin) (1 << ((pin)&0x1f))
-
-#define gpio_set_pin_input(pin) \
- do { \
- PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
- PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
- } while (0)
-
-#define gpio_set_pin_input_high(pin) \
- do { \
- PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
- PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
- PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
- PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.PULLEN = 1; \
- } while (0)
-
-#define gpio_set_pin_input_low(pin) \
- do { \
- PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
- PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
- PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
- PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.PULLEN = 1; \
- } while (0)
-
-#define gpio_set_pin_output_push_pull(pin) \
- do { \
- PORT->Group[SAMD_PORT(pin)].DIRSET.reg = SAMD_PIN_MASK(pin); \
- PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
- } while (0)
-
-#define gpio_set_pin_output_open_drain(pin) _Static_assert(0, "Open-drain outputs are not available on ATSAM")
-
-#define gpio_set_pin_output(pin) gpio_set_pin_output_push_pull(pin)
-
-#define gpio_write_pin_high(pin) \
- do { \
- PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
- } while (0)
-
-#define gpio_write_pin_low(pin) \
- do { \
- PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
- } while (0)
-
-#define gpio_write_pin(pin, level) \
- do { \
- if (level) \
- PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
- else \
- PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
- } while (0)
-
-#define gpio_read_pin(pin) ((PORT->Group[SAMD_PORT(pin)].IN.reg & SAMD_PIN_MASK(pin)) != 0)
-
-#define gpio_toggle_pin(pin) (PORT->Group[SAMD_PORT(pin)].OUTTGL.reg = SAMD_PIN_MASK(pin))
diff --git a/platforms/arm_atsam/hardware_id.c b/platforms/arm_atsam/hardware_id.c
deleted file mode 100644
index fc193e46d8ab..000000000000
--- a/platforms/arm_atsam/hardware_id.c
+++ /dev/null
@@ -1,9 +0,0 @@
-// Copyright 2022 QMK
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "hardware_id.h"
-
-__attribute__((weak)) hardware_id_t get_hardware_id(void) {
- hardware_id_t id = {0};
- return id;
-}
diff --git a/platforms/arm_atsam/platform.c b/platforms/arm_atsam/platform.c
deleted file mode 100644
index 3e35b4fe4c74..000000000000
--- a/platforms/arm_atsam/platform.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-
-#include "platform_deps.h"
-
-void platform_setup(void) {
- // do nothing
-}
diff --git a/platforms/arm_atsam/platform.mk b/platforms/arm_atsam/platform.mk
deleted file mode 100644
index 9462f517ae72..000000000000
--- a/platforms/arm_atsam/platform.mk
+++ /dev/null
@@ -1,68 +0,0 @@
-# Hey Emacs, this is a -*- makefile -*-
-##############################################################################
-# Compiler settings
-#
-CC = $(CC_PREFIX) arm-none-eabi-gcc
-OBJCOPY = arm-none-eabi-objcopy
-OBJDUMP = arm-none-eabi-objdump
-SIZE = arm-none-eabi-size
-AR = arm-none-eabi-ar
-NM = arm-none-eabi-nm
-HEX = $(OBJCOPY) -O $(FORMAT) -R .eeprom -R .fuse -R .lock -R .signature
-EEP = $(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT)
-BIN =
-
-COMMON_VPATH += $(LIB_PATH)/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include
-COMMON_VPATH += $(LIB_PATH)/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include
-
-COMPILEFLAGS += -funsigned-char
-COMPILEFLAGS += -funsigned-bitfields
-COMPILEFLAGS += -ffunction-sections
-COMPILEFLAGS += -fshort-enums
-COMPILEFLAGS += -fno-inline-small-functions
-COMPILEFLAGS += -fno-strict-aliasing
-COMPILEFLAGS += -mfloat-abi=hard
-COMPILEFLAGS += -mfpu=fpv4-sp-d16
-COMPILEFLAGS += -mthumb
-COMPILEFLAGS += -fno-builtin-printf
-
-#ALLOW_WARNINGS = yes
-
-CFLAGS += $(COMPILEFLAGS)
-
-CXXFLAGS += $(COMPILEFLAGS)
-CXXFLAGS += -fno-exceptions $(CXXSTANDARD)
-
-LDFLAGS +=-Wl,--gc-sections
-LDFLAGS += -Wl,-Map="%OUT%%PROJ_NAME%.map"
-LDFLAGS += -Wl,--start-group
-LDFLAGS += -Wl,--end-group
-LDFLAGS += --specs=rdimon.specs
-LDFLAGS += -T$(LIB_PATH)/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld
-
-OPT_DEFS += -DPROTOCOL_ARM_ATSAM
-
-MCUFLAGS = -mcpu=$(MCU)
-MCUFLAGS += -D__$(ARM_ATSAM)__
-
-# List any extra directories to look for libraries here.
-# Each directory must be seperated by a space.
-# Use forward slashes for directory separators.
-# For a directory that has spaces, enclose it in quotes.
-EXTRALIBDIRS =
-
-cpfirmware: warn-arm_atsam
-.INTERMEDIATE: warn-arm_atsam
-warn-arm_atsam: $(FIRMWARE_FORMAT)
- $(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
- $(info This MCU support package has a lack of support from the upstream provider (Massdrop).)
- $(info There are currently questions about valid licensing, and at this stage it's likely)
- $(info their boards and supporting code will be removed from QMK in the near future. Please)
- $(info contact Massdrop for support, and encourage them to align their future board design)
- $(info choices to gain proper license compatibility with QMK.)
- $(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
-
-# Convert hex to bin.
-bin: $(BUILD_DIR)/$(TARGET).hex
- $(OBJCOPY) -Iihex -Obinary $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
- $(COPY) $(BUILD_DIR)/$(TARGET).bin $(TARGET).bin;
diff --git a/platforms/arm_atsam/platform_deps.h b/platforms/arm_atsam/platform_deps.h
deleted file mode 100644
index f296d1d535e7..000000000000
--- a/platforms/arm_atsam/platform_deps.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#pragma once
-
-// here just to please the build
diff --git a/platforms/arm_atsam/suspend.c b/platforms/arm_atsam/suspend.c
deleted file mode 100644
index 242e9c91a2fa..000000000000
--- a/platforms/arm_atsam/suspend.c
+++ /dev/null
@@ -1,34 +0,0 @@
-#include "matrix.h"
-#include "i2c_master.h"
-#include "md_rgb_matrix.h"
-#include "suspend.h"
-
-/** \brief Suspend power down
- *
- * FIXME: needs doc
- */
-void suspend_power_down(void) {
-#ifdef RGB_MATRIX_ENABLE
- I2C3733_Control_Set(0); // Disable LED driver
-#endif
-
- suspend_power_down_kb();
-}
-
-/** \brief run immediately after wakeup
- *
- * FIXME: needs doc
- */
-void suspend_wakeup_init(void) {
-#ifdef RGB_MATRIX_ENABLE
-# ifdef USE_MASSDROP_CONFIGURATOR
- if (led_enabled) {
- I2C3733_Control_Set(1);
- }
-# else
- I2C3733_Control_Set(1);
-# endif
-#endif
-
- suspend_wakeup_init_kb();
-}
diff --git a/platforms/arm_atsam/timer.c b/platforms/arm_atsam/timer.c
deleted file mode 100644
index cf01e3625e4a..000000000000
--- a/platforms/arm_atsam/timer.c
+++ /dev/null
@@ -1,35 +0,0 @@
-#include "samd51j18a.h"
-#include "timer.h"
-#include "tmk_core/protocol/arm_atsam/clks.h"
-
-void set_time(uint64_t tset) {
- ms_clk = tset;
-}
-
-void timer_init(void) {
- timer_clear();
-}
-
-uint16_t timer_read(void) {
- return (uint16_t)ms_clk;
-}
-
-uint32_t timer_read32(void) {
- return (uint32_t)ms_clk;
-}
-
-uint64_t timer_read64(void) {
- return ms_clk;
-}
-
-uint16_t timer_elapsed(uint16_t tlast) {
- return TIMER_DIFF_16(timer_read(), tlast);
-}
-
-uint32_t timer_elapsed32(uint32_t tlast) {
- return TIMER_DIFF_32(timer_read32(), tlast);
-}
-
-void timer_clear(void) {
- set_time(0);
-}
diff --git a/platforms/avr/drivers/spi_master.c b/platforms/avr/drivers/spi_master.c
index 74b847c71a2c..ba7d782ab081 100644
--- a/platforms/avr/drivers/spi_master.c
+++ b/platforms/avr/drivers/spi_master.c
@@ -36,9 +36,18 @@
# define SPI_TIMEOUT 100
#endif
-static pin_t currentSlavePin = NO_PIN;
-static uint8_t currentSlaveConfig = 0;
-static bool currentSlave2X = false;
+static pin_t current_slave_pin = NO_PIN;
+static bool current_cs_active_low = true;
+static uint8_t current_slave_config = 0;
+static bool current_slave_2x = false;
+
+static inline void spi_select(void) {
+ gpio_write_pin(current_slave_pin, current_cs_active_low ? 0 : 1);
+}
+
+static inline void spi_unselect(void) {
+ gpio_write_pin(current_slave_pin, current_cs_active_low ? 1 : 0);
+}
void spi_init(void) {
gpio_write_pin_high(SPI_SS_PIN);
@@ -50,63 +59,74 @@ void spi_init(void) {
}
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
- if (currentSlavePin != NO_PIN || slavePin == NO_PIN) {
+ spi_start_config_t start_config = {0};
+ start_config.slave_pin = slavePin;
+ start_config.lsb_first = lsbFirst;
+ start_config.mode = mode;
+ start_config.divisor = divisor;
+ start_config.cs_active_low = true;
+ return spi_start_extended(&start_config);
+}
+
+bool spi_start_extended(spi_start_config_t *start_config) {
+ if (current_slave_pin != NO_PIN || start_config->slave_pin == NO_PIN) {
return false;
}
- currentSlaveConfig = 0;
+ current_slave_config = 0;
- if (lsbFirst) {
- currentSlaveConfig |= _BV(DORD);
+ if (start_config->lsb_first) {
+ current_slave_config |= _BV(DORD);
}
- switch (mode) {
+ switch (start_config->mode) {
case 1:
- currentSlaveConfig |= _BV(CPHA);
+ current_slave_config |= _BV(CPHA);
break;
case 2:
- currentSlaveConfig |= _BV(CPOL);
+ current_slave_config |= _BV(CPOL);
break;
case 3:
- currentSlaveConfig |= (_BV(CPOL) | _BV(CPHA));
+ current_slave_config |= (_BV(CPOL) | _BV(CPHA));
break;
}
uint16_t roundedDivisor = 1;
- while (roundedDivisor < divisor) {
+ while (roundedDivisor < start_config->divisor) {
roundedDivisor <<= 1;
}
switch (roundedDivisor) {
case 16:
- currentSlaveConfig |= _BV(SPR0);
+ current_slave_config |= _BV(SPR0);
break;
case 64:
- currentSlaveConfig |= _BV(SPR1);
+ current_slave_config |= _BV(SPR1);
break;
case 128:
- currentSlaveConfig |= (_BV(SPR1) | _BV(SPR0));
+ current_slave_config |= (_BV(SPR1) | _BV(SPR0));
break;
case 2:
- currentSlave2X = true;
+ current_slave_2x = true;
break;
case 8:
- currentSlave2X = true;
- currentSlaveConfig |= _BV(SPR0);
+ current_slave_2x = true;
+ current_slave_config |= _BV(SPR0);
break;
case 32:
- currentSlave2X = true;
- currentSlaveConfig |= _BV(SPR1);
+ current_slave_2x = true;
+ current_slave_config |= _BV(SPR1);
break;
}
- SPCR |= currentSlaveConfig;
- if (currentSlave2X) {
+ SPCR |= current_slave_config;
+ if (current_slave_2x) {
SPSR |= _BV(SPI2X);
}
- currentSlavePin = slavePin;
- gpio_set_pin_output(currentSlavePin);
- gpio_write_pin_low(currentSlavePin);
+ current_slave_pin = start_config->slave_pin;
+ current_cs_active_low = start_config->cs_active_low;
+ gpio_set_pin_output(current_slave_pin);
+ spi_select();
return true;
}
@@ -168,13 +188,13 @@ spi_status_t spi_receive(uint8_t *data, uint16_t length) {
}
void spi_stop(void) {
- if (currentSlavePin != NO_PIN) {
- gpio_set_pin_output(currentSlavePin);
- gpio_write_pin_high(currentSlavePin);
- currentSlavePin = NO_PIN;
+ if (current_slave_pin != NO_PIN) {
+ gpio_set_pin_output(current_slave_pin);
+ spi_unselect();
+ current_slave_pin = NO_PIN;
SPSR &= ~(_BV(SPI2X));
- SPCR &= ~(currentSlaveConfig);
- currentSlaveConfig = 0;
- currentSlave2X = false;
+ SPCR &= ~(current_slave_config);
+ current_slave_config = 0;
+ current_slave_2x = false;
}
}
diff --git a/platforms/avr/drivers/spi_master.h b/platforms/avr/drivers/spi_master.h
index 8a30f47ae408..ebbf7ddeab93 100644
--- a/platforms/avr/drivers/spi_master.h
+++ b/platforms/avr/drivers/spi_master.h
@@ -41,9 +41,18 @@ typedef int16_t spi_status_t;
#ifdef __cplusplus
extern "C" {
#endif
+typedef struct spi_start_config_t {
+ pin_t slave_pin;
+ bool lsb_first;
+ uint8_t mode;
+ uint16_t divisor;
+ bool cs_active_low;
+} spi_start_config_t;
+
void spi_init(void);
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor);
+bool spi_start_extended(spi_start_config_t *start_config);
spi_status_t spi_write(uint8_t data);
diff --git a/platforms/avr/drivers/ws2812_bitbang.c b/platforms/avr/drivers/ws2812_bitbang.c
index be127e501c95..183690c96744 100644
--- a/platforms/avr/drivers/ws2812_bitbang.c
+++ b/platforms/avr/drivers/ws2812_bitbang.c
@@ -28,28 +28,6 @@
#define pinmask(pin) (_BV((pin)&0xF))
-/*
- * Forward declare internal functions
- *
- * The functions take a byte-array and send to the data output as WS2812 bitstream.
- * The length is the number of bytes to send - three per LED.
- */
-
-static inline void ws2812_sendarray_mask(uint8_t *data, uint16_t datlen, uint8_t masklo, uint8_t maskhi);
-
-void ws2812_init(void) {
- DDRx_ADDRESS(WS2812_DI_PIN) |= pinmask(WS2812_DI_PIN);
-}
-
-void ws2812_setleds(rgb_led_t *ledarray, uint16_t number_of_leds) {
- uint8_t masklo = ~(pinmask(WS2812_DI_PIN)) & PORTx_ADDRESS(WS2812_DI_PIN);
- uint8_t maskhi = pinmask(WS2812_DI_PIN) | PORTx_ADDRESS(WS2812_DI_PIN);
-
- ws2812_sendarray_mask((uint8_t *)ledarray, number_of_leds * sizeof(rgb_led_t), masklo, maskhi);
-
- _delay_us(WS2812_TRST_US);
-}
-
/*
This routine writes an array of bytes with RGB values to the Dataout pin
using the fast 800kHz clockless WS2811/2812 protocol.
@@ -172,3 +150,33 @@ static inline void ws2812_sendarray_mask(uint8_t *data, uint16_t datlen, uint8_t
SREG = sreg_prev;
}
+
+ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
+
+void ws2812_init(void) {
+ DDRx_ADDRESS(WS2812_DI_PIN) |= pinmask(WS2812_DI_PIN);
+}
+
+void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
+ ws2812_leds[index].r = red;
+ ws2812_leds[index].g = green;
+ ws2812_leds[index].b = blue;
+#if defined(WS2812_RGBW)
+ ws2812_rgb_to_rgbw(&ws2812_leds[index]);
+#endif
+}
+
+void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+ ws2812_set_color(i, red, green, blue);
+ }
+}
+
+void ws2812_flush(void) {
+ uint8_t masklo = ~(pinmask(WS2812_DI_PIN)) & PORTx_ADDRESS(WS2812_DI_PIN);
+ uint8_t maskhi = pinmask(WS2812_DI_PIN) | PORTx_ADDRESS(WS2812_DI_PIN);
+
+ ws2812_sendarray_mask((uint8_t *)ws2812_leds, WS2812_LED_COUNT * sizeof(ws2812_led_t), masklo, maskhi);
+
+ _delay_us(WS2812_TRST_US);
+}
diff --git a/platforms/avr/drivers/ws2812_i2c.c b/platforms/avr/drivers/ws2812_i2c.c
index 86a5ac8394ed..e6b922f4bfea 100644
--- a/platforms/avr/drivers/ws2812_i2c.c
+++ b/platforms/avr/drivers/ws2812_i2c.c
@@ -1,3 +1,6 @@
+// Copyright 2024 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
#include "ws2812.h"
#include "i2c_master.h"
@@ -13,11 +16,24 @@
# define WS2812_I2C_TIMEOUT 100
#endif
+ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
+
void ws2812_init(void) {
i2c_init();
}
-// Setleds for standard RGB
-void ws2812_setleds(rgb_led_t *ledarray, uint16_t leds) {
- i2c_transmit(WS2812_I2C_ADDRESS, (uint8_t *)ledarray, sizeof(rgb_led_t) * leds, WS2812_I2C_TIMEOUT);
+void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
+ ws2812_leds[index].r = red;
+ ws2812_leds[index].g = green;
+ ws2812_leds[index].b = blue;
+}
+
+void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+ ws2812_set_color(i, red, green, blue);
+ }
+}
+
+void ws2812_flush(void) {
+ i2c_transmit(WS2812_I2C_ADDRESS, (uint8_t *)ws2812_leds, WS2812_LED_COUNT * sizeof(ws2812_led_t), WS2812_I2C_TIMEOUT);
}
diff --git a/platforms/avr/timer.c b/platforms/avr/timer.c
index 9fb671ae8d88..26ba0e29fa2d 100644
--- a/platforms/avr/timer.c
+++ b/platforms/avr/timer.c
@@ -25,6 +25,7 @@ along with this program. If not, see .
// counter resolution 1ms
// NOTE: union { uint32_t timer32; struct { uint16_t dummy; uint16_t timer16; }}
volatile uint32_t timer_count;
+static uint32_t saved_ms;
/** \brief timer initialization
*
@@ -78,6 +79,24 @@ inline void timer_clear(void) {
}
}
+/** \brief timer save
+ *
+ * Set saved_ms to current time.
+ */
+void timer_save(void) {
+ saved_ms = timer_read32();
+}
+
+/** \brief timer restore
+ *
+ * Set timer_count to saved_ms
+ */
+void timer_restore(void) {
+ ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+ timer_count = saved_ms;
+ }
+}
+
/** \brief timer read
*
* FIXME: needs doc
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c
new file mode 100644
index 000000000000..28cf7c18e016
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c
@@ -0,0 +1,101 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2023..2024 HorrorTroll
+ ChibiOS - Copyright (C) 2023..2024 Zhaqian
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODT, VAL_GPIOACFGLR, VAL_GPIOACFGHR},
+ {VAL_GPIOBODT, VAL_GPIOBCFGLR, VAL_GPIOBCFGHR},
+#if AT32_HAS_GPIOC
+ {VAL_GPIOCODT, VAL_GPIOCCFGLR, VAL_GPIOCCFGHR},
+#endif
+ {VAL_GPIODODT, VAL_GPIODCFGLR, VAL_GPIODCFGHR},
+#if AT32_HAS_GPIOF
+ {VAL_GPIOFODT, VAL_GPIOFCFGLR, VAL_GPIOFCFGHR},
+#endif
+};
+#endif
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details System clocks are initialized before everything else.
+ */
+void __early_init(void) {
+ at32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ static bool last_status = false;
+
+ if (blkIsTransferring(sdcp))
+ return last_status;
+ return last_status = (bool)palReadPad(GPIOC, GPIOC_PIN11);
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+ IOMUX->REMAP |= IOMUX_REMAP_SWJTAG_MUX_JTAGDIS;
+}
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h
new file mode 100644
index 000000000000..c3ade198bae5
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h
@@ -0,0 +1,207 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2023..2024 HorrorTroll
+ ChibiOS - Copyright (C) 2023..2024 Zhaqian
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for a Generic AT32F415 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_GENERIC_AT32_F415XX
+#define BOARD_NAME "GENERIC AT32F415 board"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(AT32_LEXTCLK)
+#define AT32_LEXTCLK 32768
+#endif
+
+#if !defined(AT32_HEXTCLK)
+#define AT32_HEXTCLK 8000000
+#endif
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define AT32F415KB
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0U
+#define GPIOA_PIN1 1U
+#define GPIOA_PIN2 2U
+#define GPIOA_PIN3 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_PIN5 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_PIN7 7U
+#define GPIOA_PIN8 8U
+#define GPIOA_PIN9 9U
+#define GPIOA_PIN10 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_PIN0 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_PIN3 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_PIN10 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_PIN1 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_PIN7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_PIN13 13U
+#define GPIOC_PIN14 14U
+#define GPIOC_PIN15 15U
+
+#define GPIOD_HEXT_IN 0U
+#define GPIOD_HEXT_OUT 1U
+#define GPIOD_PIN2 2U
+
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with Pull-Up or Pull-Down resistor depending on ODT.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the AT32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ */
+#define VAL_GPIOACFGLR 0x88888B88 /* PA7...PA0 */
+#define VAL_GPIOACFGHR 0x888888B8 /* PA15...PA8 */
+#define VAL_GPIOAODT 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ */
+#define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */
+#define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */
+#define VAL_GPIOBODT 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ */
+#define VAL_GPIOCCFGLR 0x88888888 /* PC7...PC0 */
+#define VAL_GPIOCCFGHR 0x88888888 /* PC15...PC8 */
+#define VAL_GPIOCODT 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0 - Normal input (GPIOD_HEXT_IN).
+ * PD1 - Normal input (GPIOD_HEXT_OUT).
+ */
+#define VAL_GPIODCFGLR 0x88888844 /* PD7...PD0 */
+#define VAL_GPIODCFGHR 0x88888888 /* PD15...PD8 */
+#define VAL_GPIODODT 0xFFFFFFFF
+
+/*
+ * Port F setup.
+ */
+#define VAL_GPIOFCFGLR 0x88888888 /* PF7...PF0 */
+#define VAL_GPIOFCFGHR 0x88888888 /* PF15...PF8 */
+#define VAL_GPIOFODT 0xFFFFFFFF
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.mk b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.mk
new file mode 100644
index 000000000000..842e33590594
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(BOARD_PATH)/board/board.c
+
+# Required include directories
+BOARDINC = $(BOARD_PATH)/board
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h
new file mode 100644
index 000000000000..da60447a0af0
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h
@@ -0,0 +1,13 @@
+// Copyright 2023-2024 HorrorTroll
+// Copyright 2023-2024 Zhaqian
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#define BOARD_OTG_VBUSIG
+
+#define USB_ENDPOINTS_ARE_REORDERABLE
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h
new file mode 100644
index 000000000000..d148379fe1db
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h
@@ -0,0 +1,236 @@
+/*
+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2023..2024 HorrorTroll
+ ChibiOS - Copyright (C) 2023..2024 Zhaqian
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * AT32F415 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define AT32F415_MCUCONF
+
+/*
+ * General settings.
+ */
+#define AT32_NO_INIT FALSE
+
+/*
+ * HAL driver system settings.
+ */
+#define AT32_HICK_ENABLED TRUE
+#define AT32_LICK_ENABLED FALSE
+#define AT32_HEXT_ENABLED TRUE
+#define AT32_LEXT_ENABLED FALSE
+#define AT32_SCLKSEL AT32_SCLKSEL_PLL
+#define AT32_PLLRCS AT32_PLLRCS_HEXT
+#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1
+#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID
+#define AT32_PLLMULT_VALUE 18
+#define AT32_PLL_FR_VALUE 4
+#define AT32_PLL_MS_VALUE 1
+#define AT32_PLL_NS_VALUE 72
+#define AT32_AHBDIV AT32_AHBDIV_DIV1
+#define AT32_APB1DIV AT32_APB1DIV_DIV2
+#define AT32_APB2DIV AT32_APB2DIV_DIV2
+#define AT32_ADCDIV AT32_ADCDIV_DIV4
+#define AT32_USB_CLOCK_REQUIRED TRUE
+#define AT32_USBDIV AT32_USBDIV_DIV3
+#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK
+#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1
+#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV
+#define AT32_PVM_ENABLE FALSE
+#define AT32_PVMSEL AT32_PVMSEL_LEV1
+
+/*
+ * IRQ system settings.
+ */
+#define AT32_IRQ_EXINT0_PRIORITY 6
+#define AT32_IRQ_EXINT1_PRIORITY 6
+#define AT32_IRQ_EXINT2_PRIORITY 6
+#define AT32_IRQ_EXINT3_PRIORITY 6
+#define AT32_IRQ_EXINT4_PRIORITY 6
+#define AT32_IRQ_EXINT5_9_PRIORITY 6
+#define AT32_IRQ_EXINT10_15_PRIORITY 6
+#define AT32_IRQ_EXINT16_PRIORITY 6
+#define AT32_IRQ_EXINT17_PRIORITY 15
+#define AT32_IRQ_EXINT18_PRIORITY 6
+#define AT32_IRQ_EXINT19_PRIORITY 6
+#define AT32_IRQ_EXINT20_PRIORITY 6
+#define AT32_IRQ_EXINT21_PRIORITY 15
+#define AT32_IRQ_EXINT22_PRIORITY 15
+
+#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7
+#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7
+#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7
+#define AT32_IRQ_TMR1_CH_PRIORITY 7
+#define AT32_IRQ_TMR2_PRIORITY 7
+#define AT32_IRQ_TMR3_PRIORITY 7
+#define AT32_IRQ_TMR4_PRIORITY 7
+#define AT32_IRQ_TMR5_PRIORITY 7
+
+#define AT32_IRQ_USART1_PRIORITY 12
+#define AT32_IRQ_USART2_PRIORITY 12
+#define AT32_IRQ_USART3_PRIORITY 12
+#define AT32_IRQ_UART4_PRIORITY 12
+#define AT32_IRQ_UART5_PRIORITY 12
+
+/*
+ * ADC driver system settings.
+ */
+#define AT32_ADC_USE_ADC1 FALSE
+#define AT32_ADC_ADC1_DMA_PRIORITY 2
+#define AT32_ADC_ADC1_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define AT32_CAN_USE_CAN1 FALSE
+#define AT32_CAN_CAN1_IRQ_PRIORITY 11
+
+/*
+ * DMA driver system settings.
+ */
+#define AT32_DMA_USE_DMAMUX TRUE
+
+/*
+ * GPT driver system settings.
+ */
+#define AT32_GPT_USE_TMR1 FALSE
+#define AT32_GPT_USE_TMR2 FALSE
+#define AT32_GPT_USE_TMR3 FALSE
+#define AT32_GPT_USE_TMR4 FALSE
+#define AT32_GPT_USE_TMR5 FALSE
+#define AT32_GPT_USE_TMR9 FALSE
+#define AT32_GPT_USE_TMR10 FALSE
+#define AT32_GPT_USE_TMR11 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define AT32_I2C_USE_I2C1 FALSE
+#define AT32_I2C_USE_I2C2 FALSE
+#define AT32_I2C_BUSY_TIMEOUT 50
+#define AT32_I2C_I2C1_IRQ_PRIORITY 5
+#define AT32_I2C_I2C2_IRQ_PRIORITY 5
+#define AT32_I2C_I2C1_DMA_PRIORITY 3
+#define AT32_I2C_I2C2_DMA_PRIORITY 3
+#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define AT32_ICU_USE_TMR1 FALSE
+#define AT32_ICU_USE_TMR2 FALSE
+#define AT32_ICU_USE_TMR3 FALSE
+#define AT32_ICU_USE_TMR4 FALSE
+#define AT32_ICU_USE_TMR5 FALSE
+#define AT32_ICU_USE_TMR9 FALSE
+#define AT32_ICU_USE_TMR10 FALSE
+#define AT32_ICU_USE_TMR11 FALSE
+
+/*
+ * PWM driver system settings.
+ */
+#define AT32_PWM_USE_TMR1 FALSE
+#define AT32_PWM_USE_TMR2 FALSE
+#define AT32_PWM_USE_TMR3 FALSE
+#define AT32_PWM_USE_TMR4 FALSE
+#define AT32_PWM_USE_TMR5 FALSE
+#define AT32_PWM_USE_TMR9 FALSE
+#define AT32_PWM_USE_TMR10 FALSE
+#define AT32_PWM_USE_TMR11 FALSE
+
+/*
+ * RTC driver system settings.
+ */
+#define AT32_ERTC_DIVA_VALUE 32
+#define AT32_ERTC_DIVB_VALUE 1024
+#define AT32_ERTC_CTRL_INIT 0
+#define AT32_ERTC_TAMP_INIT 0
+
+/*
+ * SDC driver system settings.
+ */
+#define AT32_SDC_SDIO_DMA_PRIORITY 3
+#define AT32_SDC_SDIO_IRQ_PRIORITY 9
+#define AT32_SDC_WRITE_TIMEOUT_MS 1000
+#define AT32_SDC_READ_TIMEOUT_MS 1000
+#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+
+/*
+ * SERIAL driver system settings.
+ */
+#define AT32_SERIAL_USE_USART1 FALSE
+#define AT32_SERIAL_USE_USART2 FALSE
+#define AT32_SERIAL_USE_USART3 FALSE
+#define AT32_SERIAL_USE_UART4 FALSE
+#define AT32_SERIAL_USE_UART5 FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#define AT32_SPI_USE_SPI1 FALSE
+#define AT32_SPI_USE_SPI2 FALSE
+#define AT32_SPI_SPI1_DMA_PRIORITY 1
+#define AT32_SPI_SPI2_DMA_PRIORITY 1
+#define AT32_SPI_SPI1_IRQ_PRIORITY 10
+#define AT32_SPI_SPI2_IRQ_PRIORITY 10
+#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define AT32_ST_IRQ_PRIORITY 8
+#define AT32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define AT32_UART_USE_USART1 FALSE
+#define AT32_UART_USE_USART2 FALSE
+#define AT32_UART_USE_USART3 FALSE
+#define AT32_UART_USART1_DMA_PRIORITY 0
+#define AT32_UART_USART2_DMA_PRIORITY 0
+#define AT32_UART_USART3_DMA_PRIORITY 0
+#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define AT32_USB_USE_OTG1 TRUE
+#define AT32_USB_OTG1_IRQ_PRIORITY 14
+#define AT32_USB_OTG1_RX_FIFO_SIZE 512
+
+/*
+ * WDG driver system settings.
+ */
+#define AT32_WDG_USE_WDT FALSE
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
index 90a41326a16e..5333a919a0b7 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
@@ -21,3 +21,13 @@
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
+
+#ifdef WEAR_LEVELING_EMBEDDED_FLASH
+# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
+# ifdef BOOTLOADER_TINYUF2
+# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
+# else
+# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
+# endif
+# endif
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h
index 90a41326a16e..5333a919a0b7 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h
@@ -21,3 +21,13 @@
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
+
+#ifdef WEAR_LEVELING_EMBEDDED_FLASH
+# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
+# ifdef BOOTLOADER_TINYUF2
+# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
+# else
+# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
+# endif
+# endif
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
index cbb98f90980e..362327efded6 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
@@ -17,3 +17,13 @@
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
+
+#ifdef WEAR_LEVELING_EMBEDDED_FLASH
+# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
+# ifdef BOOTLOADER_TINYUF2
+# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
+# else
+# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
+# endif
+# endif
+#endif
diff --git a/platforms/chibios/boards/common/ld/STM32F401xC.ld b/platforms/chibios/boards/common/ld/STM32F401xC.ld
index 8fae66cec9aa..64f019706fa4 100644
--- a/platforms/chibios/boards/common/ld/STM32F401xC.ld
+++ b/platforms/chibios/boards/common/ld/STM32F401xC.ld
@@ -1,85 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F401xC memory setup.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
- flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
- flash2 (rx) : org = 0x08008000, len = 256k - 32k /* Sector 2..6 - Rest of firmware */
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 64k
- ram1 (wx) : org = 0x00000000, len = 0
- ram2 (wx) : org = 0x00000000, len = 0
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x00000000, len = 0
- ram5 (wx) : org = 0x00000000, len = 0
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash2);
-REGION_ALIAS("XTORS_FLASH_LMA", flash2);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash2);
-REGION_ALIAS("TEXT_FLASH_LMA", flash2);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash2);
-REGION_ALIAS("RODATA_FLASH_LMA", flash2);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash2);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash2);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
+f4xx_flash_size = 256k;
+f4xx_ram1_size = 64k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
+INCLUDE stm32f4xx_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld
index f4e487dc8f92..05aa51917f69 100644
--- a/platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld
@@ -1,88 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F401xC memory setup.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
- flash1 (rx) : org = 0x00000000, len = 0
- flash2 (rx) : org = 0x00000000, len = 0
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 64k
- ram1 (wx) : org = 0x00000000, len = 0
- ram2 (wx) : org = 0x00000000, len = 0
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x00000000, len = 0
- ram5 (wx) : org = 0x00000000, len = 0
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash0);
-REGION_ALIAS("XTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash0);
-REGION_ALIAS("TEXT_FLASH_LMA", flash0);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash0);
-REGION_ALIAS("RODATA_FLASH_LMA", flash0);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash0);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash0);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
+f4xx_flash_size = 256k;
+f4xx_ram1_size = 64k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
-/* TinyUF2 bootloader reset support */
-_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
+INCLUDE stm32f4xx_tinyuf2_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F401xE.ld b/platforms/chibios/boards/common/ld/STM32F401xE.ld
index 69af7ed71ec8..6c72c8f127f5 100644
--- a/platforms/chibios/boards/common/ld/STM32F401xE.ld
+++ b/platforms/chibios/boards/common/ld/STM32F401xE.ld
@@ -1,85 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F401xE memory setup.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
- flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
- flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 96k
- ram1 (wx) : org = 0x00000000, len = 0
- ram2 (wx) : org = 0x00000000, len = 0
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x00000000, len = 0
- ram5 (wx) : org = 0x00000000, len = 0
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash2);
-REGION_ALIAS("XTORS_FLASH_LMA", flash2);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash2);
-REGION_ALIAS("TEXT_FLASH_LMA", flash2);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash2);
-REGION_ALIAS("RODATA_FLASH_LMA", flash2);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash2);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash2);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 96k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
+INCLUDE stm32f4xx_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld
index 895d13fa3223..65272ec015f6 100644
--- a/platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld
@@ -1,88 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F401xE memory setup.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000 + 64k, len = 512k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
- flash1 (rx) : org = 0x00000000, len = 0
- flash2 (rx) : org = 0x00000000, len = 0
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 96k
- ram1 (wx) : org = 0x00000000, len = 0
- ram2 (wx) : org = 0x00000000, len = 0
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x00000000, len = 0
- ram5 (wx) : org = 0x00000000, len = 0
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash0);
-REGION_ALIAS("XTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash0);
-REGION_ALIAS("TEXT_FLASH_LMA", flash0);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash0);
-REGION_ALIAS("RODATA_FLASH_LMA", flash0);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash0);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash0);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 96k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
-/* TinyUF2 bootloader reset support */
-_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
+INCLUDE stm32f4xx_tinyuf2_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F405xG.ld b/platforms/chibios/boards/common/ld/STM32F405xG.ld
index b7d0baa21030..d9468e18c57b 100644
--- a/platforms/chibios/boards/common/ld/STM32F405xG.ld
+++ b/platforms/chibios/boards/common/ld/STM32F405xG.ld
@@ -1,86 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F405xG memory setup.
- * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
- flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
- flash2 (rx) : org = 0x08008000, len = 1M - 32k /* Sector 2..6 - Rest of firmware */
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
- ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
- ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
- ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash2);
-REGION_ALIAS("XTORS_FLASH_LMA", flash2);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash2);
-REGION_ALIAS("TEXT_FLASH_LMA", flash2);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash2);
-REGION_ALIAS("RODATA_FLASH_LMA", flash2);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash2);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash2);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
+f4xx_flash_size = 1M;
+f4xx_ram1_size = 112k;
+f4xx_ram2_size = 16k;
+f4xx_ram4_size = 64k;
+f4xx_ram5_size = 4k;
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
+INCLUDE stm32f4xx_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F405xG_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F405xG_tinyuf2.ld
index 1ee4aa1a06c6..51c4b625ac8e 100644
--- a/platforms/chibios/boards/common/ld/STM32F405xG_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F405xG_tinyuf2.ld
@@ -1,89 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F405xG memory setup.
- * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000 + 64k, len = 1M - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
- flash1 (rx) : org = 0x00000000, len = 0
- flash2 (rx) : org = 0x00000000, len = 0
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
- ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
- ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
- ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash0);
-REGION_ALIAS("XTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash0);
-REGION_ALIAS("TEXT_FLASH_LMA", flash0);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash0);
-REGION_ALIAS("RODATA_FLASH_LMA", flash0);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash0);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash0);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
+f4xx_flash_size = 1M;
+f4xx_ram1_size = 112k;
+f4xx_ram2_size = 16k;
+f4xx_ram4_size = 64k;
+f4xx_ram5_size = 4k;
-/* TinyUF2 bootloader reset support */
-_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
+INCLUDE stm32f4xx_tinyuf2_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F407xE.ld b/platforms/chibios/boards/common/ld/STM32F407xE.ld
new file mode 100644
index 000000000000..66dd99116342
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F407xE.ld
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 112k;
+f4xx_ram2_size = 16k;
+f4xx_ram4_size = 64k;
+f4xx_ram5_size = 4k;
+
+INCLUDE stm32f4xx_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F407xE_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F407xE_tinyuf2.ld
new file mode 100644
index 000000000000..0cb7b89636d1
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F407xE_tinyuf2.ld
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 112k;
+f4xx_ram2_size = 16k;
+f4xx_ram4_size = 64k;
+f4xx_ram5_size = 4k;
+
+INCLUDE stm32f4xx_tinyuf2_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F411xC.ld b/platforms/chibios/boards/common/ld/STM32F411xC.ld
new file mode 100644
index 000000000000..5e3f7e034bc3
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F411xC.ld
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+f4xx_flash_size = 256k;
+f4xx_ram1_size = 128k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
+
+INCLUDE stm32f4xx_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F411xC_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F411xC_tinyuf2.ld
index 82253d3de5db..63a33309fde7 100644
--- a/platforms/chibios/boards/common/ld/STM32F411xC_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F411xC_tinyuf2.ld
@@ -1,89 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F411xC memory setup.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
- flash1 (rx) : org = 0x00000000, len = 0
- flash2 (rx) : org = 0x00000000, len = 0
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 128k
- ram1 (wx) : org = 0x00000000, len = 0
- ram2 (wx) : org = 0x00000000, len = 0
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x00000000, len = 0
- ram5 (wx) : org = 0x00000000, len = 0
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash0);
-REGION_ALIAS("XTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash0);
-REGION_ALIAS("TEXT_FLASH_LMA", flash0);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash0);
-REGION_ALIAS("RODATA_FLASH_LMA", flash0);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash0);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash0);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
-
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
-/* TinyUF2 bootloader reset support */
-_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
+f4xx_flash_size = 256k;
+f4xx_ram1_size = 128k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
+INCLUDE stm32f4xx_tinyuf2_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F411xE.ld b/platforms/chibios/boards/common/ld/STM32F411xE.ld
index aea8084b5167..c798a775e997 100644
--- a/platforms/chibios/boards/common/ld/STM32F411xE.ld
+++ b/platforms/chibios/boards/common/ld/STM32F411xE.ld
@@ -1,85 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F411xE memory setup.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
- flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
- flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 128k
- ram1 (wx) : org = 0x00000000, len = 0
- ram2 (wx) : org = 0x00000000, len = 0
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x00000000, len = 0
- ram5 (wx) : org = 0x00000000, len = 0
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash2);
-REGION_ALIAS("XTORS_FLASH_LMA", flash2);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash2);
-REGION_ALIAS("TEXT_FLASH_LMA", flash2);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash2);
-REGION_ALIAS("RODATA_FLASH_LMA", flash2);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash2);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash2);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 128k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
+INCLUDE stm32f4xx_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F411xE_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F411xE_tinyuf2.ld
index 1656c67bf75c..25253f559075 100644
--- a/platforms/chibios/boards/common/ld/STM32F411xE_tinyuf2.ld
+++ b/platforms/chibios/boards/common/ld/STM32F411xE_tinyuf2.ld
@@ -1,89 +1,13 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * STM32F411xE memory setup.
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
-MEMORY
-{
- flash0 (rx) : org = 0x08000000 + 64k, len = 512k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
- flash1 (rx) : org = 0x00000000, len = 0
- flash2 (rx) : org = 0x00000000, len = 0
- flash3 (rx) : org = 0x00000000, len = 0
- flash4 (rx) : org = 0x00000000, len = 0
- flash5 (rx) : org = 0x00000000, len = 0
- flash6 (rx) : org = 0x00000000, len = 0
- flash7 (rx) : org = 0x00000000, len = 0
- ram0 (wx) : org = 0x20000000, len = 128k
- ram1 (wx) : org = 0x00000000, len = 0
- ram2 (wx) : org = 0x00000000, len = 0
- ram3 (wx) : org = 0x00000000, len = 0
- ram4 (wx) : org = 0x00000000, len = 0
- ram5 (wx) : org = 0x00000000, len = 0
- ram6 (wx) : org = 0x00000000, len = 0
- ram7 (wx) : org = 0x00000000, len = 0
-}
-
-/* For each data/text section two region are defined, a virtual region
- and a load region (_LMA suffix).*/
-
-/* Flash region to be used for exception vectors.*/
-REGION_ALIAS("VECTORS_FLASH", flash0);
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for constructors and destructors.*/
-REGION_ALIAS("XTORS_FLASH", flash0);
-REGION_ALIAS("XTORS_FLASH_LMA", flash0);
-
-/* Flash region to be used for code text.*/
-REGION_ALIAS("TEXT_FLASH", flash0);
-REGION_ALIAS("TEXT_FLASH_LMA", flash0);
-
-/* Flash region to be used for read only data.*/
-REGION_ALIAS("RODATA_FLASH", flash0);
-REGION_ALIAS("RODATA_FLASH_LMA", flash0);
-
-/* Flash region to be used for various.*/
-REGION_ALIAS("VARIOUS_FLASH", flash0);
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
-
-/* Flash region to be used for RAM(n) initialization data.*/
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
-
-/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-
-/* RAM region to be used for the process stack. This is the stack used by
- the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("DATA_RAM_LMA", flash0);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-
-/* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
-
-/* Generic rules inclusion.*/
-INCLUDE rules.ld
-/* TinyUF2 bootloader reset support */
-_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 128k;
+f4xx_ram2_size = 0;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 0;
+INCLUDE stm32f4xx_tinyuf2_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F446xE.ld b/platforms/chibios/boards/common/ld/STM32F446xE.ld
new file mode 100644
index 000000000000..6e6c5dd3a4e7
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F446xE.ld
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 112k;
+f4xx_ram2_size = 16k;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 4k;
+
+INCLUDE stm32f4xx_common.ld
diff --git a/platforms/chibios/boards/common/ld/STM32F446xE_tinyuf2.ld b/platforms/chibios/boards/common/ld/STM32F446xE_tinyuf2.ld
new file mode 100644
index 000000000000..676ffbdf0c0b
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32F446xE_tinyuf2.ld
@@ -0,0 +1,13 @@
+/*
+* Copyright 2006..2018 Giovanni Di Sirio
+ * Copyright 2022 QMK contributors
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+f4xx_flash_size = 512k;
+f4xx_ram1_size = 112k;
+f4xx_ram2_size = 16k;
+f4xx_ram4_size = 0;
+f4xx_ram5_size = 4k;
+
+INCLUDE stm32f4xx_tinyuf2_common.ld
diff --git a/platforms/chibios/boards/common/ld/stm32f4xx_common.ld b/platforms/chibios/boards/common/ld/stm32f4xx_common.ld
new file mode 100644
index 000000000000..d5c7c7362640
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/stm32f4xx_common.ld
@@ -0,0 +1,82 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
+ flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
+ flash2 (rx) : org = 0x08008000, len = f4xx_flash_size - 32k /* Sector 2..6 - Rest of firmware */
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */
+ ram2 (wx) : org = 0x20000000 + f4xx_ram1_size, len = f4xx_ram2_size /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/platforms/chibios/boards/common/ld/stm32f4xx_tinyuf2_common.ld b/platforms/chibios/boards/common/ld/stm32f4xx_tinyuf2_common.ld
new file mode 100644
index 000000000000..d995bd014a3c
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/stm32f4xx_tinyuf2_common.ld
@@ -0,0 +1,88 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F411xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000 + 64k, len = f4xx_flash_size - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */
+ ram2 (wx) : org = 0x20000000 + f4xx_ram1_size, len = f4xx_ram2_size /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
+
+/* TinyUF2 bootloader reset support */
+_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
diff --git a/platforms/chibios/bootloader.mk b/platforms/chibios/bootloader.mk
index 5b6edd73ad34..e292e1e0b08b 100644
--- a/platforms/chibios/bootloader.mk
+++ b/platforms/chibios/bootloader.mk
@@ -26,6 +26,7 @@
# stm32-dfu STM32 USB DFU in ROM
# apm32-dfu APM32 USB DFU in ROM
# wb32-dfu WB32 USB DFU in ROM
+# at32-dfu AT32 USB DFU in ROM
# tinyuf2 TinyUF2
# rp2040 Raspberry Pi RP2040
# Current options for RISC-V:
@@ -119,6 +120,14 @@ ifeq ($(strip $(BOOTLOADER)), wb32-dfu)
OPT_DEFS += -DBOOTLOADER_WB32_DFU
BOOTLOADER_TYPE = wb32_dfu
endif
+ifeq ($(strip $(BOOTLOADER)), at32-dfu)
+ OPT_DEFS += -DBOOTLOADER_AT32_DFU
+ BOOTLOADER_TYPE = at32_dfu
+
+ # Options to pass to dfu-util when flashing
+ DFU_ARGS ?= -d 2E3C:DF11 -a 0 -s 0x08000000:leave
+ DFU_SUFFIX_ARGS ?= -v 2E3C -p DF11
+endif
ifeq ($(strip $(BOOTLOADER_TYPE)),)
ifneq ($(strip $(BOOTLOADER)),)
diff --git a/platforms/chibios/bootloaders/at32_dfu.c b/platforms/chibios/bootloaders/at32_dfu.c
new file mode 100644
index 000000000000..f3a453d0fce8
--- /dev/null
+++ b/platforms/chibios/bootloaders/at32_dfu.c
@@ -0,0 +1,83 @@
+// Copyright 2021-2023 QMK
+// Copyright 2023-2024 HorrorTroll
+// Copyright 2023-2024 Zhaqian
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bootloader.h"
+#include "util.h"
+
+#include
+#include
+#include "wait.h"
+
+#ifndef AT32_BOOTLOADER_RAM_SYMBOL
+# define AT32_BOOTLOADER_RAM_SYMBOL __ram0_end__
+#endif
+
+extern uint32_t AT32_BOOTLOADER_RAM_SYMBOL;
+
+/* This code should be checked whether it runs correctly on platforms */
+#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+#define BOOTLOADER_MAGIC 0xDEADBEEF
+#define MAGIC_ADDR (unsigned long *)(SYMVAL(AT32_BOOTLOADER_RAM_SYMBOL) - 4)
+
+__attribute__((weak)) void bootloader_marker_enable(void) {
+ uint32_t *marker = (uint32_t *)MAGIC_ADDR;
+ *marker = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
+}
+
+__attribute__((weak)) bool bootloader_marker_active(void) {
+ const uint32_t *marker = (const uint32_t *)MAGIC_ADDR;
+ return (*marker == BOOTLOADER_MAGIC) ? true : false;
+}
+
+__attribute__((weak)) void bootloader_marker_disable(void) {
+ uint32_t *marker = (uint32_t *)MAGIC_ADDR;
+ *marker = 0;
+}
+
+__attribute__((weak)) void bootloader_jump(void) {
+ bootloader_marker_enable();
+ NVIC_SystemReset();
+}
+
+__attribute__((weak)) void mcu_reset(void) {
+ NVIC_SystemReset();
+}
+
+void enter_bootloader_mode_if_requested(void) {
+ if (bootloader_marker_active()) {
+ bootloader_marker_disable();
+
+ struct system_memory_vector_t {
+ uint32_t stack_top;
+ void (*entrypoint)(void);
+ };
+ const struct system_memory_vector_t *bootloader = (const struct system_memory_vector_t *)(AT32_BOOTLOADER_ADDRESS);
+
+ __disable_irq();
+
+#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ ARM_MPU_Disable();
+#endif
+
+ SysTick->CTRL = 0;
+ SysTick->VAL = 0;
+ SysTick->LOAD = 0;
+
+ // Clear interrupt enable and interrupt pending registers
+ for (int i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
+ NVIC->ICER[i] = 0xFFFFFFFF;
+ NVIC->ICPR[i] = 0xFFFFFFFF;
+ }
+
+ __set_CONTROL(0);
+ __set_MSP(bootloader->stack_top);
+ __enable_irq();
+
+ // Jump to bootloader
+ bootloader->entrypoint();
+ while (true) {
+ }
+ }
+}
diff --git a/platforms/chibios/chibios_config.h b/platforms/chibios/chibios_config.h
index 8f46fe073608..95136baf3032 100644
--- a/platforms/chibios/chibios_config.h
+++ b/platforms/chibios/chibios_config.h
@@ -142,6 +142,19 @@
# endif
#endif
+// AT32 compatibility
+#if defined(MCU_AT32)
+# define CPU_CLOCK AT32_SYSCLK
+
+# if defined(AT32F415)
+# define USE_GPIOV1
+# define USE_I2CV1
+# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_AT32_ALTERNATE_OPENDRAIN
+# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_AT32_ALTERNATE_PUSHPULL
+# define AUDIO_PWM_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# endif
+#endif
+
#if defined(GD32VF103)
/* This chip has the same API as STM32F103, but uses different names for literally the same thing.
* As of 4.7.2021 QMK is tailored to use STM32 defines/names, for compatibility sake
diff --git a/platforms/chibios/config.h b/platforms/chibios/config.h
index 006415a5dc52..a58479bb9743 100644
--- a/platforms/chibios/config.h
+++ b/platforms/chibios/config.h
@@ -5,3 +5,7 @@
#ifndef CORTEX_ENABLE_WFI_IDLE
# define CORTEX_ENABLE_WFI_IDLE TRUE
#endif // CORTEX_ENABLE_WFI_IDLE
+
+#ifndef SERIAL_NUMBER_USE_HARDWARE_ID
+# define SERIAL_NUMBER_USE_HARDWARE_ID TRUE
+#endif // SERIAL_NUMBER_USE_HARDWARE_ID
diff --git a/platforms/chibios/converters/promicro_to_svlinky/_pin_defs.h b/platforms/chibios/converters/promicro_to_svlinky/_pin_defs.h
new file mode 100644
index 000000000000..b90e5f402038
--- /dev/null
+++ b/platforms/chibios/converters/promicro_to_svlinky/_pin_defs.h
@@ -0,0 +1,36 @@
+// Copyright 2023 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+// Left side (front)
+#define D3 0U
+#define D2 1U
+// GND
+// GND
+#define D1 2U
+#define D0 3U
+#define D4 4U
+#define C6 5U
+#define D7 6U
+#define E6 7U
+#define B4 8U
+#define B5 9U
+
+// Right side (front)
+// RAW
+// GND
+// RESET
+// VCC
+#define F4 29U
+#define F5 28U
+#define F6 18U
+#define F7 24U
+#define B1 22U
+#define B3 20U
+#define B2 23U
+#define B6 21U
+
+// LEDs
+#define D5 17U
+#define B0 25U
diff --git a/platforms/chibios/converters/promicro_to_svlinky/converter.mk b/platforms/chibios/converters/promicro_to_svlinky/converter.mk
new file mode 100644
index 000000000000..bfca20cd9932
--- /dev/null
+++ b/platforms/chibios/converters/promicro_to_svlinky/converter.mk
@@ -0,0 +1,10 @@
+# rp2040_ce MCU settings for converting AVR projects
+MCU := RP2040
+BOARD := QMK_PM2040
+BOOTLOADER := rp2040
+
+# These are defaults based on what has been implemented for RP2040 boards
+SERIAL_DRIVER ?= vendor
+WS2812_DRIVER ?= vendor
+BACKLIGHT_DRIVER ?= software
+OPT_DEFS += -DUSB_VBUS_PIN=19U
diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c
index fb146df9367a..7e1f87e6c95e 100644
--- a/platforms/chibios/drivers/analog.c
+++ b/platforms/chibios/drivers/analog.c
@@ -22,7 +22,7 @@
# error "You need to set HAL_USE_ADC to TRUE in your halconf.h to use the ADC."
#endif
-#if !RP_ADC_USE_ADC1 && !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4 && !WB32_ADC_USE_ADC1
+#if !RP_ADC_USE_ADC1 && !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4 && !WB32_ADC_USE_ADC1 && !AT32_ADC_USE_ADC1
# error "You need to set one of the 'xxx_ADC_USE_ADCx' settings to TRUE in your mcuconf.h to use the ADC."
#endif
@@ -45,7 +45,7 @@
// Otherwise assume V3
#if defined(STM32F0XX) || defined(STM32L0XX)
# define USE_ADCV1
-#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
+#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define USE_ADCV2
#endif
@@ -82,7 +82,7 @@
/* User configurable ADC options */
#ifndef ADC_COUNT
-# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
+# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define ADC_COUNT 1
# elif defined(STM32F3XX) || defined(STM32G4XX)
# define ADC_COUNT 4
@@ -142,11 +142,16 @@ static ADCConversionGroup adcConversionGroup = {
.cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION,
.smpr = ADC_SAMPLING_RATE,
#elif defined(USE_ADCV2)
-# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx)
- .cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
+# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx) && !defined(AT32F415)
+ .cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
# endif
+# if defined(AT32F415)
+ .spt2 = ADC_SPT2_CSPT_AN0(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN1(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN2(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN3(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN4(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN5(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN6(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN7(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN8(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN9(ADC_SAMPLING_RATE),
+ .spt1 = ADC_SPT1_CSPT_AN10(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN11(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN12(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN13(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN14(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN15(ADC_SAMPLING_RATE),
+# else
.smpr2 = ADC_SMPR2_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_RATE),
.smpr1 = ADC_SMPR1_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_RATE),
+# endif
#elif defined(RP2040)
// RP2040 does not have any extra config here
#else
@@ -242,7 +247,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 );
case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 );
# endif
-#elif defined(STM32F1XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
+#elif defined(STM32F1XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
@@ -344,7 +349,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
static inline ADCDriver* intToADCDriver(uint8_t adcInt) {
switch (adcInt) {
-#if RP_ADC_USE_ADC1 || STM32_ADC_USE_ADC1 || WB32_ADC_USE_ADC1
+#if RP_ADC_USE_ADC1 || STM32_ADC_USE_ADC1 || WB32_ADC_USE_ADC1 || AT32_ADC_USE_ADC1
case 0:
return &ADCD1;
#endif
@@ -391,7 +396,11 @@ int16_t adc_read(adc_mux mux) {
// TODO: fix previous assumption of only 1 input...
adcConversionGroup.chselr = 1 << mux.input; /*no macro to convert N to ADC_CHSELR_CHSEL1*/
#elif defined(USE_ADCV2)
+# if defined(AT32F415)
+ adcConversionGroup.osq3 = ADC_OSQ3_OSN1_N(mux.input);
+# else
adcConversionGroup.sqr3 = ADC_SQR3_SQ1_N(mux.input);
+# endif
#elif defined(RP2040)
adcConversionGroup.channel_mask = 1 << mux.input;
#else
diff --git a/platforms/chibios/drivers/backlight_pwm.c b/platforms/chibios/drivers/backlight_pwm.c
index 01e6f71307a4..25fe7962b024 100644
--- a/platforms/chibios/drivers/backlight_pwm.c
+++ b/platforms/chibios/drivers/backlight_pwm.c
@@ -25,7 +25,7 @@
# define BACKLIGHT_PWM_CHANNEL 3
#endif
-// Support for pins which are on TIM1_CH1N - requires STM32_PWM_USE_ADVANCED
+// Support for pins which are on TIM1_CH1N
#ifdef BACKLIGHT_PWM_COMPLEMENTARY_OUTPUT
# if BACKLIGHT_ON_STATE == 1
# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW;
diff --git a/platforms/chibios/drivers/serial_usart.c b/platforms/chibios/drivers/serial_usart.c
index 767ef8726fc3..becf3afbce1e 100644
--- a/platforms/chibios/drivers/serial_usart.c
+++ b/platforms/chibios/drivers/serial_usart.c
@@ -9,6 +9,17 @@
#if defined(SERIAL_USART_CONFIG)
static QMKSerialConfig serial_config = SERIAL_USART_CONFIG;
+#elif defined(MCU_AT32) /* AT32 MCUs */
+static QMKSerialConfig serial_config = {
+ .speed = (SERIAL_USART_SPEED),
+ .ctrl1 = (SERIAL_USART_CTRL1),
+ .ctrl2 = (SERIAL_USART_CTRL2),
+# if !defined(SERIAL_USART_FULL_DUPLEX)
+ .ctrl3 = ((SERIAL_USART_CTRL3) | USART_CTRL3_SLBEN) /* activate half-duplex mode */
+# else
+ .ctrl3 = (SERIAL_USART_CTRL3)
+# endif
+};
#elif defined(MCU_STM32) /* STM32 MCUs */
static QMKSerialConfig serial_config = {
# if HAL_USE_SERIAL
@@ -160,7 +171,7 @@ inline bool serial_transport_receive_blocking(uint8_t* destination, const size_t
* @brief Initiate pins for USART peripheral. Half-duplex configuration.
*/
__attribute__((weak)) void usart_init(void) {
-# if defined(MCU_STM32) /* STM32 MCUs */
+# if defined(MCU_STM32) || defined(MCU_AT32) /* STM32 and AT32 MCUs */
# if defined(USE_GPIOV1)
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
# else
@@ -183,7 +194,7 @@ __attribute__((weak)) void usart_init(void) {
* @brief Initiate pins for USART peripheral. Full-duplex configuration.
*/
__attribute__((weak)) void usart_init(void) {
-# if defined(MCU_STM32) /* STM32 MCUs */
+# if defined(MCU_STM32) || defined(MCU_AT32) /* STM32 and AT32 MCUs */
# if defined(USE_GPIOV1)
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_PUSHPULL);
palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_INPUT);
diff --git a/platforms/chibios/drivers/serial_usart.h b/platforms/chibios/drivers/serial_usart.h
index dec8a292e98b..dbd7673273f0 100644
--- a/platforms/chibios/drivers/serial_usart.h
+++ b/platforms/chibios/drivers/serial_usart.h
@@ -74,40 +74,75 @@ typedef SIOConfig QMKSerialConfig;
# endif
#endif
-#if !defined(USART_CR1_M0)
-# define USART_CR1_M0 USART_CR1_M // some platforms (f1xx) dont have this so
-#endif
+#if defined(MCU_STM32) /* STM32 MCUs */
+# if !defined(USART_CR1_M0)
+# define USART_CR1_M0 USART_CR1_M // some platforms (f1xx) dont have this so
+# endif
-#if !defined(SERIAL_USART_CR1)
-# define SERIAL_USART_CR1 (USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0) // parity enable, odd parity, 9 bit length
-#endif
+# if !defined(SERIAL_USART_CR1)
+# define SERIAL_USART_CR1 (USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0) // parity enable, odd parity, 9 bit length
+# endif
-#if !defined(SERIAL_USART_CR2)
-# define SERIAL_USART_CR2 (USART_CR2_STOP_1) // 2 stop bits
-#endif
+# if !defined(SERIAL_USART_CR2)
+# define SERIAL_USART_CR2 (USART_CR2_STOP_1) // 2 stop bits
+# endif
-#if !defined(SERIAL_USART_CR3)
-# define SERIAL_USART_CR3 0
-#endif
+# if !defined(SERIAL_USART_CR3)
+# define SERIAL_USART_CR3 0
+# endif
+
+# if defined(USART1_REMAP)
+# define USART_REMAP \
+ do { \
+ (AFIO->MAPR |= AFIO_MAPR_USART1_REMAP); \
+ } while (0)
+# elif defined(USART2_REMAP)
+# define USART_REMAP \
+ do { \
+ (AFIO->MAPR |= AFIO_MAPR_USART2_REMAP); \
+ } while (0)
+# elif defined(USART3_PARTIALREMAP)
+# define USART_REMAP \
+ do { \
+ (AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
+ } while (0)
+# elif defined(USART3_FULLREMAP)
+# define USART_REMAP \
+ do { \
+ (AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP); \
+ } while (0)
+# endif
+#elif defined(MCU_AT32) /* AT32 MCUs */
+# if !defined(USART_CTRL1_DBN0)
+# define USART_CTRL1_DBN0 USART_CTRL1_DBN
+# endif
-#if defined(USART1_REMAP)
-# define USART_REMAP \
- do { \
- (AFIO->MAPR |= AFIO_MAPR_USART1_REMAP); \
- } while (0)
-#elif defined(USART2_REMAP)
-# define USART_REMAP \
- do { \
- (AFIO->MAPR |= AFIO_MAPR_USART2_REMAP); \
- } while (0)
-#elif defined(USART3_PARTIALREMAP)
-# define USART_REMAP \
- do { \
- (AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
- } while (0)
-#elif defined(USART3_FULLREMAP)
-# define USART_REMAP \
- do { \
- (AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP); \
- } while (0)
+# if !defined(SERIAL_USART_CTRL1)
+# define SERIAL_USART_CTRL1 (USART_CTRL1_PEN | USART_CTRL1_PSEL | USART_CTRL1_DBN0) // parity enable, odd parity, 9 bit length
+# endif
+
+# if !defined(SERIAL_USART_CTRL2)
+# define SERIAL_USART_CTRL2 (USART_CTRL2_STOPBN_1) // 2 stop bits
+# endif
+
+# if !defined(SERIAL_USART_CTRL3)
+# define SERIAL_USART_CTRL3 0
+# endif
+
+# if defined(USART1_REMAP)
+# define USART_REMAP \
+ do { \
+ (IOMUX->REMAP |= IOMUX_REMAP_USART1_MUX); \
+ } while (0)
+# elif defined(USART3_PARTIALREMAP)
+# define USART_REMAP \
+ do { \
+ (IOMUX->REMAP |= IOMUX_REMAP_USART3_MUX_MUX1); \
+ } while (0)
+# elif defined(USART3_FULLREMAP)
+# define USART_REMAP \
+ do { \
+ (IOMUX->REMAP |= IOMUX_REMAP_USART3_MUX_MUX2); \
+ } while (0)
+# endif
#endif
diff --git a/platforms/chibios/drivers/spi_master.c b/platforms/chibios/drivers/spi_master.c
index fcdbc9ecf0ca..6417b7077f54 100644
--- a/platforms/chibios/drivers/spi_master.c
+++ b/platforms/chibios/drivers/spi_master.c
@@ -19,13 +19,33 @@
#include "timer.h"
static bool spiStarted = false;
-
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
-static pin_t currentSlavePin;
+static pin_t current_slave_pin = NO_PIN;
+static bool current_cs_active_low = true;
#endif
static SPIConfig spiConfig;
+static inline void spi_select(void) {
+ spiSelect(&SPI_DRIVER);
+
+#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
+ if (current_slave_pin != NO_PIN) {
+ gpio_write_pin(current_slave_pin, current_cs_active_low ? 0 : 1);
+ }
+#endif
+}
+
+static inline void spi_unselect(void) {
+#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
+ if (current_slave_pin != NO_PIN) {
+ gpio_write_pin(current_slave_pin, current_cs_active_low ? 1 : 0);
+ }
+#endif
+
+ spiUnselect(&SPI_DRIVER);
+}
+
__attribute__((weak)) void spi_init(void) {
static bool is_initialised = false;
if (!is_initialised) {
@@ -63,7 +83,7 @@ __attribute__((weak)) void spi_init(void) {
}
}
-bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
+bool spi_start_extended(spi_start_config_t *start_config) {
#if (SPI_USE_MUTUAL_EXCLUSION == TRUE)
spiAcquireBus(&SPI_DRIVER);
#endif // (SPI_USE_MUTUAL_EXCLUSION == TRUE)
@@ -71,32 +91,37 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
if (spiStarted) {
return false;
}
-
#if SPI_SELECT_MODE != SPI_SELECT_MODE_NONE
- if (slavePin == NO_PIN) {
+ if (start_config->slave_pin == NO_PIN) {
return false;
}
#endif
#if !(defined(WB32F3G71xx) || defined(WB32FQ95xx))
uint16_t roundedDivisor = 2;
- while (roundedDivisor < divisor) {
+ while (roundedDivisor < start_config->divisor) {
roundedDivisor <<= 1;
}
+# if defined(AT32F415)
+ if (roundedDivisor < 2 || roundedDivisor > 1024) {
+ return false;
+ }
+# else
if (roundedDivisor < 2 || roundedDivisor > 256) {
return false;
}
+# endif
#endif
#if defined(K20x) || defined(KL2x)
spiConfig.tar0 = SPIx_CTARn_FMSZ(7) | SPIx_CTARn_ASC(1);
- if (lsbFirst) {
+ if (start_config->lsb_first) {
spiConfig.tar0 |= SPIx_CTARn_LSBFE;
}
- switch (mode) {
+ switch (start_config->mode) {
case 0:
break;
case 1:
@@ -141,11 +166,11 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.cr0 = SPI_CR0_SELOEN;
spiConfig.cr1 = SPI_CR1_MODE | 8; // 8 bits and in master mode
- if (lsbFirst) {
+ if (start_config->lsb_first) {
spiConfig.cr1 |= SPI_CR1_FIRSTBIT;
}
- switch (mode) {
+ switch (start_config->mode) {
case 0:
spiConfig.cr1 |= SPI_CR1_FORMAT_MODE0;
break;
@@ -163,17 +188,17 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.cpr = (roundedDivisor - 1) >> 1;
#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
- if (!lsbFirst) {
- osalDbgAssert(lsbFirst != FALSE, "unsupported lsbFirst");
+ if (!start_config->lsb_first) {
+ osalDbgAssert(start_config->lsb_first != FALSE, "unsupported lsb_first");
}
- if (divisor < 1) {
+ if (start_config->divisor < 1) {
return false;
}
- spiConfig.SPI_BaudRatePrescaler = (divisor << 2);
+ spiConfig.SPI_BaudRatePrescaler = (start_config->divisor << 2);
- switch (mode) {
+ switch (start_config->mode) {
case 0:
spiConfig.SPI_CPHA = SPI_CPHA_1Edge;
spiConfig.SPI_CPOL = SPI_CPOL_Low;
@@ -192,8 +217,8 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
break;
}
#elif defined(MCU_RP)
- if (lsbFirst) {
- osalDbgAssert(lsbFirst == false, "RP2040s PrimeCell SPI implementation does not support sending LSB first.");
+ if (start_config->lsb_first) {
+ osalDbgAssert(start_config->lsb_first == false, "RP2040s PrimeCell SPI implementation does not support sending LSB first.");
}
// Motorola frame format and 8bit transfer data size.
@@ -203,7 +228,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
// passed divisor to be the only value to divide the input clock by.
spiConfig.SSPCPSR = roundedDivisor; // Even number from 2 to 254
- switch (mode) {
+ switch (start_config->mode) {
case 0:
spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPO; // Clock polarity: low
spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPH; // Clock phase: sample on first edge
@@ -221,14 +246,67 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.SSPCR0 |= SPI_SSPCR0_SPH; // Clock phase: sample on second edge transition
break;
}
+#elif defined(AT32F415)
+ spiConfig.ctrl1 = 0;
+
+ if (lsbFirst) {
+ spiConfig.ctrl1 |= SPI_CTRL1_LTF;
+ }
+
+ switch (mode) {
+ case 0:
+ break;
+ case 1:
+ spiConfig.ctrl1 |= SPI_CTRL1_CLKPHA;
+ break;
+ case 2:
+ spiConfig.ctrl1 |= SPI_CTRL1_CLKPOL;
+ break;
+ case 3:
+ spiConfig.ctrl1 |= SPI_CTRL1_CLKPHA | SPI_CTRL1_CLKPOL;
+ break;
+ }
+
+ switch (roundedDivisor) {
+ case 2:
+ break;
+ case 4:
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_0;
+ break;
+ case 8:
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_1;
+ break;
+ case 16:
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0;
+ break;
+ case 32:
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2;
+ break;
+ case 64:
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_0;
+ break;
+ case 128:
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1;
+ break;
+ case 256:
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0;
+ break;
+ case 512:
+ spiConfig.ctrl2 |= SPI_CTRL1_MDIV_3;
+ break;
+ case 1024:
+ spiConfig.ctrl2 |= SPI_CTRL1_MDIV_3;
+ spiConfig.ctrl1 |= SPI_CTRL1_MDIV_0;
+ break;
+ }
#else
spiConfig.cr1 = 0;
- if (lsbFirst) {
+ if (start_config->lsb_first) {
spiConfig.cr1 |= SPI_CR1_LSBFIRST;
}
- switch (mode) {
+ switch (start_config->mode) {
case 0:
break;
case 1:
@@ -271,31 +349,37 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiStarted = true;
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
- currentSlavePin = slavePin;
+ current_slave_pin = start_config->slave_pin;
+ current_cs_active_low = start_config->cs_active_low;
#endif
#if SPI_SELECT_MODE == SPI_SELECT_MODE_PAD
- spiConfig.ssport = PAL_PORT(slavePin);
- spiConfig.sspad = PAL_PAD(slavePin);
- gpio_set_pin_output(slavePin);
+ spiConfig.ssport = PAL_PORT(start_config->slave_pin);
+ spiConfig.sspad = PAL_PAD(start_config->slave_pin);
+ gpio_set_pin_output(start_config->slave_pin);
#elif SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
- if (slavePin != NO_PIN) {
- gpio_set_pin_output(slavePin);
+ if (start_config->slave_pin != NO_PIN) {
+ gpio_set_pin_output(start_config->slave_pin);
}
#else
# error "Unsupported SPI_SELECT_MODE"
#endif
spiStart(&SPI_DRIVER, &spiConfig);
- spiSelect(&SPI_DRIVER);
-#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
- if (slavePin != NO_PIN) {
- gpio_write_pin_low(slavePin);
- }
-#endif
+ spi_select();
return true;
}
+bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
+ spi_start_config_t start_config = {0};
+ start_config.slave_pin = slavePin;
+ start_config.lsb_first = lsbFirst;
+ start_config.mode = mode;
+ start_config.divisor = divisor;
+ start_config.cs_active_low = true;
+ return spi_start_extended(&start_config);
+}
+
spi_status_t spi_write(uint8_t data) {
uint8_t rxData;
spiExchange(&SPI_DRIVER, 1, &data, &rxData);
@@ -322,12 +406,7 @@ spi_status_t spi_receive(uint8_t *data, uint16_t length) {
void spi_stop(void) {
if (spiStarted) {
-#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
- if (currentSlavePin != NO_PIN) {
- gpio_write_pin_high(currentSlavePin);
- }
-#endif
- spiUnselect(&SPI_DRIVER);
+ spi_unselect();
spiStop(&SPI_DRIVER);
spiStarted = false;
}
diff --git a/platforms/chibios/drivers/spi_master.h b/platforms/chibios/drivers/spi_master.h
index 6a3ce481f1ac..4ad6144091e0 100644
--- a/platforms/chibios/drivers/spi_master.h
+++ b/platforms/chibios/drivers/spi_master.h
@@ -75,9 +75,18 @@ typedef int16_t spi_status_t;
#ifdef __cplusplus
extern "C" {
#endif
+typedef struct spi_start_config_t {
+ pin_t slave_pin;
+ bool lsb_first;
+ uint8_t mode;
+ uint16_t divisor;
+ bool cs_active_low;
+} spi_start_config_t;
+
void spi_init(void);
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor);
+bool spi_start_extended(spi_start_config_t *start_config);
spi_status_t spi_write(uint8_t data);
diff --git a/platforms/chibios/drivers/vendor/RP/RP2040/ws2812_vendor.c b/platforms/chibios/drivers/vendor/RP/RP2040/ws2812_vendor.c
index 41a5311719f1..6cf035e1f2b1 100644
--- a/platforms/chibios/drivers/vendor/RP/RP2040/ws2812_vendor.c
+++ b/platforms/chibios/drivers/vendor/RP/RP2040/ws2812_vendor.c
@@ -266,19 +266,36 @@ static inline void sync_ws2812_transfer(void) {
busy_wait_until(LAST_TRANSFER);
}
-void ws2812_setleds(rgb_led_t* ledarray, uint16_t leds) {
+ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
+
+void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
+ ws2812_leds[index].r = red;
+ ws2812_leds[index].g = green;
+ ws2812_leds[index].b = blue;
+#if defined(WS2812_RGBW)
+ ws2812_rgb_to_rgbw(&ws2812_leds[index]);
+#endif
+}
+
+void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+ ws2812_set_color(i, red, green, blue);
+ }
+}
+
+void ws2812_flush(void) {
sync_ws2812_transfer();
- for (int i = 0; i < leds; i++) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
#if defined(WS2812_RGBW)
- WS2812_BUFFER[i] = rgbw8888_to_u32(ledarray[i].r, ledarray[i].g, ledarray[i].b, ledarray[i].w);
+ WS2812_BUFFER[i] = rgbw8888_to_u32(ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b, ws2812_leds[i].w);
#else
- WS2812_BUFFER[i] = rgbw8888_to_u32(ledarray[i].r, ledarray[i].g, ledarray[i].b, 0);
+ WS2812_BUFFER[i] = rgbw8888_to_u32(ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b, 0);
#endif
}
dmaChannelSetSourceX(dma_channel, (uint32_t)WS2812_BUFFER);
- dmaChannelSetCounterX(dma_channel, leds);
+ dmaChannelSetCounterX(dma_channel, WS2812_LED_COUNT);
dmaChannelSetModeX(dma_channel, RP_DMA_MODE_WS2812);
dmaChannelEnableX(dma_channel);
}
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
index f49c4a45b0bf..fed16d20b1aa 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
@@ -33,7 +33,7 @@ static inline uint32_t detect_flash_size(void) {
#elif defined(FLASH_SIZE)
return FLASH_SIZE;
#elif defined(FLASHSIZE_BASE)
-# if defined(QMK_MCU_SERIES_STM32F0XX) || defined(QMK_MCU_SERIES_STM32F1XX) || defined(QMK_MCU_SERIES_STM32F3XX) || defined(QMK_MCU_SERIES_STM32F4XX) || defined(QMK_MCU_SERIES_STM32G4XX) || defined(QMK_MCU_SERIES_STM32L0XX) || defined(QMK_MCU_SERIES_STM32L4XX) || defined(QMK_MCU_SERIES_GD32VF103)
+# if defined(QMK_MCU_SERIES_STM32F0XX) || defined(QMK_MCU_SERIES_STM32F1XX) || defined(QMK_MCU_SERIES_STM32F3XX) || defined(QMK_MCU_SERIES_STM32F4XX) || defined(QMK_MCU_SERIES_STM32G4XX) || defined(QMK_MCU_SERIES_STM32L0XX) || defined(QMK_MCU_SERIES_STM32L4XX) || defined(QMK_MCU_SERIES_AT32F415) || defined(QMK_MCU_SERIES_GD32VF103)
return ((*(uint32_t *)FLASHSIZE_BASE) & 0xFFFFU) << 10U; // this register has the flash size in kB, so we convert it to bytes
# elif defined(QMK_MCU_SERIES_STM32L1XX)
# error This MCU family has an uncommon flash size register definition and has not been implemented. Perhaps try using the true EEPROM on the MCU instead?
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl_config.h b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl_config.h
index 0f0fa694e9c5..f09f824bd8bd 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl_config.h
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl_config.h
@@ -16,6 +16,8 @@
# define BACKING_STORE_WRITE_SIZE 4 // from hal_efl_lld.c
# elif defined(QMK_MCU_FAMILY_WB32)
# define BACKING_STORE_WRITE_SIZE 8 // from hal_efl_lld.c
+# elif defined(QMK_MCU_FAMILY_AT32)
+# define BACKING_STORE_WRITE_SIZE 2 // from hal_efl_lld.c
# elif defined(QMK_MCU_FAMILY_STM32)
# if defined(STM32_FLASH_LINE_SIZE) // from some family's stm32_registry.h file
# define BACKING_STORE_WRITE_SIZE (STM32_FLASH_LINE_SIZE)
diff --git a/platforms/chibios/drivers/ws2812_bitbang.c b/platforms/chibios/drivers/ws2812_bitbang.c
index 96378ec0ac50..a88c5ff619d5 100644
--- a/platforms/chibios/drivers/ws2812_bitbang.c
+++ b/platforms/chibios/drivers/ws2812_bitbang.c
@@ -11,7 +11,7 @@
/* Adapted from https://github.com/bigjosh/SimpleNeoPixelDemo/ */
#ifndef WS2812_BITBANG_NOP_FUDGE
-# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
+# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define WS2812_BITBANG_NOP_FUDGE 0.4
# else
# if defined(RP2040)
@@ -76,33 +76,49 @@ void sendByte(uint8_t byte) {
}
}
+ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
+
void ws2812_init(void) {
palSetLineMode(WS2812_DI_PIN, WS2812_OUTPUT_MODE);
}
-// Setleds for standard RGB
-void ws2812_setleds(rgb_led_t *ledarray, uint16_t leds) {
+void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
+ ws2812_leds[index].r = red;
+ ws2812_leds[index].g = green;
+ ws2812_leds[index].b = blue;
+#if defined(WS2812_RGBW)
+ ws2812_rgb_to_rgbw(&ws2812_leds[index]);
+#endif
+}
+
+void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+ ws2812_set_color(i, red, green, blue);
+ }
+}
+
+void ws2812_flush(void) {
// this code is very time dependent, so we need to disable interrupts
chSysLock();
- for (uint8_t i = 0; i < leds; i++) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
// WS2812 protocol dictates grb order
#if (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_GRB)
- sendByte(ledarray[i].g);
- sendByte(ledarray[i].r);
- sendByte(ledarray[i].b);
+ sendByte(ws2812_leds[i].g);
+ sendByte(ws2812_leds[i].r);
+ sendByte(ws2812_leds[i].b);
#elif (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_RGB)
- sendByte(ledarray[i].r);
- sendByte(ledarray[i].g);
- sendByte(ledarray[i].b);
+ sendByte(ws2812_leds[i].r);
+ sendByte(ws2812_leds[i].g);
+ sendByte(ws2812_leds[i].b);
#elif (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_BGR)
- sendByte(ledarray[i].b);
- sendByte(ledarray[i].g);
- sendByte(ledarray[i].r);
+ sendByte(ws2812_leds[i].b);
+ sendByte(ws2812_leds[i].g);
+ sendByte(ws2812_leds[i].r);
#endif
#ifdef WS2812_RGBW
- sendByte(ledarray[i].w);
+ sendByte(ws2812_leds[i].w);
#endif
}
diff --git a/platforms/chibios/drivers/ws2812_pwm.c b/platforms/chibios/drivers/ws2812_pwm.c
index 1e9d2ebb4105..50927b849a41 100644
--- a/platforms/chibios/drivers/ws2812_pwm.c
+++ b/platforms/chibios/drivers/ws2812_pwm.c
@@ -40,6 +40,9 @@
#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_ID)
# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_ID STM32_DMAMUX1_TIM?_UP"
#endif
+#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_CHANNEL) && !defined(WS2812_PWM_DMAMUX_ID)
+# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_CHANNEL 1, #define WS2812_PWM_DMAMUX_ID AT32_DMAMUX_TMR?_OVERFLOW"
+#endif
/* Summarize https://www.st.com/resource/en/application_note/an4013-stm32-crossseries-timer-overview-stmicroelectronics.pdf to
* figure out if we are using a 32bit timer. This is needed to setup the DMA controller correctly.
@@ -79,15 +82,15 @@
# endif
#endif
-#ifndef WS2812_PWM_TARGET_PERIOD
-//# define WS2812_PWM_TARGET_PERIOD 800000 // Original code is 800k...?
-# define WS2812_PWM_TARGET_PERIOD 80000 // TODO: work out why 10x less on f303/f4x1
+// Default is 800000Hz, which has a period of 1.25us
+#ifndef WS2812_PWM_FREQUENCY
+# define WS2812_PWM_FREQUENCY (1000000000 / WS2812_TIMING)
#endif
/* --- PRIVATE CONSTANTS ---------------------------------------------------- */
-#define WS2812_PWM_FREQUENCY (CPU_CLOCK / 2) /**< Clock frequency of PWM, must be valid with respect to system clock! */
-#define WS2812_PWM_PERIOD (WS2812_PWM_FREQUENCY / WS2812_PWM_TARGET_PERIOD) /**< Clock period in ticks. 1 / 800kHz = 1.25 uS (as per datasheet) */
+#define WS2812_PWM_TICK_FREQUENCY (CPU_CLOCK / 2) /**< Clock frequency of PWM ticks, must be valid with respect to system clock! */
+#define WS2812_PWM_PERIOD (WS2812_PWM_TICK_FREQUENCY / WS2812_PWM_FREQUENCY) /**< Clock period in PWM ticks. */
/**
* @brief Number of bit-periods to hold the data line low at the end of a frame
@@ -102,37 +105,16 @@
/**
* @brief High period for a zero, in ticks
- *
- * Per the datasheet:
- * WS2812:
- * - T0H: 200 nS to 500 nS, inclusive
- * - T0L: 650 nS to 950 nS, inclusive
- * WS2812B:
- * - T0H: 200 nS to 500 nS, inclusive
- * - T0L: 750 nS to 1050 nS, inclusive
- *
- * The duty cycle is calculated for a high period of 350 nS.
*/
-#define WS2812_DUTYCYCLE_0 (WS2812_PWM_FREQUENCY / (1000000000 / 350))
+#define WS2812_DUTYCYCLE_0 (WS2812_PWM_TICK_FREQUENCY / (1000000000 / WS2812_T0H))
#if (WS2812_DUTYCYCLE_0 > 255)
# error WS2812 PWM driver: High period for a 0 is more than a byte
#endif
/**
* @brief High period for a one, in ticks
- *
- * Per the datasheet:
- * WS2812:
- * - T1H: 550 nS to 850 nS, inclusive
- * - T1L: 450 nS to 750 nS, inclusive
- * WS2812B:
- * - T1H: 750 nS to 1050 nS, inclusive
- * - T1L: 200 nS to 500 nS, inclusive
- *
- * The duty cycle is calculated for a high period of 800 nS.
- * This is in the middle of the specifications of the WS2812 and WS2812B.
*/
-#define WS2812_DUTYCYCLE_1 (WS2812_PWM_FREQUENCY / (1000000000 / 800))
+#define WS2812_DUTYCYCLE_1 (WS2812_PWM_TICK_FREQUENCY / (1000000000 / WS2812_T1H))
#if (WS2812_DUTYCYCLE_1 > 255)
# error WS2812 PWM driver: High period for a 1 is more than a byte
#endif
@@ -290,6 +272,14 @@ typedef uint32_t ws2812_buffer_t;
# define WS2812_PWM_DMA_PERIPHERAL_WIDTH STM32_DMA_CR_PSIZE_HWORD
typedef uint16_t ws2812_buffer_t;
# endif
+#elif defined(AT32F415)
+# define WS2812_PWM_DMA_MEMORY_WIDTH AT32_DMA_CCTRL_MWIDTH_BYTE
+# if defined(WS2812_PWM_TIMER_32BIT)
+# define WS2812_PWM_DMA_PERIPHERAL_WIDTH AT32_DMA_CCTRL_PWIDTH_WORD
+# else
+# define WS2812_PWM_DMA_PERIPHERAL_WIDTH AT32_DMA_CCTRL_PWIDTH_HWORD
+# endif
+typedef uint8_t ws2812_buffer_t;
#else
# define WS2812_PWM_DMA_MEMORY_WIDTH STM32_DMA_CR_MSIZE_BYTE
# if defined(WS2812_PWM_TIMER_32BIT)
@@ -322,7 +312,7 @@ void ws2812_init(void) {
// PWM Configuration
//#pragma GCC diagnostic ignored "-Woverride-init" // Turn off override-init warning for this struct. We use the overriding ability to set a "default" channel config
static const PWMConfig ws2812_pwm_config = {
- .frequency = WS2812_PWM_FREQUENCY,
+ .frequency = WS2812_PWM_TICK_FREQUENCY,
.period = WS2812_PWM_PERIOD, // Mit dieser Periode wird UDE-Event erzeugt und ein neuer Wert (Länge WS2812_BIT_N) vom DMA ins CCR geschrieben
.callback = NULL,
.channels =
@@ -330,8 +320,13 @@ void ws2812_init(void) {
[0 ... 3] = {.mode = PWM_OUTPUT_DISABLED, .callback = NULL}, // Channels default to disabled
[WS2812_PWM_CHANNEL - 1] = {.mode = WS2812_PWM_OUTPUT_MODE, .callback = NULL}, // Turn on the channel we care about
},
+#if defined(AT32F415)
+ .ctrl2 = 0,
+ .iden = AT32_TMR_IDEN_OVFDEN, // DMA on update event for next period
+#else
.cr2 = 0,
.dier = TIM_DIER_UDE, // DMA on update event for next period
+#endif
};
//#pragma GCC diagnostic pop // Restore command-line warning options
@@ -342,6 +337,11 @@ void ws2812_init(void) {
dmaStreamSetSource(WS2812_PWM_DMA_STREAM, ws2812_frame_buffer);
dmaStreamSetDestination(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tim->CCR[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
dmaStreamSetMode(WS2812_PWM_DMA_STREAM, WB32_DMA_CHCFG_HWHIF(WS2812_PWM_DMA_CHANNEL) | WB32_DMA_CHCFG_DIR_M2P | WB32_DMA_CHCFG_PSIZE_WORD | WB32_DMA_CHCFG_MSIZE_WORD | WB32_DMA_CHCFG_MINC | WB32_DMA_CHCFG_CIRC | WB32_DMA_CHCFG_TCIE | WB32_DMA_CHCFG_PL(3));
+#elif defined(AT32F415)
+ dmaStreamAlloc(WS2812_PWM_DMA_STREAM - AT32_DMA_STREAM(0), 10, NULL, NULL);
+ dmaStreamSetPeripheral(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tmr->CDT[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
+ dmaStreamSetMemory0(WS2812_PWM_DMA_STREAM, ws2812_frame_buffer);
+ dmaStreamSetMode(WS2812_PWM_DMA_STREAM, AT32_DMA_CCTRL_DTD_M2P | WS2812_PWM_DMA_PERIPHERAL_WIDTH | WS2812_PWM_DMA_MEMORY_WIDTH | AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_CHPL(3));
#else
dmaStreamAlloc(WS2812_PWM_DMA_STREAM - STM32_DMA_STREAM(0), 10, NULL, NULL);
dmaStreamSetPeripheral(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tim->CCR[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
@@ -356,6 +356,11 @@ void ws2812_init(void) {
dmaSetRequestSource(WS2812_PWM_DMA_STREAM, WS2812_PWM_DMAMUX_ID);
#endif
+#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE)
+ // If the MCU has a DMAMUX we need to assign the correct resource
+ dmaSetRequestSource(WS2812_PWM_DMA_STREAM, WS2812_PWM_DMAMUX_CHANNEL, WS2812_PWM_DMAMUX_ID);
+#endif
+
// Start DMA
dmaStreamEnable(WS2812_PWM_DMA_STREAM);
@@ -387,13 +392,29 @@ void ws2812_write_led_rgbw(uint16_t led_number, uint8_t r, uint8_t g, uint8_t b,
}
}
-// Setleds for standard RGB
-void ws2812_setleds(rgb_led_t* ledarray, uint16_t leds) {
- for (uint16_t i = 0; i < leds; i++) {
-#ifdef WS2812_RGBW
- ws2812_write_led_rgbw(i, ledarray[i].r, ledarray[i].g, ledarray[i].b, ledarray[i].w);
+ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
+
+void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
+ ws2812_leds[index].r = red;
+ ws2812_leds[index].g = green;
+ ws2812_leds[index].b = blue;
+#if defined(WS2812_RGBW)
+ ws2812_rgb_to_rgbw(&ws2812_leds[index]);
+#endif
+}
+
+void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+ ws2812_set_color(i, red, green, blue);
+ }
+}
+
+void ws2812_flush(void) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+#if defined(WS2812_RGBW)
+ ws2812_write_led_rgbw(i, ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b, ws2812_leds[i].w);
#else
- ws2812_write_led(i, ledarray[i].r, ledarray[i].g, ledarray[i].b);
+ ws2812_write_led(i, ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b);
#endif
}
}
diff --git a/platforms/chibios/drivers/ws2812_spi.c b/platforms/chibios/drivers/ws2812_spi.c
index 9896f9e69d8e..d1792b871bf0 100644
--- a/platforms/chibios/drivers/ws2812_spi.c
+++ b/platforms/chibios/drivers/ws2812_spi.c
@@ -40,26 +40,53 @@
// Define SPI config speed
// baudrate should target 3.2MHz
+#if defined(AT32F415)
+# if WS2812_SPI_DIVISOR == 2
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (0)
+# elif WS2812_SPI_DIVISOR == 4
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_0)
+# elif WS2812_SPI_DIVISOR == 8
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_1)
+# elif WS2812_SPI_DIVISOR == 16 // default
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0)
+# elif WS2812_SPI_DIVISOR == 32
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2)
+# elif WS2812_SPI_DIVISOR == 64
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_0)
+# elif WS2812_SPI_DIVISOR == 128
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1)
+# elif WS2812_SPI_DIVISOR == 256
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0)
+# elif WS2812_SPI_DIVISOR == 512
+# define WS2812_SPI_DIVISOR_CTRL2_MDIV_X (SPI_CTRL1_MDIV_3)
+# elif WS2812_SPI_DIVISOR == 1024
+# define WS2812_SPI_DIVISOR_CTRL2_MDIV_X (SPI_CTRL1_MDIV_3)
+# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_0)
+# else
+# error "Configured WS2812_SPI_DIVISOR value is not supported at this time."
+# endif
+#else
// F072 fpclk = 48MHz
// 48/16 = 3Mhz
-#if WS2812_SPI_DIVISOR == 2
-# define WS2812_SPI_DIVISOR_CR1_BR_X (0)
-#elif WS2812_SPI_DIVISOR == 4
-# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_0)
-#elif WS2812_SPI_DIVISOR == 8
-# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1)
-#elif WS2812_SPI_DIVISOR == 16 // default
-# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#elif WS2812_SPI_DIVISOR == 32
-# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2)
-#elif WS2812_SPI_DIVISOR == 64
-# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#elif WS2812_SPI_DIVISOR == 128
-# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#elif WS2812_SPI_DIVISOR == 256
-# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#else
-# error "Configured WS2812_SPI_DIVISOR value is not supported at this time."
+# if WS2812_SPI_DIVISOR == 2
+# define WS2812_SPI_DIVISOR_CR1_BR_X (0)
+# elif WS2812_SPI_DIVISOR == 4
+# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_0)
+# elif WS2812_SPI_DIVISOR == 8
+# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1)
+# elif WS2812_SPI_DIVISOR == 16 // default
+# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+# elif WS2812_SPI_DIVISOR == 32
+# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2)
+# elif WS2812_SPI_DIVISOR == 64
+# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+# elif WS2812_SPI_DIVISOR == 128
+# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+# elif WS2812_SPI_DIVISOR == 256
+# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
+# else
+# error "Configured WS2812_SPI_DIVISOR value is not supported at this time."
+# endif
#endif
// Use SPI circular buffer
@@ -106,7 +133,7 @@ static uint8_t get_protocol_eq(uint8_t data, int pos) {
return eq;
}
-static void set_led_color_rgb(rgb_led_t color, int pos) {
+static void set_led_color_rgb(ws2812_led_t color, int pos) {
uint8_t* tx_start = &txbuf[PREAMBLE_SIZE];
#if (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_GRB)
@@ -137,6 +164,8 @@ static void set_led_color_rgb(rgb_led_t color, int pos) {
#endif
}
+ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
+
void ws2812_init(void) {
palSetLineMode(WS2812_DI_PIN, WS2812_MOSI_OUTPUT_MODE);
@@ -174,8 +203,16 @@ void ws2812_init(void) {
NULL, // error_cb
PAL_PORT(WS2812_DI_PIN),
PAL_PAD(WS2812_DI_PIN),
+# if defined(AT32F415)
+ WS2812_SPI_DIVISOR_CTRL1_MDIV_X,
+# if (WS2812_SPI_DIVISOR == 512 || WS2812_SPI_DIVISOR == 1024)
+ WS2812_SPI_DIVISOR_CTRL2_MDIV_X,
+# endif
+ 0
+# else
WS2812_SPI_DIVISOR_CR1_BR_X,
0
+# endif
#endif
};
@@ -187,9 +224,24 @@ void ws2812_init(void) {
#endif
}
-void ws2812_setleds(rgb_led_t* ledarray, uint16_t leds) {
- for (uint8_t i = 0; i < leds; i++) {
- set_led_color_rgb(ledarray[i], i);
+void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
+ ws2812_leds[index].r = red;
+ ws2812_leds[index].g = green;
+ ws2812_leds[index].b = blue;
+#if defined(WS2812_RGBW)
+ ws2812_rgb_to_rgbw(&ws2812_leds[index]);
+#endif
+}
+
+void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+ ws2812_set_color(i, red, green, blue);
+ }
+}
+
+void ws2812_flush(void) {
+ for (int i = 0; i < WS2812_LED_COUNT; i++) {
+ set_led_color_rgb(ws2812_leds[i], i);
}
// Send async - each led takes ~0.03ms, 50 leds ~1.5ms, animations flushing faster than send will cause issues.
diff --git a/platforms/chibios/flash.mk b/platforms/chibios/flash.mk
index 525f177f9ebb..f4db17a58bf9 100644
--- a/platforms/chibios/flash.mk
+++ b/platforms/chibios/flash.mk
@@ -113,6 +113,8 @@ else ifeq ($(strip $(MCU_FAMILY)),STM32)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
else ifeq ($(strip $(MCU_FAMILY)),WB32)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_WB32_DFU_UPDATER)
+else ifeq ($(strip $(MCU_FAMILY)),AT32)
+ $(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
else ifeq ($(strip $(MCU_FAMILY)),GD32V)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
else
diff --git a/platforms/chibios/mcu_selection.mk b/platforms/chibios/mcu_selection.mk
index a1597fa1e912..086a2b31c60b 100644
--- a/platforms/chibios/mcu_selection.mk
+++ b/platforms/chibios/mcu_selection.mk
@@ -809,6 +809,40 @@ ifneq ($(findstring WB32FQ95, $(MCU)),)
WB32_BOOTLOADER_ADDRESS ?= 0x1FFFE000
endif
+ifneq ($(findstring AT32F415, $(MCU)),)
+ # Cortex version
+ MCU = cortex-m4
+
+ # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
+ ARMV = 7
+
+ ## chip/board settings
+ # - the next two should match the directories in
+ # /os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)
+ # OR
+ # /os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
+ MCU_FAMILY = AT32
+ MCU_SERIES = AT32F415
+
+ # Linker script to use
+ # - it should exist either in /os/common/startup/ARMCMx/compilers/GCC/ld/
+ # or /ld/
+ MCU_LDSCRIPT ?= AT32F415xB
+
+ # Startup code to use
+ # - it should exist in /os/common/startup/ARMCMx/compilers/GCC/mk/
+ MCU_STARTUP ?= at32f415
+
+ # Board: it should exist either in /os/hal/boards/,
+ # /boards/, or drivers/boards/
+ BOARD ?= GENERIC_AT32_F415XX
+
+ USE_FPU ?= no
+
+ # Bootloader address for AT32 DFU
+ AT32_BOOTLOADER_ADDRESS ?= 0x1FFFAC00
+endif
+
ifneq ($(findstring GD32VF103, $(MCU)),)
# RISC-V
MCU = risc-v
diff --git a/platforms/chibios/platform.mk b/platforms/chibios/platform.mk
index 169707966ff8..cf9fac251e45 100644
--- a/platforms/chibios/platform.mk
+++ b/platforms/chibios/platform.mk
@@ -155,6 +155,10 @@ ifdef WB32_BOOTLOADER_ADDRESS
OPT_DEFS += -DWB32_BOOTLOADER_ADDRESS=$(WB32_BOOTLOADER_ADDRESS)
endif
+ifdef AT32_BOOTLOADER_ADDRESS
+ OPT_DEFS += -DAT32_BOOTLOADER_ADDRESS=$(AT32_BOOTLOADER_ADDRESS)
+endif
+
# Work out if we need to set up the include for the bootloader definitions
ifneq ("$(wildcard $(KEYBOARD_PATH_5)/bootloader_defs.h)","")
OPT_DEFS += -include $(KEYBOARD_PATH_5)/bootloader_defs.h
diff --git a/platforms/chibios/timer.c b/platforms/chibios/timer.c
index 5e01ea637245..4a347b445d83 100644
--- a/platforms/chibios/timer.c
+++ b/platforms/chibios/timer.c
@@ -5,6 +5,7 @@
static uint32_t ticks_offset = 0;
static uint32_t last_ticks = 0;
static uint32_t ms_offset = 0;
+static uint32_t saved_ms = 0;
#if CH_CFG_ST_RESOLUTION < 32
static uint32_t last_systime = 0;
static uint32_t overflow = 0;
@@ -73,6 +74,26 @@ void timer_clear(void) {
chSysUnlock();
}
+__attribute__((weak)) void platform_timer_save_value(uint32_t value) {
+ saved_ms = value;
+}
+
+__attribute__((weak)) uint32_t platform_timer_restore_value(void) {
+ return saved_ms;
+}
+
+void timer_restore(void) {
+ chSysLock();
+ ticks_offset = get_system_time_ticks();
+ last_ticks = 0;
+ ms_offset = platform_timer_restore_value();
+ chSysUnlock();
+}
+
+void timer_save(void) {
+ platform_timer_save_value(timer_read32());
+}
+
uint16_t timer_read(void) {
return (uint16_t)timer_read32();
}
diff --git a/platforms/timer.h b/platforms/timer.h
index d55f40f0b0b1..fb8ff6bc5454 100644
--- a/platforms/timer.h
+++ b/platforms/timer.h
@@ -38,6 +38,8 @@ extern volatile uint32_t timer_count;
void timer_init(void);
void timer_clear(void);
+void timer_save(void);
+void timer_restore(void);
uint16_t timer_read(void);
uint32_t timer_read32(void);
uint16_t timer_elapsed(uint16_t last);
diff --git a/quantum/action_util.c b/quantum/action_util.c
index 52171b50508a..c0dc4f38228e 100644
--- a/quantum/action_util.c
+++ b/quantum/action_util.c
@@ -21,6 +21,7 @@ along with this program. If not, see .
#include "action_layer.h"
#include "timer.h"
#include "keycode_config.h"
+#include "usb_device_state.h"
#include
extern keymap_config_t keymap_config;
@@ -318,7 +319,7 @@ void send_nkro_report(void) {
*/
void send_keyboard_report(void) {
#ifdef NKRO_ENABLE
- if (keyboard_protocol && keymap_config.nkro) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_REPORT && keymap_config.nkro) {
send_nkro_report();
} else {
send_6kro_report();
diff --git a/quantum/basic_profiling.h b/quantum/basic_profiling.h
index d371acd6f002..e0a88d49cfd4 100644
--- a/quantum/basic_profiling.h
+++ b/quantum/basic_profiling.h
@@ -25,8 +25,6 @@
# define TIMESTAMP_GETTER TCNT0
#elif defined(PROTOCOL_CHIBIOS)
# define TIMESTAMP_GETTER chSysGetRealtimeCounterX()
-#elif defined(PROTOCOL_ARM_ATSAM)
-# error arm_atsam not currently supported
#else
# error Unknown protocol in use
#endif
diff --git a/quantum/bits.h b/quantum/bits.h
new file mode 100644
index 000000000000..2f3c34376232
--- /dev/null
+++ b/quantum/bits.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#pragma once
+
+#include
+
+/* Remove these once we transitioned to C23 across all platfroms */
+#define UINT32_WIDTH 32
+#define UINT64_WIDTH 64
+
+/**
+ * @brief Mask for the little endian nth bit (0-31) in a 32-bit integer.
+ */
+#define BIT32(n) (UINT32_C(1) << (n))
+
+/**
+ * @brief Mask for the little endian nth bit (0-63) in a 64-bit integer.
+ */
+#define BIT64(n) (UINT64_C(1) << (n))
+
+/**
+ * @brief Create a contiguous 32-bit wide bitmask starting at bit position @l
+ * and ending at position @h. The range is inclusive, meaning GENMASK32(20, 10)
+ * gives us the 32-bit mask 0x001ffc00.
+ */
+#define GENMASK32(h, l) (((~UINT32_C(0)) - (UINT32_C(1) << (l)) + 1) & (~UINT32_C(0) >> (UINT32_WIDTH - 1 - (h))))
+
+/**
+ * @brief Create a contiguous 64-bit wide bitmask starting at bit position @l
+ * and ending at position @h. The range is inclusive, meaning GENMASK64(39, 21)
+ * gives us the 64-bit mask 0x000000ffffe00000.
+ */
+#define GENMASK64(h, l) (((~UINT64_C(0)) - (UINT64_C(1) << (l)) + 1) & (~UINT64_C(0) >> (UINT64_WIDTH - 1 - (h))))
diff --git a/quantum/color.c b/quantum/color.c
index 96d548a33cce..93564784f0d8 100644
--- a/quantum/color.c
+++ b/quantum/color.c
@@ -19,8 +19,8 @@
#include "progmem.h"
#include "util.h"
-RGB hsv_to_rgb_impl(HSV hsv, bool use_cie) {
- RGB rgb;
+rgb_t hsv_to_rgb_impl(hsv_t hsv, bool use_cie) {
+ rgb_t rgb;
uint8_t region, remainder, p, q, t;
uint16_t h, s, v;
@@ -97,7 +97,7 @@ RGB hsv_to_rgb_impl(HSV hsv, bool use_cie) {
return rgb;
}
-RGB hsv_to_rgb(HSV hsv) {
+rgb_t hsv_to_rgb(hsv_t hsv) {
#ifdef USE_CIE1931_CURVE
return hsv_to_rgb_impl(hsv, true);
#else
@@ -105,17 +105,6 @@ RGB hsv_to_rgb(HSV hsv) {
#endif
}
-RGB hsv_to_rgb_nocie(HSV hsv) {
+rgb_t hsv_to_rgb_nocie(hsv_t hsv) {
return hsv_to_rgb_impl(hsv, false);
}
-
-#ifdef WS2812_RGBW
-void convert_rgb_to_rgbw(rgb_led_t *led) {
- // Determine lowest value in all three colors, put that into
- // the white channel and then shift all colors by that amount
- led->w = MIN(led->r, MIN(led->g, led->b));
- led->r -= led->w;
- led->g -= led->w;
- led->b -= led->w;
-}
-#endif
diff --git a/quantum/color.h b/quantum/color.h
index b6a9dd0641c0..5c23b2533509 100644
--- a/quantum/color.h
+++ b/quantum/color.h
@@ -74,43 +74,24 @@
// clang-format on
-#define WS2812_BYTE_ORDER_RGB 0
-#define WS2812_BYTE_ORDER_GRB 1
-#define WS2812_BYTE_ORDER_BGR 2
-
-#ifndef WS2812_BYTE_ORDER
-# define WS2812_BYTE_ORDER WS2812_BYTE_ORDER_GRB
-#endif
-
-typedef struct PACKED rgb_led_t {
-#if (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_GRB)
- uint8_t g;
- uint8_t r;
- uint8_t b;
-#elif (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_RGB)
+typedef struct PACKED rgb_t {
uint8_t r;
uint8_t g;
uint8_t b;
-#elif (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_BGR)
- uint8_t b;
- uint8_t g;
- uint8_t r;
-#endif
-#ifdef WS2812_RGBW
- uint8_t w;
-#endif
-} rgb_led_t;
+} rgb_t;
-typedef rgb_led_t RGB;
+// DEPRECATED
+typedef rgb_t RGB;
+typedef rgb_t rgb_led_t;
-typedef struct PACKED HSV {
+typedef struct PACKED hsv_t {
uint8_t h;
uint8_t s;
uint8_t v;
-} HSV;
+} hsv_t;
+
+// DEPRECATED
+typedef hsv_t HSV;
-RGB hsv_to_rgb(HSV hsv);
-RGB hsv_to_rgb_nocie(HSV hsv);
-#ifdef WS2812_RGBW
-void convert_rgb_to_rgbw(rgb_led_t *led);
-#endif
+rgb_t hsv_to_rgb(hsv_t hsv);
+rgb_t hsv_to_rgb_nocie(hsv_t hsv);
diff --git a/quantum/command.c b/quantum/command.c
index c188638eb40f..024d96917d7d 100644
--- a/quantum/command.c
+++ b/quantum/command.c
@@ -32,6 +32,7 @@ along with this program. If not, see .
#include "led.h"
#include "command.h"
#include "quantum.h"
+#include "usb_device_state.h"
#include "version.h"
#ifdef BACKLIGHT_ENABLE
@@ -230,8 +231,8 @@ static void print_status(void) {
"timer_read32(): %08lX\n"
, host_keyboard_leds()
- , keyboard_protocol
- , keyboard_idle
+ , usb_device_state_get_protocol()
+ , usb_device_state_get_idle_rate()
#ifdef NKRO_ENABLE
, keymap_config.nkro
#endif
diff --git a/quantum/eeconfig.c b/quantum/eeconfig.c
index ffbbf43a95c6..e27f604f1242 100644
--- a/quantum/eeconfig.c
+++ b/quantum/eeconfig.c
@@ -3,7 +3,6 @@
#include
#include "eeprom.h"
#include "eeconfig.h"
-#include "action_layer.h"
#if defined(EEPROM_DRIVER)
# include "eeprom_driver.h"
@@ -52,7 +51,7 @@ void eeconfig_init_quantum(void) {
eeprom_update_word(EECONFIG_MAGIC, EECONFIG_MAGIC_NUMBER);
eeprom_update_byte(EECONFIG_DEBUG, 0);
default_layer_state = (layer_state_t)1 << 0;
- eeprom_update_byte(EECONFIG_DEFAULT_LAYER, default_layer_state);
+ eeconfig_update_default_layer(default_layer_state);
// Enable oneshot and autocorrect by default: 0b0001 0100 0000 0000
eeprom_update_word(EECONFIG_KEYMAP, 0x1400);
eeprom_update_byte(EECONFIG_BACKLIGHT, 0);
@@ -160,14 +159,30 @@ void eeconfig_update_debug(uint8_t val) {
*
* FIXME: needs doc
*/
-uint8_t eeconfig_read_default_layer(void) {
- return eeprom_read_byte(EECONFIG_DEFAULT_LAYER);
+layer_state_t eeconfig_read_default_layer(void) {
+ uint8_t val = eeprom_read_byte(EECONFIG_DEFAULT_LAYER);
+
+#ifdef DEFAULT_LAYER_STATE_IS_VALUE_NOT_BITMASK
+ // stored as a layer number, so convert back to bitmask
+ return 1 << val;
+#else
+ // stored as 8-bit-wide bitmask, so read the value directly - handling padding to 16/32 bit layer_state_t
+ return val;
+#endif
}
/** \brief eeconfig update default layer
*
* FIXME: needs doc
*/
-void eeconfig_update_default_layer(uint8_t val) {
+void eeconfig_update_default_layer(layer_state_t state) {
+#ifdef DEFAULT_LAYER_STATE_IS_VALUE_NOT_BITMASK
+ // stored as a layer number, so only store the highest layer
+ uint8_t val = get_highest_layer(state);
+#else
+ // stored as 8-bit-wide bitmask, so write the value directly - handling truncation from 16/32 bit layer_state_t
+ uint8_t val = state;
+#endif
+
eeprom_update_byte(EECONFIG_DEFAULT_LAYER, val);
}
diff --git a/quantum/eeconfig.h b/quantum/eeconfig.h
index fa0dd799d195..11cf1ccbca8b 100644
--- a/quantum/eeconfig.h
+++ b/quantum/eeconfig.h
@@ -22,6 +22,7 @@ along with this program. If not, see .
#include // offsetof
#include "eeprom.h"
#include "util.h"
+#include "action_layer.h" // layer_state_t
#ifndef EECONFIG_MAGIC_NUMBER
# define EECONFIG_MAGIC_NUMBER (uint16_t)0xFEE5 // When changing, decrement this value to avoid future re-init issues
@@ -122,8 +123,8 @@ void eeconfig_disable(void);
uint8_t eeconfig_read_debug(void);
void eeconfig_update_debug(uint8_t val);
-uint8_t eeconfig_read_default_layer(void);
-void eeconfig_update_default_layer(uint8_t val);
+layer_state_t eeconfig_read_default_layer(void);
+void eeconfig_update_default_layer(layer_state_t val);
uint16_t eeconfig_read_keymap(void);
void eeconfig_update_keymap(uint16_t val);
diff --git a/quantum/haptic.c b/quantum/haptic.c
index 6a466293a745..81bad469b37f 100644
--- a/quantum/haptic.c
+++ b/quantum/haptic.c
@@ -36,7 +36,7 @@ extern uint8_t split_haptic_play;
haptic_config_t haptic_config;
static void update_haptic_enable_gpios(void) {
- if (haptic_config.enable && ((!HAPTIC_OFF_IN_LOW_POWER) || (usb_device_state == USB_DEVICE_STATE_CONFIGURED))) {
+ if (haptic_config.enable && ((!HAPTIC_OFF_IN_LOW_POWER) || (usb_device_state_get_configure_state() == USB_DEVICE_STATE_CONFIGURED))) {
#if defined(HAPTIC_ENABLE_PIN)
HAPTIC_ENABLE_PIN_WRITE_ACTIVE();
#endif
diff --git a/quantum/joystick.c b/quantum/joystick.c
index 32f19b2cd99d..62893fd1997a 100644
--- a/quantum/joystick.c
+++ b/quantum/joystick.c
@@ -29,6 +29,9 @@ joystick_t joystick_state = {
0
#endif
},
+#ifdef JOYSTICK_HAS_HAT
+ .hat = -1,
+#endif
.dirty = false,
};
@@ -145,6 +148,13 @@ void joystick_set_axis(uint8_t axis, int16_t value) {
}
}
+#ifdef JOYSTICK_HAS_HAT
+void joystick_set_hat(int8_t value) {
+ joystick_state.hat = value;
+ joystick_state.dirty = true;
+}
+#endif
+
void joystick_init(void) {
joystick_init_axes();
}
diff --git a/quantum/joystick.h b/quantum/joystick.h
index 5a69ceac64a9..24f80c1ad6f6 100644
--- a/quantum/joystick.h
+++ b/quantum/joystick.h
@@ -52,6 +52,16 @@
#define JOYSTICK_MAX_VALUE ((1L << (JOYSTICK_AXIS_RESOLUTION - 1)) - 1)
+#define JOYSTICK_HAT_CENTER -1
+#define JOYSTICK_HAT_NORTH 0
+#define JOYSTICK_HAT_NORTHEAST 1
+#define JOYSTICK_HAT_EAST 2
+#define JOYSTICK_HAT_SOUTHEAST 3
+#define JOYSTICK_HAT_SOUTH 4
+#define JOYSTICK_HAT_SOUTHWEST 5
+#define JOYSTICK_HAT_WEST 6
+#define JOYSTICK_HAT_NORTHWEST 7
+
// configure on input_pin of the joystick_axes array entry to NO_PIN
// to prevent it from being read from the ADC. This allows outputting forged axis value.
#define JOYSTICK_AXIS_VIRTUAL \
@@ -73,7 +83,10 @@ extern joystick_config_t joystick_axes[JOYSTICK_AXIS_COUNT];
typedef struct {
uint8_t buttons[(JOYSTICK_BUTTON_COUNT - 1) / 8 + 1];
int16_t axes[JOYSTICK_AXIS_COUNT];
- bool dirty;
+#ifdef JOYSTICK_HAS_HAT
+ int8_t hat;
+#endif
+ bool dirty;
} joystick_t;
extern joystick_t joystick_state;
@@ -129,4 +142,11 @@ void joystick_read_axes(void);
*/
void joystick_set_axis(uint8_t axis, int16_t value);
+/**
+ * \brief Set the position of the hat switch.
+ *
+ * \param value The hat switch position to set.
+ */
+void joystick_set_hat(int8_t value);
+
/** \} */
diff --git a/quantum/keyboard.c b/quantum/keyboard.c
index df1dc1c3ee09..d7836cf36e00 100644
--- a/quantum/keyboard.c
+++ b/quantum/keyboard.c
@@ -140,6 +140,9 @@ along with this program. If not, see .
#ifdef OS_DETECTION_ENABLE
# include "os_detection.h"
#endif
+#ifdef LAYER_LOCK_ENABLE
+# include "layer_lock.h"
+#endif
static uint32_t last_input_modification_time = 0;
uint32_t last_input_activity_time(void) {
@@ -655,6 +658,10 @@ void quantum_task(void) {
#ifdef SECURE_ENABLE
secure_task();
#endif
+
+#ifdef LAYER_LOCK_ENABLE
+ layer_lock_task();
+#endif
}
/** \brief Main task that is repeatedly called as fast as possible. */
diff --git a/quantum/keycodes.h b/quantum/keycodes.h
index f461e4a586e2..921dc7199f26 100644
--- a/quantum/keycodes.h
+++ b/quantum/keycodes.h
@@ -52,6 +52,8 @@ enum qk_keycode_ranges {
QK_ONE_SHOT_MOD_MAX = 0x52BF,
QK_LAYER_TAP_TOGGLE = 0x52C0,
QK_LAYER_TAP_TOGGLE_MAX = 0x52DF,
+ QK_PERSISTENT_DEF_LAYER = 0x52E0,
+ QK_PERSISTENT_DEF_LAYER_MAX = 0x52FF,
QK_SWAP_HANDS = 0x5600,
QK_SWAP_HANDS_MAX = 0x56FF,
QK_TAP_DANCE = 0x5700,
@@ -72,6 +74,8 @@ enum qk_keycode_ranges {
QK_STENO_MAX = 0x74FF,
QK_MACRO = 0x7700,
QK_MACRO_MAX = 0x777F,
+ QK_CONNECTION = 0x7780,
+ QK_CONNECTION_MAX = 0x77BF,
QK_LIGHTING = 0x7800,
QK_LIGHTING_MAX = 0x78FF,
QK_QUANTUM = 0x7C00,
@@ -620,6 +624,21 @@ enum qk_keycode_defines {
QK_MACRO_29 = 0x771D,
QK_MACRO_30 = 0x771E,
QK_MACRO_31 = 0x771F,
+ QK_OUTPUT_AUTO = 0x7780,
+ QK_OUTPUT_NEXT = 0x7781,
+ QK_OUTPUT_PREV = 0x7782,
+ QK_OUTPUT_NONE = 0x7783,
+ QK_OUTPUT_USB = 0x7784,
+ QK_OUTPUT_2P4GHZ = 0x7785,
+ QK_OUTPUT_BLUETOOTH = 0x7786,
+ QK_BLUETOOTH_PROFILE_NEXT = 0x7790,
+ QK_BLUETOOTH_PROFILE_PREV = 0x7791,
+ QK_BLUETOOTH_UNPAIR = 0x7792,
+ QK_BLUETOOTH_PROFILE1 = 0x7793,
+ QK_BLUETOOTH_PROFILE2 = 0x7794,
+ QK_BLUETOOTH_PROFILE3 = 0x7795,
+ QK_BLUETOOTH_PROFILE4 = 0x7796,
+ QK_BLUETOOTH_PROFILE5 = 0x7797,
QK_BACKLIGHT_ON = 0x7800,
QK_BACKLIGHT_OFF = 0x7801,
QK_BACKLIGHT_TOGGLE = 0x7802,
@@ -690,9 +709,6 @@ enum qk_keycode_defines {
QK_SPACE_CADET_LEFT_ALT_PARENTHESIS_OPEN = 0x7C1C,
QK_SPACE_CADET_RIGHT_ALT_PARENTHESIS_CLOSE = 0x7C1D,
QK_SPACE_CADET_RIGHT_SHIFT_ENTER = 0x7C1E,
- QK_OUTPUT_AUTO = 0x7C20,
- QK_OUTPUT_USB = 0x7C21,
- QK_OUTPUT_BLUETOOTH = 0x7C22,
QK_UNICODE_MODE_NEXT = 0x7C30,
QK_UNICODE_MODE_PREVIOUS = 0x7C31,
QK_UNICODE_MODE_MACOS = 0x7C32,
@@ -745,6 +761,7 @@ enum qk_keycode_defines {
QK_TRI_LAYER_UPPER = 0x7C78,
QK_REPEAT_KEY = 0x7C79,
QK_ALT_REPEAT_KEY = 0x7C7A,
+ QK_LAYER_LOCK = 0x7C7B,
QK_KB_0 = 0x7E00,
QK_KB_1 = 0x7E01,
QK_KB_2 = 0x7E02,
@@ -1296,6 +1313,21 @@ enum qk_keycode_defines {
MC_29 = QK_MACRO_29,
MC_30 = QK_MACRO_30,
MC_31 = QK_MACRO_31,
+ OU_AUTO = QK_OUTPUT_AUTO,
+ OU_NEXT = QK_OUTPUT_NEXT,
+ OU_PREV = QK_OUTPUT_PREV,
+ OU_NONE = QK_OUTPUT_NONE,
+ OU_USB = QK_OUTPUT_USB,
+ OU_2P4G = QK_OUTPUT_2P4GHZ,
+ OU_BT = QK_OUTPUT_BLUETOOTH,
+ BT_NEXT = QK_BLUETOOTH_PROFILE_NEXT,
+ BT_PREV = QK_BLUETOOTH_PROFILE_PREV,
+ BT_UNPR = QK_BLUETOOTH_UNPAIR,
+ BT_PRF1 = QK_BLUETOOTH_PROFILE1,
+ BT_PRF2 = QK_BLUETOOTH_PROFILE2,
+ BT_PRF3 = QK_BLUETOOTH_PROFILE3,
+ BT_PRF4 = QK_BLUETOOTH_PROFILE4,
+ BT_PRF5 = QK_BLUETOOTH_PROFILE5,
BL_ON = QK_BACKLIGHT_ON,
BL_OFF = QK_BACKLIGHT_OFF,
BL_TOGG = QK_BACKLIGHT_TOGGLE,
@@ -1365,9 +1397,6 @@ enum qk_keycode_defines {
SC_LAPO = QK_SPACE_CADET_LEFT_ALT_PARENTHESIS_OPEN,
SC_RAPC = QK_SPACE_CADET_RIGHT_ALT_PARENTHESIS_CLOSE,
SC_SENT = QK_SPACE_CADET_RIGHT_SHIFT_ENTER,
- OU_AUTO = QK_OUTPUT_AUTO,
- OU_USB = QK_OUTPUT_USB,
- OU_BT = QK_OUTPUT_BLUETOOTH,
UC_NEXT = QK_UNICODE_MODE_NEXT,
UC_PREV = QK_UNICODE_MODE_PREVIOUS,
UC_MAC = QK_UNICODE_MODE_MACOS,
@@ -1419,6 +1448,7 @@ enum qk_keycode_defines {
TL_UPPR = QK_TRI_LAYER_UPPER,
QK_REP = QK_REPEAT_KEY,
QK_AREP = QK_ALT_REPEAT_KEY,
+ QK_LLCK = QK_LAYER_LOCK,
};
// Range Helpers
@@ -1434,6 +1464,7 @@ enum qk_keycode_defines {
#define IS_QK_ONE_SHOT_LAYER(code) ((code) >= QK_ONE_SHOT_LAYER && (code) <= QK_ONE_SHOT_LAYER_MAX)
#define IS_QK_ONE_SHOT_MOD(code) ((code) >= QK_ONE_SHOT_MOD && (code) <= QK_ONE_SHOT_MOD_MAX)
#define IS_QK_LAYER_TAP_TOGGLE(code) ((code) >= QK_LAYER_TAP_TOGGLE && (code) <= QK_LAYER_TAP_TOGGLE_MAX)
+#define IS_QK_PERSISTENT_DEF_LAYER(code) ((code) >= QK_PERSISTENT_DEF_LAYER && (code) <= QK_PERSISTENT_DEF_LAYER_MAX)
#define IS_QK_SWAP_HANDS(code) ((code) >= QK_SWAP_HANDS && (code) <= QK_SWAP_HANDS_MAX)
#define IS_QK_TAP_DANCE(code) ((code) >= QK_TAP_DANCE && (code) <= QK_TAP_DANCE_MAX)
#define IS_QK_MAGIC(code) ((code) >= QK_MAGIC && (code) <= QK_MAGIC_MAX)
@@ -1444,6 +1475,7 @@ enum qk_keycode_defines {
#define IS_QK_AUDIO(code) ((code) >= QK_AUDIO && (code) <= QK_AUDIO_MAX)
#define IS_QK_STENO(code) ((code) >= QK_STENO && (code) <= QK_STENO_MAX)
#define IS_QK_MACRO(code) ((code) >= QK_MACRO && (code) <= QK_MACRO_MAX)
+#define IS_QK_CONNECTION(code) ((code) >= QK_CONNECTION && (code) <= QK_CONNECTION_MAX)
#define IS_QK_LIGHTING(code) ((code) >= QK_LIGHTING && (code) <= QK_LIGHTING_MAX)
#define IS_QK_QUANTUM(code) ((code) >= QK_QUANTUM && (code) <= QK_QUANTUM_MAX)
#define IS_QK_KB(code) ((code) >= QK_KB && (code) <= QK_KB_MAX)
@@ -1468,12 +1500,13 @@ enum qk_keycode_defines {
#define IS_AUDIO_KEYCODE(code) ((code) >= QK_AUDIO_ON && (code) <= QK_AUDIO_VOICE_PREVIOUS)
#define IS_STENO_KEYCODE(code) ((code) >= QK_STENO_BOLT && (code) <= QK_STENO_COMB_MAX)
#define IS_MACRO_KEYCODE(code) ((code) >= QK_MACRO_0 && (code) <= QK_MACRO_31)
+#define IS_CONNECTION_KEYCODE(code) ((code) >= QK_OUTPUT_AUTO && (code) <= QK_BLUETOOTH_PROFILE5)
#define IS_BACKLIGHT_KEYCODE(code) ((code) >= QK_BACKLIGHT_ON && (code) <= QK_BACKLIGHT_TOGGLE_BREATHING)
#define IS_LED_MATRIX_KEYCODE(code) ((code) >= QK_LED_MATRIX_ON && (code) <= QK_LED_MATRIX_SPEED_DOWN)
#define IS_UNDERGLOW_KEYCODE(code) ((code) >= QK_UNDERGLOW_TOGGLE && (code) <= QK_UNDERGLOW_SPEED_DOWN)
#define IS_RGB_KEYCODE(code) ((code) >= RGB_MODE_PLAIN && (code) <= RGB_MODE_TWINKLE)
#define IS_RGB_MATRIX_KEYCODE(code) ((code) >= QK_RGB_MATRIX_ON && (code) <= QK_RGB_MATRIX_SPEED_DOWN)
-#define IS_QUANTUM_KEYCODE(code) ((code) >= QK_BOOTLOADER && (code) <= QK_ALT_REPEAT_KEY)
+#define IS_QUANTUM_KEYCODE(code) ((code) >= QK_BOOTLOADER && (code) <= QK_LAYER_LOCK)
#define IS_KB_KEYCODE(code) ((code) >= QK_KB_0 && (code) <= QK_KB_31)
#define IS_USER_KEYCODE(code) ((code) >= QK_USER_0 && (code) <= QK_USER_31)
@@ -1493,11 +1526,12 @@ enum qk_keycode_defines {
#define AUDIO_KEYCODE_RANGE QK_AUDIO_ON ... QK_AUDIO_VOICE_PREVIOUS
#define STENO_KEYCODE_RANGE QK_STENO_BOLT ... QK_STENO_COMB_MAX
#define MACRO_KEYCODE_RANGE QK_MACRO_0 ... QK_MACRO_31
+#define CONNECTION_KEYCODE_RANGE QK_OUTPUT_AUTO ... QK_BLUETOOTH_PROFILE5
#define BACKLIGHT_KEYCODE_RANGE QK_BACKLIGHT_ON ... QK_BACKLIGHT_TOGGLE_BREATHING
#define LED_MATRIX_KEYCODE_RANGE QK_LED_MATRIX_ON ... QK_LED_MATRIX_SPEED_DOWN
#define UNDERGLOW_KEYCODE_RANGE QK_UNDERGLOW_TOGGLE ... QK_UNDERGLOW_SPEED_DOWN
#define RGB_KEYCODE_RANGE RGB_MODE_PLAIN ... RGB_MODE_TWINKLE
#define RGB_MATRIX_KEYCODE_RANGE QK_RGB_MATRIX_ON ... QK_RGB_MATRIX_SPEED_DOWN
-#define QUANTUM_KEYCODE_RANGE QK_BOOTLOADER ... QK_ALT_REPEAT_KEY
+#define QUANTUM_KEYCODE_RANGE QK_BOOTLOADER ... QK_LAYER_LOCK
#define KB_KEYCODE_RANGE QK_KB_0 ... QK_KB_31
#define USER_KEYCODE_RANGE QK_USER_0 ... QK_USER_31
diff --git a/quantum/layer_lock.c b/quantum/layer_lock.c
new file mode 100644
index 000000000000..9fc84bcfca18
--- /dev/null
+++ b/quantum/layer_lock.c
@@ -0,0 +1,100 @@
+// Copyright 2022-2023 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "layer_lock.h"
+#include "quantum_keycodes.h"
+
+#ifndef NO_ACTION_LAYER
+// The current lock state. The kth bit is on if layer k is locked.
+layer_state_t locked_layers = 0;
+
+// Layer Lock timer to disable layer lock after X seconds inactivity
+# if defined(LAYER_LOCK_IDLE_TIMEOUT) && LAYER_LOCK_IDLE_TIMEOUT > 0
+uint32_t layer_lock_timer = 0;
+
+void layer_lock_timeout_task(void) {
+ if (locked_layers && timer_elapsed32(layer_lock_timer) > LAYER_LOCK_IDLE_TIMEOUT) {
+ layer_lock_all_off();
+ layer_lock_timer = timer_read32();
+ }
+}
+void layer_lock_activity_trigger(void) {
+ layer_lock_timer = timer_read32();
+}
+# else
+void layer_lock_timeout_task(void) {}
+void layer_lock_activity_trigger(void) {}
+# endif // LAYER_LOCK_IDLE_TIMEOUT > 0
+
+bool is_layer_locked(uint8_t layer) {
+ return locked_layers & ((layer_state_t)1 << layer);
+}
+
+void layer_lock_invert(uint8_t layer) {
+ const layer_state_t mask = (layer_state_t)1 << layer;
+ if ((locked_layers & mask) == 0) { // Layer is being locked.
+# ifndef NO_ACTION_ONESHOT
+ if (layer == get_oneshot_layer()) {
+ reset_oneshot_layer(); // Reset so that OSL doesn't turn layer off.
+ }
+# endif // NO_ACTION_ONESHOT
+ layer_on(layer);
+ layer_lock_activity_trigger();
+ } else { // Layer is being unlocked.
+ layer_off(layer);
+ }
+ layer_lock_set_kb(locked_layers ^= mask);
+}
+
+// Implement layer_lock_on/off by deferring to layer_lock_invert.
+void layer_lock_on(uint8_t layer) {
+ if (!is_layer_locked(layer)) {
+ layer_lock_invert(layer);
+ }
+}
+
+void layer_lock_off(uint8_t layer) {
+ if (is_layer_locked(layer)) {
+ layer_lock_invert(layer);
+ }
+}
+
+void layer_lock_all_off(void) {
+ layer_and(~locked_layers);
+ locked_layers = 0;
+ layer_lock_set_kb(locked_layers);
+}
+
+#else // NO_ACTION_LAYER
+bool is_layer_locked(uint8_t layer) {
+ return false;
+}
+void layer_lock_on(uint8_t layer) {}
+void layer_lock_off(uint8_t layer) {}
+void layer_lock_all_off(void) {}
+void layer_lock_invert(uint8_t layer) {}
+void layer_lock_timeout_task(void) {}
+void layer_lock_activity_trigger(void) {}
+#endif // NO_ACTION_LAYER
+
+__attribute__((weak)) bool layer_lock_set_kb(layer_state_t locked_layers) {
+ return layer_lock_set_user(locked_layers);
+}
+__attribute__((weak)) bool layer_lock_set_user(layer_state_t locked_layers) {
+ return true;
+}
+
+void layer_lock_task(void) {
+ layer_lock_timeout_task();
+}
diff --git a/quantum/layer_lock.h b/quantum/layer_lock.h
new file mode 100644
index 000000000000..97f6c60d70d1
--- /dev/null
+++ b/quantum/layer_lock.h
@@ -0,0 +1,98 @@
+// Copyright 2022-2023 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @file layer_lock.h
+ * @brief Layer Lock, a key to stay in the current layer.
+ *
+ * Overview
+ * --------
+ *
+ * Layers are often accessed by holding a button, e.g. with a momentary layer
+ * switch `MO(layer)` or layer tap `LT(layer, key)` key. But you may sometimes
+ * want to "lock" or "toggle" the layer so that it stays on without having to
+ * hold down a button. One way to do that is with a tap-toggle `TT` layer key,
+ * but here is an alternative.
+ *
+ * This library implements a "Layer Lock key". When tapped, it "locks" the
+ * highest layer to stay active, assuming the layer was activated by one of the
+ * following keys:
+ *
+ * * `MO(layer)` momentary layer switch
+ * * `LT(layer, key)` layer tap
+ * * `OSL(layer)` one-shot layer
+ * * `TT(layer)` layer tap toggle
+ * * `LM(layer, mod)` layer-mod key (the layer is locked, but not the mods)
+ *
+ * Tapping the Layer Lock key again unlocks and turns off the layer.
+ *
+ * @note When a layer is "locked", other layer keys such as `TO(layer)` or
+ * manually calling `layer_off(layer)` will override and unlock the layer.
+ *
+ * Configuration
+ * -------------
+ *
+ * Optionally, a timeout may be defined so that Layer Lock disables
+ * automatically if not keys are pressed for `LAYER_LOCK_IDLE_TIMEOUT`
+ * milliseconds. Define `LAYER_LOCK_IDLE_TIMEOUT` in your config.h, for instance
+ *
+ * #define LAYER_LOCK_IDLE_TIMEOUT 60000 // Turn off after 60 seconds.
+ *
+ * For full documentation, see
+ *
+ */
+
+#pragma once
+
+#include
+#include
+#include "action_layer.h"
+#include "action_util.h"
+
+/** Returns true if `layer` is currently locked. */
+bool is_layer_locked(uint8_t layer);
+
+/** Locks and turns on `layer`. */
+void layer_lock_on(uint8_t layer);
+
+/** Unlocks and turns off `layer`. */
+void layer_lock_off(uint8_t layer);
+
+/** Unlocks and turns off all locked layers. */
+void layer_lock_all_off(void);
+
+/** Toggles whether `layer` is locked. */
+void layer_lock_invert(uint8_t layer);
+
+/**
+ * Optional callback that gets called when a layer is locked or unlocked.
+ *
+ * This is useful to represent the current lock state, e.g. by setting an LED or
+ * playing a sound. In your keymap, define
+ *
+ * void layer_lock_set_user(layer_state_t locked_layers) {
+ * // Do something like `set_led(is_layer_locked(NAV));`
+ * }
+ *
+ * @param locked_layers Bitfield in which the kth bit represents whether the
+ * kth layer is on.
+ */
+bool layer_lock_set_kb(layer_state_t locked_layers);
+bool layer_lock_set_user(layer_state_t locked_layers);
+
+/** Handle various background tasks */
+void layer_lock_task(void);
+
+/** Update any configured timeouts */
+void layer_lock_activity_trigger(void);
diff --git a/quantum/led_matrix/animations/breathing_anim.h b/quantum/led_matrix/animations/breathing_anim.h
index 0bd4cb0cc388..3d1b0d95d218 100644
--- a/quantum/led_matrix/animations/breathing_anim.h
+++ b/quantum/led_matrix/animations/breathing_anim.h
@@ -2,17 +2,12 @@
LED_MATRIX_EFFECT(BREATHING)
# ifdef LED_MATRIX_CUSTOM_EFFECT_IMPLS
-bool BREATHING(effect_params_t* params) {
- LED_MATRIX_USE_LIMITS(led_min, led_max);
+static uint8_t BREATHING_math(uint8_t val, uint8_t i, uint8_t time) {
+ return scale8(abs8(sin8(time / 2) - 128) * 2, val);
+}
- uint8_t val = led_matrix_eeconfig.val;
- uint16_t time = scale16by8(g_led_timer, led_matrix_eeconfig.speed / 8);
- val = scale8(abs8(sin8(time) - 128) * 2, val);
- for (uint8_t i = led_min; i < led_max; i++) {
- LED_MATRIX_TEST_LED_FLAGS();
- led_matrix_set_value(i, val);
- }
- return led_matrix_check_finished_leds(led_max);
+bool BREATHING(effect_params_t* params) {
+ return effect_runner_i(params, &BREATHING_math);
}
# endif // LED_MATRIX_CUSTOM_EFFECT_IMPLS
diff --git a/quantum/led_matrix/led_matrix.c b/quantum/led_matrix/led_matrix.c
index 798ab9a120e3..58263c62e37b 100644
--- a/quantum/led_matrix/led_matrix.c
+++ b/quantum/led_matrix/led_matrix.c
@@ -139,11 +139,20 @@ void led_matrix_update_pwm_buffers(void) {
led_matrix_driver.flush();
}
+__attribute__((weak)) int led_matrix_led_index(int index) {
+#if defined(LED_MATRIX_SPLIT)
+ if (!is_keyboard_left() && index >= k_led_matrix_split[0]) {
+ return index - k_led_matrix_split[0];
+ }
+#endif
+ return index;
+}
+
void led_matrix_set_value(int index, uint8_t value) {
#ifdef USE_CIE1931_CURVE
value = pgm_read_byte(&CIE1931_CURVE[value]);
#endif
- led_matrix_driver.set_value(index, value);
+ led_matrix_driver.set_value(led_matrix_led_index(index), value);
}
void led_matrix_set_value_all(uint8_t value) {
@@ -387,7 +396,6 @@ struct led_matrix_limits_t led_matrix_get_limits(uint8_t iter) {
limits.led_min_index = LED_MATRIX_LED_PROCESS_LIMIT * (iter);
limits.led_max_index = limits.led_min_index + LED_MATRIX_LED_PROCESS_LIMIT;
if (limits.led_max_index > LED_MATRIX_LED_COUNT) limits.led_max_index = LED_MATRIX_LED_COUNT;
- uint8_t k_led_matrix_split[2] = LED_MATRIX_SPLIT;
if (is_keyboard_left() && (limits.led_max_index > k_led_matrix_split[0])) limits.led_max_index = k_led_matrix_split[0];
if (!(is_keyboard_left()) && (limits.led_min_index < k_led_matrix_split[0])) limits.led_min_index = k_led_matrix_split[0];
# else
@@ -397,9 +405,8 @@ struct led_matrix_limits_t led_matrix_get_limits(uint8_t iter) {
# endif
#else
# if defined(LED_MATRIX_SPLIT)
- limits.led_min_index = 0;
- limits.led_max_index = LED_MATRIX_LED_COUNT;
- const uint8_t k_led_matrix_split[2] = LED_MATRIX_SPLIT;
+ limits.led_min_index = 0;
+ limits.led_max_index = LED_MATRIX_LED_COUNT;
if (is_keyboard_left() && (limits.led_max_index > k_led_matrix_split[0])) limits.led_max_index = k_led_matrix_split[0];
if (!(is_keyboard_left()) && (limits.led_min_index < k_led_matrix_split[0])) limits.led_min_index = k_led_matrix_split[0];
# else
diff --git a/quantum/led_matrix/led_matrix.h b/quantum/led_matrix/led_matrix.h
index 9a13c3e52b46..a3468a200394 100644
--- a/quantum/led_matrix/led_matrix.h
+++ b/quantum/led_matrix/led_matrix.h
@@ -121,6 +121,8 @@ void eeconfig_debug_led_matrix(void);
uint8_t led_matrix_map_row_column_to_led_kb(uint8_t row, uint8_t column, uint8_t *led_i);
uint8_t led_matrix_map_row_column_to_led(uint8_t row, uint8_t column, uint8_t *led_i);
+int led_matrix_led_index(int index);
+
void led_matrix_set_value(int index, uint8_t value);
void led_matrix_set_value_all(uint8_t value);
diff --git a/quantum/logging/debug.h b/quantum/logging/debug.h
index d0590474c045..b0d9b9a10ed4 100644
--- a/quantum/logging/debug.h
+++ b/quantum/logging/debug.h
@@ -17,10 +17,7 @@ along with this program. If not, see .
#pragma once
-#ifndef PROTOCOL_ARM_ATSAM
-# include
-#endif
-
+#include
#include
#include "print.h"
diff --git a/quantum/os_detection.c b/quantum/os_detection.c
index 96b026e2471c..0dd048a8c472 100644
--- a/quantum/os_detection.c
+++ b/quantum/os_detection.c
@@ -34,7 +34,7 @@ static uint16_t usb_setups[STORED_USB_SETUPS];
#endif
#ifndef OS_DETECTION_DEBOUNCE
-# define OS_DETECTION_DEBOUNCE 200
+# define OS_DETECTION_DEBOUNCE 250
#endif
// 2s should always be more than enough (otherwise, you may have other issues)
@@ -59,25 +59,40 @@ struct setups_data_t setups_data = {
};
static volatile os_variant_t detected_os = OS_UNSURE;
-static os_variant_t reported_os = OS_UNSURE;
+static volatile os_variant_t reported_os = OS_UNSURE;
// we need to be able to report OS_UNSURE if that is the stable result of the guesses
-static bool first_report = true;
+static volatile bool first_report = true;
// to react on USB state changes
-static volatile enum usb_device_state current_usb_device_state = USB_DEVICE_STATE_INIT;
-static enum usb_device_state reported_usb_device_state = USB_DEVICE_STATE_INIT;
+static volatile struct usb_device_state current_usb_device_state = {.configure_state = USB_DEVICE_STATE_NO_INIT};
+static volatile struct usb_device_state maxprev_usb_device_state = {.configure_state = USB_DEVICE_STATE_NO_INIT};
// the OS detection might be unstable for a while, "debounce" it
static volatile bool debouncing = false;
-static volatile fast_timer_t last_time;
+static volatile fast_timer_t last_time = 0;
void os_detection_task(void) {
- if (current_usb_device_state == USB_DEVICE_STATE_CONFIGURED) {
+#ifdef OS_DETECTION_KEYBOARD_RESET
+ // resetting the keyboard on the USB device state change callback results in instability, so delegate that to this task
+ // only take action if it's been stable at least once, to avoid issues with some KVMs
+ if (current_usb_device_state.configure_state <= USB_DEVICE_STATE_INIT && maxprev_usb_device_state.configure_state >= USB_DEVICE_STATE_CONFIGURED) {
+ if (debouncing && timer_elapsed_fast(last_time) >= OS_DETECTION_DEBOUNCE) {
+ soft_reset_keyboard();
+ }
+ return;
+ }
+#endif
+#ifdef OS_DETECTION_SINGLE_REPORT
+ if (!first_report) {
+ return;
+ }
+#endif
+ if (current_usb_device_state.configure_state == USB_DEVICE_STATE_CONFIGURED) {
// debouncing goes for both the detected OS as well as the USB state
if (debouncing && timer_elapsed_fast(last_time) >= OS_DETECTION_DEBOUNCE) {
- debouncing = false;
- reported_usb_device_state = current_usb_device_state;
+ debouncing = false;
+ last_time = 0;
if (detected_os != reported_os || first_report) {
first_report = false;
reported_os = detected_os;
@@ -85,13 +100,6 @@ void os_detection_task(void) {
}
}
}
-#ifdef OS_DETECTION_KEYBOARD_RESET
- // resetting the keyboard on the USB device state change callback results in instability, so delegate that to this task
- // only take action if it's been stable at least once, to avoid issues with some KVMs
- else if (current_usb_device_state == USB_DEVICE_STATE_INIT && reported_usb_device_state != USB_DEVICE_STATE_INIT) {
- soft_reset_keyboard();
- }
-#endif
}
__attribute__((weak)) bool process_detected_host_os_kb(os_variant_t detected_os) {
@@ -155,16 +163,20 @@ os_variant_t detected_host_os(void) {
void erase_wlength_data(void) {
memset(&setups_data, 0, sizeof(setups_data));
- detected_os = OS_UNSURE;
- reported_os = OS_UNSURE;
- current_usb_device_state = USB_DEVICE_STATE_INIT;
- reported_usb_device_state = USB_DEVICE_STATE_INIT;
- debouncing = false;
- first_report = true;
+ detected_os = OS_UNSURE;
+ reported_os = OS_UNSURE;
+ current_usb_device_state.configure_state = USB_DEVICE_STATE_NO_INIT;
+ maxprev_usb_device_state.configure_state = USB_DEVICE_STATE_NO_INIT;
+ debouncing = false;
+ last_time = 0;
+ first_report = true;
}
-void os_detection_notify_usb_device_state_change(enum usb_device_state usb_device_state) {
+void os_detection_notify_usb_device_state_change(struct usb_device_state usb_device_state) {
// treat this like any other source of instability
+ if (maxprev_usb_device_state.configure_state < current_usb_device_state.configure_state) {
+ maxprev_usb_device_state.configure_state = current_usb_device_state.configure_state;
+ }
current_usb_device_state = usb_device_state;
last_time = timer_read_fast();
debouncing = true;
diff --git a/quantum/os_detection.h b/quantum/os_detection.h
index b8cd89833595..98a8e805e4cf 100644
--- a/quantum/os_detection.h
+++ b/quantum/os_detection.h
@@ -31,7 +31,7 @@ typedef enum {
void process_wlength(const uint16_t w_length);
os_variant_t detected_host_os(void);
void erase_wlength_data(void);
-void os_detection_notify_usb_device_state_change(enum usb_device_state usb_device_state);
+void os_detection_notify_usb_device_state_change(struct usb_device_state usb_device_state);
void os_detection_task(void);
diff --git a/quantum/os_detection/tests/os_detection.cpp b/quantum/os_detection/tests/os_detection.cpp
index a9f671156b83..ea43de144c3a 100644
--- a/quantum/os_detection/tests/os_detection.cpp
+++ b/quantum/os_detection/tests/os_detection.cpp
@@ -253,9 +253,11 @@ TEST_F(OsDetectionTest, TestDoNotReportIfUsbUnstable) {
EXPECT_EQ(detected_host_os(), OS_LINUX);
}
+static struct usb_device_state usb_device_state_configured = {.configure_state = USB_DEVICE_STATE_CONFIGURED};
+
TEST_F(OsDetectionTest, TestReportAfterDebounce) {
EXPECT_EQ(check_sequence({0xFF, 0xFF, 0xFF, 0xFE}), OS_LINUX);
- os_detection_notify_usb_device_state_change(USB_DEVICE_STATE_CONFIGURED);
+ os_detection_notify_usb_device_state_change(usb_device_state_configured);
os_detection_task();
assert_not_reported();
@@ -291,7 +293,7 @@ TEST_F(OsDetectionTest, TestReportAfterDebounce) {
TEST_F(OsDetectionTest, TestReportAfterDebounceLongWait) {
EXPECT_EQ(check_sequence({0x12, 0xFF, 0xFF, 0x4, 0x10, 0xFF, 0xFF, 0xFF, 0x4, 0x10, 0x20A, 0x20A, 0x20A, 0x20A, 0x20A, 0x20A}), OS_WINDOWS);
- os_detection_notify_usb_device_state_change(USB_DEVICE_STATE_CONFIGURED);
+ os_detection_notify_usb_device_state_change(usb_device_state_configured);
os_detection_task();
assert_not_reported();
@@ -318,7 +320,7 @@ TEST_F(OsDetectionTest, TestReportAfterDebounceLongWait) {
TEST_F(OsDetectionTest, TestReportUnsure) {
EXPECT_EQ(check_sequence({0x12, 0xFF}), OS_UNSURE);
- os_detection_notify_usb_device_state_change(USB_DEVICE_STATE_CONFIGURED);
+ os_detection_notify_usb_device_state_change(usb_device_state_configured);
os_detection_task();
assert_not_reported();
@@ -345,7 +347,7 @@ TEST_F(OsDetectionTest, TestReportUnsure) {
TEST_F(OsDetectionTest, TestDoNotReportIntermediateResults) {
EXPECT_EQ(check_sequence({0x12, 0xFF}), OS_UNSURE);
- os_detection_notify_usb_device_state_change(USB_DEVICE_STATE_CONFIGURED);
+ os_detection_notify_usb_device_state_change(usb_device_state_configured);
os_detection_task();
assert_not_reported();
@@ -356,7 +358,7 @@ TEST_F(OsDetectionTest, TestDoNotReportIntermediateResults) {
// at this stage, the final result has not been reached yet
EXPECT_EQ(check_sequence({0xFF}), OS_LINUX);
- os_detection_notify_usb_device_state_change(USB_DEVICE_STATE_CONFIGURED);
+ os_detection_notify_usb_device_state_change(usb_device_state_configured);
advance_time(OS_DETECTION_DEBOUNCE - 1);
os_detection_task();
assert_not_reported();
@@ -365,7 +367,7 @@ TEST_F(OsDetectionTest, TestDoNotReportIntermediateResults) {
// the remainder is processed
EXPECT_EQ(check_sequence({0x4, 0x10, 0xFF, 0xFF, 0xFF, 0x4, 0x10, 0x20A, 0x20A, 0x20A, 0x20A, 0x20A, 0x20A}), OS_WINDOWS);
- os_detection_notify_usb_device_state_change(USB_DEVICE_STATE_CONFIGURED);
+ os_detection_notify_usb_device_state_change(usb_device_state_configured);
advance_time(OS_DETECTION_DEBOUNCE - 1);
os_detection_task();
assert_not_reported();
diff --git a/quantum/painter/qp.h b/quantum/painter/qp.h
index 820c418f43b7..3dc77b42cfb5 100644
--- a/quantum/painter/qp.h
+++ b/quantum/painter/qp.h
@@ -557,6 +557,12 @@ int16_t qp_drawtext_recolor(painter_device_t device, uint16_t x, uint16_t y, pai
# define SH1106_NUM_DEVICES 0
#endif // QUANTUM_PAINTER_SH1106_ENABLE
+#ifdef QUANTUM_PAINTER_LD7032_ENABLE
+# include "qp_ld7032.h"
+#else // QUANTUM_PAINTER_LD7032_ENABLE
+# define LD7032_NUM_DEVICES 0
+#endif // QUANTUM_PAINTER_LD7032_ENABLE
+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Quantum Painter Extras
diff --git a/quantum/painter/qp_internal.c b/quantum/painter/qp_internal.c
index 7d4a6430afe0..5097edfa0747 100644
--- a/quantum/painter/qp_internal.c
+++ b/quantum/painter/qp_internal.c
@@ -19,6 +19,7 @@ enum {
+ (GC9107_NUM_DEVICES) // GC9107
+ (SSD1351_NUM_DEVICES) // SSD1351
+ (SH1106_NUM_DEVICES) // SH1106
+ + (LD7032_NUM_DEVICES) // LD7032
};
static painter_device_t qp_devices[QP_NUM_DEVICES] = {NULL};
diff --git a/quantum/painter/rules.mk b/quantum/painter/rules.mk
index 7b2ab702ee11..b773dd091c30 100644
--- a/quantum/painter/rules.mk
+++ b/quantum/painter/rules.mk
@@ -17,7 +17,9 @@ VALID_QUANTUM_PAINTER_DRIVERS := \
gc9107_spi \
ssd1351_spi \
sh1106_i2c \
- sh1106_spi
+ sh1106_spi \
+ ld7032_i2c \
+ ld7032_spi
#-------------------------------------------------------------------------------
@@ -182,6 +184,29 @@ define handle_quantum_painter_driver
$(DRIVER_PATH)/painter/oled_panel/qp_oled_panel.c \
$(DRIVER_PATH)/painter/sh1106/qp_sh1106.c
+ else ifeq ($$(strip $$(CURRENT_PAINTER_DRIVER)),ld7032_spi)
+ QUANTUM_PAINTER_NEEDS_SURFACE := yes
+ QUANTUM_PAINTER_NEEDS_COMMS_SPI := yes
+ QUANTUM_PAINTER_NEEDS_COMMS_SPI_DC_RESET := yes
+ OPT_DEFS += -DQUANTUM_PAINTER_LD7032_ENABLE -DQUANTUM_PAINTER_LD7032_SPI_ENABLE
+ COMMON_VPATH += \
+ $(DRIVER_PATH)/painter/oled_panel \
+ $(DRIVER_PATH)/painter/ld7032
+ SRC += \
+ $(DRIVER_PATH)/painter/oled_panel/qp_oled_panel.c \
+ $(DRIVER_PATH)/painter/ld7032/qp_ld7032.c
+
+ else ifeq ($$(strip $$(CURRENT_PAINTER_DRIVER)),ld7032_i2c)
+ QUANTUM_PAINTER_NEEDS_SURFACE := yes
+ QUANTUM_PAINTER_NEEDS_COMMS_I2C := yes
+ OPT_DEFS += -DQUANTUM_PAINTER_LD7032_ENABLE -DQUANTUM_PAINTER_LD7032_I2C_ENABLE
+ COMMON_VPATH += \
+ $(DRIVER_PATH)/painter/oled_panel \
+ $(DRIVER_PATH)/painter/ld7032
+ SRC += \
+ $(DRIVER_PATH)/painter/oled_panel/qp_oled_panel.c \
+ $(DRIVER_PATH)/painter/ld7032/qp_ld7032.c
+
endif
endef
diff --git a/quantum/pointing_device/pointing_device.c b/quantum/pointing_device/pointing_device.c
index 74ce9108a9cf..cac2875fc8d4 100644
--- a/quantum/pointing_device/pointing_device.c
+++ b/quantum/pointing_device/pointing_device.c
@@ -79,7 +79,28 @@ uint16_t pointing_device_get_shared_cpi(void) {
static report_mouse_t local_mouse_report = {};
static bool pointing_device_force_send = false;
-extern const pointing_device_driver_t pointing_device_driver;
+#define POINTING_DEVICE_DRIVER_CONCAT(name) name##_pointing_device_driver
+#define POINTING_DEVICE_DRIVER(name) POINTING_DEVICE_DRIVER_CONCAT(name)
+
+#ifdef POINTING_DEVICE_DRIVER_custom
+__attribute__((weak)) void pointing_device_driver_init(void) {}
+__attribute__((weak)) report_mouse_t pointing_device_driver_get_report(report_mouse_t mouse_report) {
+ return mouse_report;
+}
+__attribute__((weak)) uint16_t pointing_device_driver_get_cpi(void) {
+ return 0;
+}
+__attribute__((weak)) void pointing_device_driver_set_cpi(uint16_t cpi) {}
+
+const pointing_device_driver_t custom_pointing_device_driver = {
+ .init = pointing_device_driver_init,
+ .get_report = pointing_device_driver_get_report,
+ .get_cpi = pointing_device_driver_get_cpi,
+ .set_cpi = pointing_device_driver_set_cpi,
+};
+#endif
+
+const pointing_device_driver_t *pointing_device_driver = &POINTING_DEVICE_DRIVER(POINTING_DEVICE_DRIVER_NAME);
/**
* @brief Keyboard level code pointing device initialisation
@@ -146,7 +167,7 @@ __attribute__((weak)) void pointing_device_init(void) {
if ((POINTING_DEVICE_THIS_SIDE))
#endif
{
- pointing_device_driver.init();
+ pointing_device_driver->init();
#ifdef POINTING_DEVICE_MOTION_PIN
# ifdef POINTING_DEVICE_MOTION_PIN_ACTIVE_LOW
gpio_set_pin_input_high(POINTING_DEVICE_MOTION_PIN);
@@ -258,15 +279,15 @@ __attribute__((weak)) bool pointing_device_task(void) {
# if defined(POINTING_DEVICE_COMBINED)
static uint8_t old_buttons = 0;
local_mouse_report.buttons = old_buttons;
- local_mouse_report = pointing_device_driver.get_report(local_mouse_report);
+ local_mouse_report = pointing_device_driver->get_report(local_mouse_report);
old_buttons = local_mouse_report.buttons;
# elif defined(POINTING_DEVICE_LEFT) || defined(POINTING_DEVICE_RIGHT)
- local_mouse_report = POINTING_DEVICE_THIS_SIDE ? pointing_device_driver.get_report(local_mouse_report) : shared_mouse_report;
+ local_mouse_report = POINTING_DEVICE_THIS_SIDE ? pointing_device_driver->get_report(local_mouse_report) : shared_mouse_report;
# else
# error "You need to define the side(s) the pointing device is on. POINTING_DEVICE_COMBINED / POINTING_DEVICE_LEFT / POINTING_DEVICE_RIGHT"
# endif
#else
- local_mouse_report = pointing_device_driver.get_report(local_mouse_report);
+ local_mouse_report = pointing_device_driver->get_report(local_mouse_report);
#endif // defined(SPLIT_POINTING_ENABLE)
#ifdef POINTING_DEVICE_MOTION_PIN
@@ -331,9 +352,9 @@ void pointing_device_set_report(report_mouse_t mouse_report) {
*/
uint16_t pointing_device_get_cpi(void) {
#if defined(SPLIT_POINTING_ENABLE)
- return POINTING_DEVICE_THIS_SIDE ? pointing_device_driver.get_cpi() : shared_cpi;
+ return POINTING_DEVICE_THIS_SIDE ? pointing_device_driver->get_cpi() : shared_cpi;
#else
- return pointing_device_driver.get_cpi();
+ return pointing_device_driver->get_cpi();
#endif
}
@@ -347,12 +368,12 @@ uint16_t pointing_device_get_cpi(void) {
void pointing_device_set_cpi(uint16_t cpi) {
#if defined(SPLIT_POINTING_ENABLE)
if (POINTING_DEVICE_THIS_SIDE) {
- pointing_device_driver.set_cpi(cpi);
+ pointing_device_driver->set_cpi(cpi);
} else {
shared_cpi = cpi;
}
#else
- pointing_device_driver.set_cpi(cpi);
+ pointing_device_driver->set_cpi(cpi);
#endif
}
@@ -370,35 +391,35 @@ void pointing_device_set_cpi(uint16_t cpi) {
void pointing_device_set_cpi_on_side(bool left, uint16_t cpi) {
bool local = (is_keyboard_left() == left);
if (local) {
- pointing_device_driver.set_cpi(cpi);
+ pointing_device_driver->set_cpi(cpi);
} else {
shared_cpi = cpi;
}
}
/**
- * @brief clamps int16_t to int8_t
+ * @brief clamps int16_t to int8_t, or int32_t to int16_t
*
- * @param[in] int16_t value
- * @return int8_t clamped value
+ * @param[in] hv_clamp_range_t value
+ * @return mouse_hv_report_t clamped value
*/
-static inline int8_t pointing_device_hv_clamp(int16_t value) {
- if (value < INT8_MIN) {
- return INT8_MIN;
- } else if (value > INT8_MAX) {
- return INT8_MAX;
+static inline mouse_hv_report_t pointing_device_hv_clamp(hv_clamp_range_t value) {
+ if (value < HV_REPORT_MIN) {
+ return HV_REPORT_MIN;
+ } else if (value > HV_REPORT_MAX) {
+ return HV_REPORT_MAX;
} else {
return value;
}
}
/**
- * @brief clamps int16_t to int8_t
+ * @brief clamps int16_t to int8_t, or int32_t to int16_t
*
- * @param[in] clamp_range_t value
+ * @param[in] xy_clamp_range_t value
* @return mouse_xy_report_t clamped value
*/
-static inline mouse_xy_report_t pointing_device_xy_clamp(clamp_range_t value) {
+static inline mouse_xy_report_t pointing_device_xy_clamp(xy_clamp_range_t value) {
if (value < XY_REPORT_MIN) {
return XY_REPORT_MIN;
} else if (value > XY_REPORT_MAX) {
@@ -419,10 +440,10 @@ static inline mouse_xy_report_t pointing_device_xy_clamp(clamp_range_t value) {
* @return combined report_mouse_t of left_report and right_report
*/
report_mouse_t pointing_device_combine_reports(report_mouse_t left_report, report_mouse_t right_report) {
- left_report.x = pointing_device_xy_clamp((clamp_range_t)left_report.x + right_report.x);
- left_report.y = pointing_device_xy_clamp((clamp_range_t)left_report.y + right_report.y);
- left_report.h = pointing_device_hv_clamp((int16_t)left_report.h + right_report.h);
- left_report.v = pointing_device_hv_clamp((int16_t)left_report.v + right_report.v);
+ left_report.x = pointing_device_xy_clamp((xy_clamp_range_t)left_report.x + right_report.x);
+ left_report.y = pointing_device_xy_clamp((xy_clamp_range_t)left_report.y + right_report.y);
+ left_report.h = pointing_device_hv_clamp((hv_clamp_range_t)left_report.h + right_report.h);
+ left_report.v = pointing_device_hv_clamp((hv_clamp_range_t)left_report.v + right_report.v);
left_report.buttons |= right_report.buttons;
return left_report;
}
diff --git a/quantum/pointing_device/pointing_device.h b/quantum/pointing_device/pointing_device.h
index 1cd4b0b5e60d..72188c977dd1 100644
--- a/quantum/pointing_device/pointing_device.h
+++ b/quantum/pointing_device/pointing_device.h
@@ -21,6 +21,13 @@ along with this program. If not, see .
#include "host.h"
#include "report.h"
+typedef struct {
+ void (*init)(void);
+ report_mouse_t (*get_report)(report_mouse_t mouse_report);
+ void (*set_cpi)(uint16_t);
+ uint16_t (*get_cpi)(void);
+} pointing_device_driver_t;
+
#ifdef POINTING_DEVICE_AUTO_MOUSE_ENABLE
# include "pointing_device_auto_mouse.h"
#endif
@@ -44,7 +51,6 @@ along with this program. If not, see .
# include "drivers/sensors/azoteq_iqs5xx.h"
#elif defined(POINTING_DEVICE_DRIVER_cirque_pinnacle_i2c) || defined(POINTING_DEVICE_DRIVER_cirque_pinnacle_spi)
# include "drivers/sensors/cirque_pinnacle.h"
-# include "drivers/sensors/cirque_pinnacle_gestures.h"
# include "pointing_device_gestures.h"
#elif defined(POINTING_DEVICE_DRIVER_paw3204)
# include "drivers/sensors/paw3204.h"
@@ -74,13 +80,6 @@ uint16_t pointing_device_driver_get_cpi(void);
void pointing_device_driver_set_cpi(uint16_t cpi);
#endif
-typedef struct {
- void (*init)(void);
- report_mouse_t (*get_report)(report_mouse_t mouse_report);
- void (*set_cpi)(uint16_t);
- uint16_t (*get_cpi)(void);
-} pointing_device_driver_t;
-
typedef enum {
POINTING_DEVICE_BUTTON1,
POINTING_DEVICE_BUTTON2,
@@ -95,13 +94,26 @@ typedef enum {
#ifdef MOUSE_EXTENDED_REPORT
# define XY_REPORT_MIN INT16_MIN
# define XY_REPORT_MAX INT16_MAX
-typedef int32_t clamp_range_t;
+typedef int32_t xy_clamp_range_t;
#else
# define XY_REPORT_MIN INT8_MIN
# define XY_REPORT_MAX INT8_MAX
-typedef int16_t clamp_range_t;
+typedef int16_t xy_clamp_range_t;
#endif
+#ifdef WHEEL_EXTENDED_REPORT
+# define HV_REPORT_MIN INT16_MIN
+# define HV_REPORT_MAX INT16_MAX
+typedef int32_t hv_clamp_range_t;
+#else
+# define HV_REPORT_MIN INT8_MIN
+# define HV_REPORT_MAX INT8_MAX
+typedef int16_t hv_clamp_range_t;
+#endif
+
+#define CONSTRAIN_HID(amt) ((amt) < INT8_MIN ? INT8_MIN : ((amt) > INT8_MAX ? INT8_MAX : (amt)))
+#define CONSTRAIN_HID_XY(amt) ((amt) < XY_REPORT_MIN ? XY_REPORT_MIN : ((amt) > XY_REPORT_MAX ? XY_REPORT_MAX : (amt)))
+
void pointing_device_init(void);
bool pointing_device_task(void);
bool pointing_device_send(void);
diff --git a/quantum/pointing_device/pointing_device_auto_mouse.c b/quantum/pointing_device/pointing_device_auto_mouse.c
index d9f924e258e3..250351f6088d 100644
--- a/quantum/pointing_device/pointing_device_auto_mouse.c
+++ b/quantum/pointing_device/pointing_device_auto_mouse.c
@@ -357,6 +357,8 @@ bool process_auto_mouse(uint16_t keycode, keyrecord_t* record) {
}
// DF ---------------------------------------------------------------------------------------------------------
case QK_DEF_LAYER ... QK_DEF_LAYER_MAX:
+ // PDF --------------------------------------------------------------------------------------------------------
+ case QK_PERSISTENT_DEF_LAYER ... QK_PERSISTENT_DEF_LAYER_MAX:
# ifndef NO_ACTION_ONESHOT
// OSL((AUTO_MOUSE_TARGET_LAYER))------------------------------------------------------------------------------
case QK_ONE_SHOT_LAYER ... QK_ONE_SHOT_LAYER_MAX:
diff --git a/quantum/pointing_device/pointing_device_drivers.c b/quantum/pointing_device/pointing_device_drivers.c
deleted file mode 100644
index bf131c6eda51..000000000000
--- a/quantum/pointing_device/pointing_device_drivers.c
+++ /dev/null
@@ -1,514 +0,0 @@
-/* Copyright 2017 Joshua Broekhuijsen
- * Copyright 2020 Christopher Courtney, aka Drashna Jael're (@drashna)
- * Copyright 2021 Dasky (@daskygit)
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-
-#include "pointing_device.h"
-#include "pointing_device_internal.h"
-#include "debug.h"
-#include "wait.h"
-#include "timer.h"
-#include
-
-#define CONSTRAIN_HID(amt) ((amt) < INT8_MIN ? INT8_MIN : ((amt) > INT8_MAX ? INT8_MAX : (amt)))
-#define CONSTRAIN_HID_XY(amt) ((amt) < XY_REPORT_MIN ? XY_REPORT_MIN : ((amt) > XY_REPORT_MAX ? XY_REPORT_MAX : (amt)))
-
-// get_report functions should probably be moved to their respective drivers.
-
-#if defined(POINTING_DEVICE_DRIVER_adns5050)
-report_mouse_t adns5050_get_report(report_mouse_t mouse_report) {
- report_adns5050_t data = adns5050_read_burst();
-
- if (data.dx != 0 || data.dy != 0) {
- pd_dprintf("Raw ] X: %d, Y: %d\n", data.dx, data.dy);
- mouse_report.x = (mouse_xy_report_t)data.dx;
- mouse_report.y = (mouse_xy_report_t)data.dy;
- }
-
- return mouse_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = adns5050_init,
- .get_report = adns5050_get_report,
- .set_cpi = adns5050_set_cpi,
- .get_cpi = adns5050_get_cpi,
-};
-// clang-format on
-
-#elif defined(POINTING_DEVICE_DRIVER_pmw3320)
-report_mouse_t pmw3320_get_report(report_mouse_t mouse_report) {
- report_pmw3320_t data = pmw3320_read_burst();
-
- if (data.dx != 0 || data.dy != 0) {
- pd_dprintf("Raw ] X: %d, Y: %d\n", data.dx, data.dy);
- mouse_report.x = (mouse_xy_report_t)data.dx;
- mouse_report.y = (mouse_xy_report_t)data.dy;
- }
-
- return mouse_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = pmw3320_init,
- .get_report = pmw3320_get_report,
- .set_cpi = pmw3320_set_cpi,
- .get_cpi = pmw3320_get_cpi,
-};
-// clang-format on
-
-#elif defined(POINTING_DEVICE_DRIVER_adns9800)
-
-report_mouse_t adns9800_get_report_driver(report_mouse_t mouse_report) {
- report_adns9800_t sensor_report = adns9800_get_report();
-
- mouse_report.x = CONSTRAIN_HID_XY(sensor_report.x);
- mouse_report.y = CONSTRAIN_HID_XY(sensor_report.y);
-
- return mouse_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = adns9800_init,
- .get_report = adns9800_get_report_driver,
- .set_cpi = adns9800_set_cpi,
- .get_cpi = adns9800_get_cpi
-};
-// clang-format on
-
-#elif defined(POINTING_DEVICE_DRIVER_analog_joystick)
-report_mouse_t analog_joystick_get_report(report_mouse_t mouse_report) {
- report_analog_joystick_t data = analog_joystick_read();
-
- pd_dprintf("Raw ] X: %d, Y: %d\n", data.x, data.y);
-
- mouse_report.x = data.x;
- mouse_report.y = data.y;
-
- mouse_report.buttons = pointing_device_handle_buttons(mouse_report.buttons, data.button, POINTING_DEVICE_BUTTON1);
-
- return mouse_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = analog_joystick_init,
- .get_report = analog_joystick_get_report,
- .set_cpi = NULL,
- .get_cpi = NULL
-};
-// clang-format on
-
-#elif defined(POINTING_DEVICE_DRIVER_azoteq_iqs5xx)
-
-static i2c_status_t azoteq_iqs5xx_init_status = 1;
-
-void azoteq_iqs5xx_init(void) {
- i2c_init();
- azoteq_iqs5xx_wake();
- azoteq_iqs5xx_reset_suspend(true, false, true);
- wait_ms(100);
- azoteq_iqs5xx_wake();
- if (azoteq_iqs5xx_get_product() != AZOTEQ_IQS5XX_UNKNOWN) {
- azoteq_iqs5xx_setup_resolution();
- azoteq_iqs5xx_init_status = azoteq_iqs5xx_set_report_rate(AZOTEQ_IQS5XX_REPORT_RATE, AZOTEQ_IQS5XX_ACTIVE, false);
- azoteq_iqs5xx_init_status |= azoteq_iqs5xx_set_event_mode(false, false);
- azoteq_iqs5xx_init_status |= azoteq_iqs5xx_set_reati(true, false);
-# if defined(AZOTEQ_IQS5XX_ROTATION_90)
- azoteq_iqs5xx_init_status |= azoteq_iqs5xx_set_xy_config(false, true, true, true, false);
-# elif defined(AZOTEQ_IQS5XX_ROTATION_180)
- azoteq_iqs5xx_init_status |= azoteq_iqs5xx_set_xy_config(true, true, false, true, false);
-# elif defined(AZOTEQ_IQS5XX_ROTATION_270)
- azoteq_iqs5xx_init_status |= azoteq_iqs5xx_set_xy_config(true, false, true, true, false);
-# else
- azoteq_iqs5xx_init_status |= azoteq_iqs5xx_set_xy_config(false, false, false, true, false);
-# endif
- azoteq_iqs5xx_init_status |= azoteq_iqs5xx_set_gesture_config(true);
- wait_ms(AZOTEQ_IQS5XX_REPORT_RATE + 1);
- }
-};
-
-report_mouse_t azoteq_iqs5xx_get_report(report_mouse_t mouse_report) {
- report_mouse_t temp_report = {0};
- static uint8_t previous_button_state = 0;
- static uint8_t read_error_count = 0;
-
- if (azoteq_iqs5xx_init_status == I2C_STATUS_SUCCESS) {
- azoteq_iqs5xx_base_data_t base_data = {0};
-# if !defined(POINTING_DEVICE_MOTION_PIN)
- azoteq_iqs5xx_wake();
-# endif
- i2c_status_t status = azoteq_iqs5xx_get_base_data(&base_data);
- bool ignore_movement = false;
-
- if (status == I2C_STATUS_SUCCESS) {
- // pd_dprintf("IQS5XX - previous cycle time: %d \n", base_data.previous_cycle_time);
- read_error_count = 0;
- if (base_data.gesture_events_0.single_tap || base_data.gesture_events_0.press_and_hold) {
- pd_dprintf("IQS5XX - Single tap/hold.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON1);
- } else if (base_data.gesture_events_1.two_finger_tap) {
- pd_dprintf("IQS5XX - Two finger tap.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON2);
- } else if (base_data.gesture_events_0.swipe_x_neg) {
- pd_dprintf("IQS5XX - X-.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON4);
- ignore_movement = true;
- } else if (base_data.gesture_events_0.swipe_x_pos) {
- pd_dprintf("IQS5XX - X+.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON5);
- ignore_movement = true;
- } else if (base_data.gesture_events_0.swipe_y_neg) {
- pd_dprintf("IQS5XX - Y-.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON6);
- ignore_movement = true;
- } else if (base_data.gesture_events_0.swipe_y_pos) {
- pd_dprintf("IQS5XX - Y+.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON3);
- ignore_movement = true;
- } else if (base_data.gesture_events_1.zoom) {
- if (AZOTEQ_IQS5XX_COMBINE_H_L_BYTES(base_data.x.h, base_data.x.l) < 0) {
- pd_dprintf("IQS5XX - Zoom out.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON7);
- } else if (AZOTEQ_IQS5XX_COMBINE_H_L_BYTES(base_data.x.h, base_data.x.l) > 0) {
- pd_dprintf("IQS5XX - Zoom in.\n");
- temp_report.buttons = pointing_device_handle_buttons(temp_report.buttons, true, POINTING_DEVICE_BUTTON8);
- }
- } else if (base_data.gesture_events_1.scroll) {
- pd_dprintf("IQS5XX - Scroll.\n");
- temp_report.h = CONSTRAIN_HID(AZOTEQ_IQS5XX_COMBINE_H_L_BYTES(base_data.x.h, base_data.x.l));
- temp_report.v = CONSTRAIN_HID(AZOTEQ_IQS5XX_COMBINE_H_L_BYTES(base_data.y.h, base_data.y.l));
- }
- if (base_data.number_of_fingers == 1 && !ignore_movement) {
- temp_report.x = CONSTRAIN_HID_XY(AZOTEQ_IQS5XX_COMBINE_H_L_BYTES(base_data.x.h, base_data.x.l));
- temp_report.y = CONSTRAIN_HID_XY(AZOTEQ_IQS5XX_COMBINE_H_L_BYTES(base_data.y.h, base_data.y.l));
- }
-
- previous_button_state = temp_report.buttons;
-
- } else {
- if (read_error_count > 10) {
- read_error_count = 0;
- previous_button_state = 0;
- } else {
- read_error_count++;
- }
- temp_report.buttons = previous_button_state;
- pd_dprintf("IQS5XX - get report failed: %d \n", status);
- }
- } else {
- pd_dprintf("IQS5XX - Init failed: %d \n", azoteq_iqs5xx_init_status);
- }
-
- return temp_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = azoteq_iqs5xx_init,
- .get_report = azoteq_iqs5xx_get_report,
- .set_cpi = azoteq_iqs5xx_set_cpi,
- .get_cpi = azoteq_iqs5xx_get_cpi
-};
-// clang-format on
-
-#elif defined(POINTING_DEVICE_DRIVER_cirque_pinnacle_i2c) || defined(POINTING_DEVICE_DRIVER_cirque_pinnacle_spi)
-# ifdef POINTING_DEVICE_GESTURES_CURSOR_GLIDE_ENABLE
-static bool cursor_glide_enable = true;
-
-static cursor_glide_context_t glide = {.config = {
- .coef = 102, /* Good default friction coef */
- .interval = 10, /* 100sps */
- .trigger_px = 10, /* Default threshold in case of hover, set to 0 if you'd like */
- }};
-
-void cirque_pinnacle_enable_cursor_glide(bool enable) {
- cursor_glide_enable = enable;
-}
-
-void cirque_pinnacle_configure_cursor_glide(float trigger_px) {
- glide.config.trigger_px = trigger_px;
-}
-# endif
-
-# if CIRQUE_PINNACLE_POSITION_MODE
-
-# ifdef POINTING_DEVICE_AUTO_MOUSE_ENABLE
-static bool is_touch_down;
-
-bool auto_mouse_activation(report_mouse_t mouse_report) {
- return is_touch_down || mouse_report.x != 0 || mouse_report.y != 0 || mouse_report.h != 0 || mouse_report.v != 0 || mouse_report.buttons;
-}
-# endif
-
-report_mouse_t cirque_pinnacle_get_report(report_mouse_t mouse_report) {
- uint16_t scale = cirque_pinnacle_get_scale();
- pinnacle_data_t touchData = cirque_pinnacle_read_data();
- mouse_xy_report_t report_x = 0, report_y = 0;
- static uint16_t x = 0, y = 0, last_scale = 0;
-
-# if defined(CIRQUE_PINNACLE_TAP_ENABLE)
- mouse_report.buttons = pointing_device_handle_buttons(mouse_report.buttons, false, POINTING_DEVICE_BUTTON1);
-# endif
-# ifdef POINTING_DEVICE_GESTURES_CURSOR_GLIDE_ENABLE
- cursor_glide_t glide_report = {0};
-
- if (cursor_glide_enable) {
- glide_report = cursor_glide_check(&glide);
- }
-# endif
-
- if (!touchData.valid) {
-# ifdef POINTING_DEVICE_GESTURES_CURSOR_GLIDE_ENABLE
- if (cursor_glide_enable && glide_report.valid) {
- report_x = glide_report.dx;
- report_y = glide_report.dy;
- goto mouse_report_update;
- }
-# endif
- return mouse_report;
- }
-
- if (touchData.touchDown) {
- pd_dprintf("cirque_pinnacle touchData x=%4d y=%4d z=%2d\n", touchData.xValue, touchData.yValue, touchData.zValue);
- }
-
-# ifdef POINTING_DEVICE_AUTO_MOUSE_ENABLE
- is_touch_down = touchData.touchDown;
-# endif
-
- // Scale coordinates to arbitrary X, Y resolution
- cirque_pinnacle_scale_data(&touchData, scale, scale);
-
- if (!cirque_pinnacle_gestures(&mouse_report, touchData)) {
- if (last_scale && scale == last_scale && x && y && touchData.xValue && touchData.yValue) {
- report_x = CONSTRAIN_HID_XY((int16_t)(touchData.xValue - x));
- report_y = CONSTRAIN_HID_XY((int16_t)(touchData.yValue - y));
- }
- x = touchData.xValue;
- y = touchData.yValue;
- last_scale = scale;
-
-# ifdef POINTING_DEVICE_GESTURES_CURSOR_GLIDE_ENABLE
- if (cursor_glide_enable) {
- if (touchData.touchDown) {
- cursor_glide_update(&glide, report_x, report_y, touchData.zValue);
- } else if (!glide_report.valid) {
- glide_report = cursor_glide_start(&glide);
- if (glide_report.valid) {
- report_x = glide_report.dx;
- report_y = glide_report.dy;
- }
- }
- }
-# endif
- }
-
-# ifdef POINTING_DEVICE_GESTURES_CURSOR_GLIDE_ENABLE
-mouse_report_update:
-# endif
- mouse_report.x = report_x;
- mouse_report.y = report_y;
-
- return mouse_report;
-}
-
-uint16_t cirque_pinnacle_get_cpi(void) {
- return CIRQUE_PINNACLE_PX_TO_INCH(cirque_pinnacle_get_scale());
-}
-void cirque_pinnacle_set_cpi(uint16_t cpi) {
- cirque_pinnacle_set_scale(CIRQUE_PINNACLE_INCH_TO_PX(cpi));
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = cirque_pinnacle_init,
- .get_report = cirque_pinnacle_get_report,
- .set_cpi = cirque_pinnacle_set_cpi,
- .get_cpi = cirque_pinnacle_get_cpi
-};
-// clang-format on
-# else
-report_mouse_t cirque_pinnacle_get_report(report_mouse_t mouse_report) {
- pinnacle_data_t touchData = cirque_pinnacle_read_data();
-
- // Scale coordinates to arbitrary X, Y resolution
- cirque_pinnacle_scale_data(&touchData, cirque_pinnacle_get_scale(), cirque_pinnacle_get_scale());
-
- if (touchData.valid) {
- mouse_report.buttons = touchData.buttons;
- mouse_report.x = CONSTRAIN_HID_XY(touchData.xDelta);
- mouse_report.y = CONSTRAIN_HID_XY(touchData.yDelta);
- mouse_report.v = touchData.wheelCount;
- }
- return mouse_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = cirque_pinnacle_init,
- .get_report = cirque_pinnacle_get_report,
- .set_cpi = cirque_pinnacle_set_scale,
- .get_cpi = cirque_pinnacle_get_scale
-};
-// clang-format on
-# endif
-
-#elif defined(POINTING_DEVICE_DRIVER_paw3204)
-
-report_mouse_t paw3204_get_report(report_mouse_t mouse_report) {
- report_paw3204_t data = paw3204_read();
- if (data.isMotion) {
- pd_dprintf("Raw ] X: %d, Y: %d\n", data.x, data.y);
-
- mouse_report.x = data.x;
- mouse_report.y = data.y;
- }
-
- return mouse_report;
-}
-const pointing_device_driver_t pointing_device_driver = {
- .init = paw3204_init,
- .get_report = paw3204_get_report,
- .set_cpi = paw3204_set_cpi,
- .get_cpi = paw3204_get_cpi,
-};
-#elif defined(POINTING_DEVICE_DRIVER_pimoroni_trackball)
-
-mouse_xy_report_t pimoroni_trackball_adapt_values(clamp_range_t* offset) {
- if (*offset > XY_REPORT_MAX) {
- *offset -= XY_REPORT_MAX;
- return (mouse_xy_report_t)XY_REPORT_MAX;
- } else if (*offset < XY_REPORT_MIN) {
- *offset += XY_REPORT_MAX;
- return (mouse_xy_report_t)XY_REPORT_MIN;
- } else {
- mouse_xy_report_t temp_return = *offset;
- *offset = 0;
- return temp_return;
- }
-}
-
-report_mouse_t pimoroni_trackball_get_report(report_mouse_t mouse_report) {
- static uint16_t debounce = 0;
- static uint8_t error_count = 0;
- pimoroni_data_t pimoroni_data = {0};
- static clamp_range_t x_offset = 0, y_offset = 0;
-
- if (error_count < PIMORONI_TRACKBALL_ERROR_COUNT) {
- i2c_status_t status = read_pimoroni_trackball(&pimoroni_data);
-
- if (status == I2C_STATUS_SUCCESS) {
- error_count = 0;
-
- if (!(pimoroni_data.click & 128)) {
- mouse_report.buttons = pointing_device_handle_buttons(mouse_report.buttons, false, POINTING_DEVICE_BUTTON1);
- if (!debounce) {
- x_offset += pimoroni_trackball_get_offsets(pimoroni_data.right, pimoroni_data.left, PIMORONI_TRACKBALL_SCALE);
- y_offset += pimoroni_trackball_get_offsets(pimoroni_data.down, pimoroni_data.up, PIMORONI_TRACKBALL_SCALE);
- mouse_report.x = pimoroni_trackball_adapt_values(&x_offset);
- mouse_report.y = pimoroni_trackball_adapt_values(&y_offset);
- } else {
- debounce--;
- }
- } else {
- mouse_report.buttons = pointing_device_handle_buttons(mouse_report.buttons, true, POINTING_DEVICE_BUTTON1);
- debounce = PIMORONI_TRACKBALL_DEBOUNCE_CYCLES;
- }
- } else {
- error_count++;
- }
- }
- return mouse_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = pimoroni_trackball_device_init,
- .get_report = pimoroni_trackball_get_report,
- .set_cpi = pimoroni_trackball_set_cpi,
- .get_cpi = pimoroni_trackball_get_cpi
-};
-// clang-format on
-
-#elif defined(POINTING_DEVICE_DRIVER_pmw3360) || defined(POINTING_DEVICE_DRIVER_pmw3389)
-static void pmw33xx_init_wrapper(void) {
- pmw33xx_init(0);
-}
-
-static void pmw33xx_set_cpi_wrapper(uint16_t cpi) {
- pmw33xx_set_cpi(0, cpi);
-}
-
-static uint16_t pmw33xx_get_cpi_wrapper(void) {
- return pmw33xx_get_cpi(0);
-}
-
-report_mouse_t pmw33xx_get_report(report_mouse_t mouse_report) {
- pmw33xx_report_t report = pmw33xx_read_burst(0);
- static bool in_motion = false;
-
- if (report.motion.b.is_lifted) {
- return mouse_report;
- }
-
- if (!report.motion.b.is_motion) {
- in_motion = false;
- return mouse_report;
- }
-
- if (!in_motion) {
- in_motion = true;
- pd_dprintf("PWM3360 (0): starting motion\n");
- }
-
- mouse_report.x = CONSTRAIN_HID_XY(report.delta_x);
- mouse_report.y = CONSTRAIN_HID_XY(report.delta_y);
- return mouse_report;
-}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = pmw33xx_init_wrapper,
- .get_report = pmw33xx_get_report,
- .set_cpi = pmw33xx_set_cpi_wrapper,
- .get_cpi = pmw33xx_get_cpi_wrapper
-};
-// clang-format on
-
-#else
-__attribute__((weak)) void pointing_device_driver_init(void) {}
-__attribute__((weak)) report_mouse_t pointing_device_driver_get_report(report_mouse_t mouse_report) {
- return mouse_report;
-}
-__attribute__((weak)) uint16_t pointing_device_driver_get_cpi(void) {
- return 0;
-}
-__attribute__((weak)) void pointing_device_driver_set_cpi(uint16_t cpi) {}
-
-// clang-format off
-const pointing_device_driver_t pointing_device_driver = {
- .init = pointing_device_driver_init,
- .get_report = pointing_device_driver_get_report,
- .get_cpi = pointing_device_driver_get_cpi,
- .set_cpi = pointing_device_driver_set_cpi
-};
-// clang-format on
-
-#endif
diff --git a/quantum/process_keycode/process_autocorrect.c b/quantum/process_keycode/process_autocorrect.c
index edc47718f324..b7f9132acf75 100644
--- a/quantum/process_keycode/process_autocorrect.c
+++ b/quantum/process_keycode/process_autocorrect.c
@@ -98,6 +98,7 @@ bool process_autocorrect_default_handler(uint16_t *keycode, keyrecord_t *record,
case QK_TO ... QK_TO_MAX:
case QK_MOMENTARY ... QK_MOMENTARY_MAX:
case QK_DEF_LAYER ... QK_DEF_LAYER_MAX:
+ case QK_PERSISTENT_DEF_LAYER ... QK_PERSISTENT_DEF_LAYER_MAX:
case QK_TOGGLE_LAYER ... QK_TOGGLE_LAYER_MAX:
case QK_ONE_SHOT_LAYER ... QK_ONE_SHOT_LAYER_MAX:
case QK_LAYER_TAP_TOGGLE ... QK_LAYER_TAP_TOGGLE_MAX:
diff --git a/quantum/process_keycode/process_combo.c b/quantum/process_keycode/process_combo.c
index b0034d136a8f..c99a66a74b0a 100644
--- a/quantum/process_keycode/process_combo.c
+++ b/quantum/process_keycode/process_combo.c
@@ -36,19 +36,19 @@ __attribute__((weak)) uint8_t combo_ref_from_layer(uint8_t layer) {
#endif
#ifdef COMBO_MUST_HOLD_PER_COMBO
-__attribute__((weak)) bool get_combo_must_hold(uint16_t index, combo_t *combo) {
+__attribute__((weak)) bool get_combo_must_hold(uint16_t combo_index, combo_t *combo) {
return false;
}
#endif
#ifdef COMBO_MUST_TAP_PER_COMBO
-__attribute__((weak)) bool get_combo_must_tap(uint16_t index, combo_t *combo) {
+__attribute__((weak)) bool get_combo_must_tap(uint16_t combo_index, combo_t *combo) {
return false;
}
#endif
#ifdef COMBO_TERM_PER_COMBO
-__attribute__((weak)) uint16_t get_combo_term(uint16_t index, combo_t *combo) {
+__attribute__((weak)) uint16_t get_combo_term(uint16_t combo_index, combo_t *combo) {
return COMBO_TERM;
}
#endif
@@ -65,12 +65,20 @@ __attribute__((weak)) bool process_combo_key_release(uint16_t combo_index, combo
}
#endif
+#ifdef COMBO_PROCESS_KEY_REPRESS
+__attribute__((weak)) bool process_combo_key_repress(uint16_t combo_index, combo_t *combo, uint8_t key_index, uint16_t keycode) {
+ return false;
+}
+#endif
+
#ifdef COMBO_SHOULD_TRIGGER
__attribute__((weak)) bool combo_should_trigger(uint16_t combo_index, combo_t *combo, uint16_t keycode, keyrecord_t *record) {
return true;
}
#endif
+typedef enum { COMBO_KEY_NOT_PRESSED, COMBO_KEY_PRESSED, COMBO_KEY_REPRESSED } combo_key_action_t;
+
#ifndef COMBO_NO_TIMER
static uint16_t timer = 0;
#endif
@@ -414,14 +422,14 @@ static bool keys_pressed_in_order(uint16_t combo_index, combo_t *combo, uint16_t
}
#endif
-static bool process_single_combo(combo_t *combo, uint16_t keycode, keyrecord_t *record, uint16_t combo_index) {
+static combo_key_action_t process_single_combo(combo_t *combo, uint16_t keycode, keyrecord_t *record, uint16_t combo_index) {
uint8_t key_count = 0;
uint16_t key_index = -1;
_find_key_index_and_count(combo->keys, keycode, &key_index, &key_count);
/* Continue processing if key isn't part of current combo. */
if (-1 == (int16_t)key_index) {
- return false;
+ return COMBO_KEY_NOT_PRESSED;
}
bool key_is_part_of_combo = (!COMBO_DISABLED(combo) && is_combo_enabled()
@@ -449,7 +457,7 @@ static bool process_single_combo(combo_t *combo, uint16_t keycode, keyrecord_t *
/* Don't buffer this combo if its combo term has passed. */
if (timer && timer_elapsed(timer) > time) {
DISABLE_COMBO(combo);
- return true;
+ return COMBO_KEY_PRESSED;
} else
#endif
{
@@ -485,6 +493,15 @@ static bool process_single_combo(combo_t *combo, uint16_t keycode, keyrecord_t *
}
} // if timer elapsed end
}
+#ifdef COMBO_PROCESS_KEY_REPRESS
+ } else if (record->event.pressed) {
+ if (COMBO_ACTIVE(combo)) {
+ if (process_combo_key_repress(combo_index, combo, key_index, keycode)) {
+ KEY_STATE_DOWN(combo->state, key_index);
+ return COMBO_KEY_REPRESSED;
+ }
+ }
+#endif
} else {
// chord releases
if (!COMBO_ACTIVE(combo) && ALL_COMBO_KEYS_ARE_DOWN(COMBO_STATE(combo), key_count)) {
@@ -531,12 +548,12 @@ static bool process_single_combo(combo_t *combo, uint16_t keycode, keyrecord_t *
KEY_STATE_UP(combo->state, key_index);
}
- return key_is_part_of_combo;
+ return key_is_part_of_combo ? COMBO_KEY_PRESSED : COMBO_KEY_NOT_PRESSED;
}
bool process_combo(uint16_t keycode, keyrecord_t *record) {
- bool is_combo_key = false;
- bool no_combo_keys_pressed = true;
+ uint8_t is_combo_key = COMBO_KEY_NOT_PRESSED;
+ bool no_combo_keys_pressed = true;
if (keycode == QK_COMBO_ON && record->event.pressed) {
combo_enable();
@@ -582,12 +599,17 @@ bool process_combo(uint16_t keycode, keyrecord_t *record) {
# endif
#endif
- if (key_buffer_size < COMBO_KEY_BUFFER_LENGTH) {
- key_buffer[key_buffer_size++] = (queued_record_t){
- .record = *record,
- .keycode = keycode,
- .combo_index = -1, // this will be set when applying combos
- };
+#ifdef COMBO_PROCESS_KEY_REPRESS
+ if (is_combo_key == COMBO_KEY_PRESSED)
+#endif
+ {
+ if (key_buffer_size < COMBO_KEY_BUFFER_LENGTH) {
+ key_buffer[key_buffer_size++] = (queued_record_t){
+ .record = *record,
+ .keycode = keycode,
+ .combo_index = -1, // this will be set when applying combos
+ };
+ }
}
} else {
if (combo_buffer_read != combo_buffer_write) {
diff --git a/quantum/process_keycode/process_connection.c b/quantum/process_keycode/process_connection.c
new file mode 100644
index 000000000000..b0e230d680a1
--- /dev/null
+++ b/quantum/process_keycode/process_connection.c
@@ -0,0 +1,36 @@
+// Copyright 2024 Nick Brassel (@tzarc)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include "outputselect.h"
+#include "process_connection.h"
+
+bool process_connection(uint16_t keycode, keyrecord_t *record) {
+ if (record->event.pressed) {
+ switch (keycode) {
+ case QK_OUTPUT_NEXT:
+ set_output(OUTPUT_AUTO); // This should cycle through the outputs going forward. Ensure `docs/keycodes.md`, `docs/features/bluetooth.md` are updated when it does.
+ return false;
+ case QK_OUTPUT_USB:
+ set_output(OUTPUT_USB);
+ return false;
+ case QK_OUTPUT_BLUETOOTH:
+ set_output(OUTPUT_BLUETOOTH);
+ return false;
+
+ case QK_OUTPUT_PREV:
+ case QK_OUTPUT_NONE:
+ case QK_OUTPUT_2P4GHZ:
+ case QK_BLUETOOTH_PROFILE_NEXT:
+ case QK_BLUETOOTH_PROFILE_PREV:
+ case QK_BLUETOOTH_UNPAIR:
+ case QK_BLUETOOTH_PROFILE1:
+ case QK_BLUETOOTH_PROFILE2:
+ case QK_BLUETOOTH_PROFILE3:
+ case QK_BLUETOOTH_PROFILE4:
+ case QK_BLUETOOTH_PROFILE5:
+ // As-yet unimplemented.
+ // When implementation is done, ensure `docs/keycodes.md`, `docs/features/bluetooth.md` are updated accordingly.
+ return false;
+ }
+ }
+ return true;
+}
diff --git a/quantum/process_keycode/process_connection.h b/quantum/process_keycode/process_connection.h
new file mode 100644
index 000000000000..cc58011bb766
--- /dev/null
+++ b/quantum/process_keycode/process_connection.h
@@ -0,0 +1,9 @@
+// Copyright 2024 Nick Brassel (@tzarc)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#include
+#include
+#include "action.h"
+
+bool process_connection(uint16_t keycode, keyrecord_t *record);
diff --git a/keyboards/work_louder/work_board/work_board.h b/quantum/process_keycode/process_default_layer.c
similarity index 59%
rename from keyboards/work_louder/work_board/work_board.h
rename to quantum/process_keycode/process_default_layer.c
index 04de456eca03..4bca30c4100e 100644
--- a/keyboards/work_louder/work_board/work_board.h
+++ b/quantum/process_keycode/process_default_layer.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 Drashna Jael're
+/* Copyright 2023 Nebuleon
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,8 +13,20 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*/
+#include "process_default_layer.h"
+#include "quantum.h"
+#include "quantum_keycodes.h"
-#pragma once
+#if !defined(NO_ACTION_LAYER)
-#include "quantum.h"
-#include "rgb_functions.h"
+bool process_default_layer(uint16_t keycode, keyrecord_t *record) {
+ if (IS_QK_PERSISTENT_DEF_LAYER(keycode) && !record->event.pressed) {
+ uint8_t layer = QK_PERSISTENT_DEF_LAYER_GET_LAYER(keycode);
+ set_single_persistent_default_layer(layer);
+ return false;
+ }
+
+ return true;
+}
+
+#endif // !defined(NO_ACTION_LAYER)
diff --git a/quantum/process_keycode/process_rgb.h b/quantum/process_keycode/process_default_layer.h
similarity index 81%
rename from quantum/process_keycode/process_rgb.h
rename to quantum/process_keycode/process_default_layer.h
index b1069d4bb6f7..246d9958177b 100644
--- a/quantum/process_keycode/process_rgb.h
+++ b/quantum/process_keycode/process_default_layer.h
@@ -1,4 +1,4 @@
-/* Copyright 2019
+/* Copyright 2023 Nebuleon
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,10 +13,15 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*/
+
#pragma once
#include
#include
#include "action.h"
-bool process_rgb(const uint16_t keycode, const keyrecord_t *record);
+#if !defined(NO_ACTION_LAYER)
+
+bool process_default_layer(uint16_t keycode, keyrecord_t *record);
+
+#endif // !defined(NO_ACTION_LAYER)
diff --git a/quantum/process_keycode/process_haptic.c b/quantum/process_keycode/process_haptic.c
index 21d4c5ce304c..54cd7b817ef3 100644
--- a/quantum/process_keycode/process_haptic.c
+++ b/quantum/process_keycode/process_haptic.c
@@ -129,7 +129,7 @@ bool process_haptic(uint16_t keycode, keyrecord_t *record) {
}
}
- if (haptic_get_enable() && ((!HAPTIC_OFF_IN_LOW_POWER) || (usb_device_state == USB_DEVICE_STATE_CONFIGURED))) {
+ if (haptic_get_enable() && ((!HAPTIC_OFF_IN_LOW_POWER) || (usb_device_state_get_configure_state() == USB_DEVICE_STATE_CONFIGURED))) {
if (record->event.pressed) {
// keypress
if (haptic_get_feedback() < 2 && get_haptic_enabled_key(keycode, record)) {
diff --git a/quantum/process_keycode/process_layer_lock.c b/quantum/process_keycode/process_layer_lock.c
new file mode 100644
index 000000000000..6946d3c8862f
--- /dev/null
+++ b/quantum/process_keycode/process_layer_lock.c
@@ -0,0 +1,82 @@
+// Copyright 2022-2023 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "layer_lock.h"
+#include "process_layer_lock.h"
+#include "quantum_keycodes.h"
+#include "action_util.h"
+
+// The current lock state. The kth bit is on if layer k is locked.
+extern layer_state_t locked_layers;
+
+// Handles an event on an `MO` or `TT` layer switch key.
+static inline bool handle_mo_or_tt(uint8_t layer, keyrecord_t* record) {
+ if (is_layer_locked(layer)) {
+ if (record->event.pressed) { // On press, unlock the layer.
+ layer_lock_invert(layer);
+ }
+ return false; // Skip default handling.
+ }
+ return true;
+}
+
+bool process_layer_lock(uint16_t keycode, keyrecord_t* record) {
+#ifndef NO_ACTION_LAYER
+ layer_lock_activity_trigger();
+
+ // The intention is that locked layers remain on. If something outside of
+ // this feature turned any locked layers off, unlock them.
+ if ((locked_layers & ~layer_state) != 0) {
+ layer_lock_set_kb(locked_layers &= layer_state);
+ }
+
+ if (keycode == QK_LAYER_LOCK) {
+ if (record->event.pressed) { // The layer lock key was pressed.
+ layer_lock_invert(get_highest_layer(layer_state));
+ }
+ return false;
+ }
+
+ switch (keycode) {
+ case QK_MOMENTARY ... QK_MOMENTARY_MAX: // `MO(layer)` keys.
+ return handle_mo_or_tt(QK_MOMENTARY_GET_LAYER(keycode), record);
+
+ case QK_LAYER_TAP_TOGGLE ... QK_LAYER_TAP_TOGGLE_MAX: // `TT(layer)`.
+ return handle_mo_or_tt(QK_LAYER_TAP_TOGGLE_GET_LAYER(keycode), record);
+
+ case QK_LAYER_MOD ... QK_LAYER_MOD_MAX: { // `LM(layer, mod)`.
+ uint8_t layer = QK_LAYER_MOD_GET_LAYER(keycode);
+ if (is_layer_locked(layer)) {
+ if (record->event.pressed) { // On press, unlock the layer.
+ layer_lock_invert(layer);
+ } else { // On release, clear the mods.
+ clear_mods();
+ send_keyboard_report();
+ }
+ return false; // Skip default handling.
+ }
+ } break;
+
+# ifndef NO_ACTION_TAPPING
+ case QK_LAYER_TAP ... QK_LAYER_TAP_MAX: // `LT(layer, key)` keys.
+ if (record->tap.count == 0 && !record->event.pressed && is_layer_locked(QK_LAYER_TAP_GET_LAYER(keycode))) {
+ // Release event on a held layer-tap key where the layer is locked.
+ return false; // Skip default handling so that layer stays on.
+ }
+ break;
+# endif // NO_ACTION_TAPPING
+ }
+#endif // NO_ACTION_LAYER
+ return true;
+}
diff --git a/quantum/process_keycode/process_layer_lock.h b/quantum/process_keycode/process_layer_lock.h
new file mode 100644
index 000000000000..6795110029a7
--- /dev/null
+++ b/quantum/process_keycode/process_layer_lock.h
@@ -0,0 +1,21 @@
+// Copyright 2022-2023 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include
+#include
+#include "action.h"
+
+bool process_layer_lock(uint16_t keycode, keyrecord_t* record);
diff --git a/quantum/process_keycode/process_rgb.c b/quantum/process_keycode/process_rgb.c
deleted file mode 100644
index b113d1c1e7f5..000000000000
--- a/quantum/process_keycode/process_rgb.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2019
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-#include "process_rgb.h"
-#include "action_util.h"
-
-#ifdef RGB_MATRIX_ENABLE
-# include "rgb_matrix.h"
-#endif
-#ifdef RGBLIGHT_ENABLE
-# include "rgblight.h"
-#endif
-
-typedef void (*rgb_func_pointer)(void);
-
-/**
- * Wrapper for inc/dec rgb keycode
- *
- * noinline to optimise for firmware size not speed (not in hot path)
- */
-#if (defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)) || (defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES))
-static void __attribute__((noinline)) handleKeycodeRGB(const uint8_t is_shifted, const rgb_func_pointer inc_func, const rgb_func_pointer dec_func) {
- if (is_shifted) {
- dec_func();
- } else {
- inc_func();
- }
-}
-#endif
-
-/**
- * Wrapper for animation mode
- * - if not in animation family -> jump to that animation
- * - otherwise -> wrap round animation speed
- *
- * noinline to optimise for firmware size not speed (not in hot path)
- */
-static void __attribute__((noinline, unused)) handleKeycodeRGBMode(const uint8_t start, const uint8_t end) {
- if ((start <= rgblight_get_mode()) && (rgblight_get_mode() < end)) {
- rgblight_step();
- } else {
- rgblight_mode(start);
- }
-}
-
-/**
- * Handle keycodes for both rgblight and rgbmatrix
- */
-bool process_rgb(const uint16_t keycode, const keyrecord_t *record) {
- // need to trigger on key-up for edge-case issue
-#ifndef RGB_TRIGGER_ON_KEYDOWN
- if (!record->event.pressed) {
-#else
- if (record->event.pressed) {
-#endif
-#if (defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)) || (defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES))
- uint8_t shifted = get_mods() & MOD_MASK_SHIFT;
-#endif
- switch (keycode) {
- case QK_UNDERGLOW_TOGGLE:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- rgblight_toggle();
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- rgb_matrix_toggle();
-#endif
- return false;
- case QK_UNDERGLOW_MODE_NEXT:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_step, rgblight_step_reverse);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_step, rgb_matrix_step_reverse);
-#endif
- return false;
- case QK_UNDERGLOW_MODE_PREVIOUS:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_step_reverse, rgblight_step);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_step_reverse, rgb_matrix_step);
-#endif
- return false;
- case QK_UNDERGLOW_HUE_UP:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_increase_hue, rgblight_decrease_hue);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_increase_hue, rgb_matrix_decrease_hue);
-#endif
- return false;
- case QK_UNDERGLOW_HUE_DOWN:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_decrease_hue, rgblight_increase_hue);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_decrease_hue, rgb_matrix_increase_hue);
-#endif
- return false;
- case QK_UNDERGLOW_SATURATION_UP:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_increase_sat, rgblight_decrease_sat);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_increase_sat, rgb_matrix_decrease_sat);
-#endif
- return false;
- case QK_UNDERGLOW_SATURATION_DOWN:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_decrease_sat, rgblight_increase_sat);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_decrease_sat, rgb_matrix_increase_sat);
-#endif
- return false;
- case QK_UNDERGLOW_VALUE_UP:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_increase_val, rgblight_decrease_val);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_increase_val, rgb_matrix_decrease_val);
-#endif
- return false;
- case QK_UNDERGLOW_VALUE_DOWN:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_decrease_val, rgblight_increase_val);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_decrease_val, rgb_matrix_increase_val);
-#endif
- return false;
- case QK_UNDERGLOW_SPEED_UP:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_increase_speed, rgblight_decrease_speed);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_increase_speed, rgb_matrix_decrease_speed);
-#endif
- return false;
- case QK_UNDERGLOW_SPEED_DOWN:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgblight_decrease_speed, rgblight_increase_speed);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- handleKeycodeRGB(shifted, rgb_matrix_decrease_speed, rgb_matrix_increase_speed);
-#endif
- return false;
- case RGB_MODE_PLAIN:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES)
- rgblight_mode(RGBLIGHT_MODE_STATIC_LIGHT);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES)
- rgb_matrix_mode(RGB_MATRIX_SOLID_COLOR);
-#endif
- return false;
- case RGB_MODE_BREATHE:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_BREATHING)
- handleKeycodeRGBMode(RGBLIGHT_MODE_BREATHING, RGBLIGHT_MODE_BREATHING_end);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES) && defined(ENABLE_RGB_MATRIX_BREATHING)
- rgb_matrix_mode(RGB_MATRIX_BREATHING);
-#endif
- return false;
- case RGB_MODE_RAINBOW:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_RAINBOW_MOOD)
- handleKeycodeRGBMode(RGBLIGHT_MODE_RAINBOW_MOOD, RGBLIGHT_MODE_RAINBOW_MOOD_end);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES) && defined(ENABLE_RGB_MATRIX_CYCLE_LEFT_RIGHT)
- rgb_matrix_mode(RGB_MATRIX_CYCLE_LEFT_RIGHT);
-#endif
- return false;
- case RGB_MODE_SWIRL:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_RAINBOW_SWIRL)
- handleKeycodeRGBMode(RGBLIGHT_MODE_RAINBOW_SWIRL, RGBLIGHT_MODE_RAINBOW_SWIRL_end);
-#endif
-#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_KEYCODES) && defined(ENABLE_RGB_MATRIX_CYCLE_PINWHEEL)
- rgb_matrix_mode(RGB_MATRIX_CYCLE_PINWHEEL);
-#endif
- return false;
- case RGB_MODE_SNAKE:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_SNAKE)
- handleKeycodeRGBMode(RGBLIGHT_MODE_SNAKE, RGBLIGHT_MODE_SNAKE_end);
-#endif
- return false;
- case RGB_MODE_KNIGHT:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_KNIGHT)
- handleKeycodeRGBMode(RGBLIGHT_MODE_KNIGHT, RGBLIGHT_MODE_KNIGHT_end);
-#endif
- return false;
- case RGB_MODE_XMAS:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_CHRISTMAS)
- rgblight_mode(RGBLIGHT_MODE_CHRISTMAS);
-#endif
- return false;
- case RGB_MODE_GRADIENT:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_STATIC_GRADIENT)
- handleKeycodeRGBMode(RGBLIGHT_MODE_STATIC_GRADIENT, RGBLIGHT_MODE_STATIC_GRADIENT_end);
-#endif
- return false;
- case RGB_MODE_RGBTEST:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_RGB_TEST)
- rgblight_mode(RGBLIGHT_MODE_RGB_TEST);
-#endif
- return false;
- case RGB_MODE_TWINKLE:
-#if defined(RGBLIGHT_ENABLE) && !defined(RGBLIGHT_DISABLE_KEYCODES) && defined(RGBLIGHT_EFFECT_TWINKLE)
- handleKeycodeRGBMode(RGBLIGHT_MODE_TWINKLE, RGBLIGHT_MODE_TWINKLE_end);
-#endif
- return false;
- }
- }
-
- return true;
-}
diff --git a/quantum/process_keycode/process_underglow.c b/quantum/process_keycode/process_underglow.c
index 779672ac0768..6104cd02c6ce 100644
--- a/quantum/process_keycode/process_underglow.c
+++ b/quantum/process_keycode/process_underglow.c
@@ -2,87 +2,200 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "process_underglow.h"
-#include "rgblight.h"
+#if defined(RGBLIGHT_ENABLE)
+# include "rgblight.h"
+#endif
#include "action_util.h"
#include "keycodes.h"
#include "modifiers.h"
+// TODO: Remove this
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+# include "rgb_matrix.h"
+#endif
+
bool process_underglow(uint16_t keycode, keyrecord_t *record) {
if (record->event.pressed) {
uint8_t shifted = get_mods() & MOD_MASK_SHIFT;
switch (keycode) {
case QK_UNDERGLOW_TOGGLE:
+#if defined(RGBLIGHT_ENABLE)
rgblight_toggle();
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ rgb_matrix_toggle();
+#endif
return false;
case QK_UNDERGLOW_MODE_NEXT:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_step_reverse();
} else {
rgblight_step();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_step_reverse();
+ } else {
+ rgb_matrix_step();
+ }
+#endif
return false;
case QK_UNDERGLOW_MODE_PREVIOUS:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_step();
} else {
rgblight_step_reverse();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_step();
+ } else {
+ rgb_matrix_step_reverse();
+ }
+#endif
return false;
case QK_UNDERGLOW_HUE_UP:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_decrease_hue();
} else {
rgblight_increase_hue();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_decrease_hue();
+ } else {
+ rgb_matrix_increase_hue();
+ }
+#endif
return false;
case QK_UNDERGLOW_HUE_DOWN:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_increase_hue();
} else {
rgblight_decrease_hue();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_increase_hue();
+ } else {
+ rgb_matrix_decrease_hue();
+ }
+#endif
return false;
case QK_UNDERGLOW_SATURATION_UP:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_decrease_sat();
} else {
rgblight_increase_sat();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_decrease_sat();
+ } else {
+ rgb_matrix_increase_sat();
+ }
+#endif
return false;
case QK_UNDERGLOW_SATURATION_DOWN:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_increase_sat();
} else {
rgblight_decrease_sat();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_increase_sat();
+ } else {
+ rgb_matrix_decrease_sat();
+ }
+#endif
return false;
case QK_UNDERGLOW_VALUE_UP:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_decrease_val();
} else {
rgblight_increase_val();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_decrease_val();
+ } else {
+ rgb_matrix_increase_val();
+ }
+#endif
return false;
case QK_UNDERGLOW_VALUE_DOWN:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
- rgblight_increase_hue();
+ rgblight_increase_val();
} else {
- rgblight_decrease_hue();
+ rgblight_decrease_val();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_increase_val();
+ } else {
+ rgb_matrix_decrease_val();
+ }
+#endif
return false;
case QK_UNDERGLOW_SPEED_UP:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_decrease_speed();
} else {
rgblight_increase_speed();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_decrease_speed();
+ } else {
+ rgb_matrix_increase_speed();
+ }
+#endif
return false;
case QK_UNDERGLOW_SPEED_DOWN:
+#if defined(RGBLIGHT_ENABLE)
if (shifted) {
rgblight_increase_speed();
} else {
rgblight_decrease_speed();
}
+#endif
+
+#if defined(RGB_MATRIX_ENABLE) && !defined(RGB_MATRIX_DISABLE_SHARED_KEYCODES)
+ if (shifted) {
+ rgb_matrix_increase_speed();
+ } else {
+ rgb_matrix_decrease_speed();
+ }
+#endif
return false;
}
}
diff --git a/quantum/quantum.c b/quantum/quantum.c
index 011f9d73e4af..d4ebd58e7fca 100644
--- a/quantum/quantum.c
+++ b/quantum/quantum.c
@@ -21,7 +21,7 @@
#endif
#ifdef BLUETOOTH_ENABLE
-# include "outputselect.h"
+# include "process_connection.h"
#endif
#ifdef GRAVE_ESC_ENABLE
@@ -52,12 +52,20 @@
# include "process_midi.h"
#endif
+#if !defined(NO_ACTION_LAYER)
+# include "process_default_layer.h"
+#endif
+
#ifdef PROGRAMMABLE_BUTTON_ENABLE
# include "process_programmable_button.h"
#endif
+#if defined(RGB_MATRIX_ENABLE)
+# include "process_rgb_matrix.h"
+#endif
+
#if defined(RGBLIGHT_ENABLE) || defined(RGB_MATRIX_ENABLE)
-# include "process_rgb.h"
+# include "process_underglow.h"
#endif
#ifdef SECURE_ENABLE
@@ -72,6 +80,10 @@
# include "process_unicode_common.h"
#endif
+#ifdef LAYER_LOCK_ENABLE
+# include "process_layer_lock.h"
+#endif
+
#ifdef AUDIO_ENABLE
# ifndef GOODBYE_SONG
# define GOODBYE_SONG SONG(GOODBYE_SOUND)
@@ -246,10 +258,9 @@ uint16_t get_event_keycode(keyevent_t event, bool update_layer_cache) {
/* Get keycode, and then process pre tapping functionality */
bool pre_process_record_quantum(keyrecord_t *record) {
- uint16_t keycode = get_record_keycode(record, true);
- return pre_process_record_kb(keycode, record) &&
+ return pre_process_record_kb(get_record_keycode(record, true), record) &&
#ifdef COMBO_ENABLE
- process_combo(keycode, record) &&
+ process_combo(get_record_keycode(record, true), record) &&
#endif
true;
}
@@ -380,7 +391,10 @@ bool process_record_quantum(keyrecord_t *record) {
process_grave_esc(keycode, record) &&
#endif
#if defined(RGBLIGHT_ENABLE) || defined(RGB_MATRIX_ENABLE)
- process_rgb(keycode, record) &&
+ process_underglow(keycode, record) &&
+#endif
+#if defined(RGB_MATRIX_ENABLE)
+ process_rgb_matrix(keycode, record) &&
#endif
#ifdef JOYSTICK_ENABLE
process_joystick(keycode, record) &&
@@ -393,6 +407,15 @@ bool process_record_quantum(keyrecord_t *record) {
#endif
#ifdef TRI_LAYER_ENABLE
process_tri_layer(keycode, record) &&
+#endif
+#if !defined(NO_ACTION_LAYER)
+ process_default_layer(keycode, record) &&
+#endif
+#ifdef LAYER_LOCK_ENABLE
+ process_layer_lock(keycode, record) &&
+#endif
+#ifdef BLUETOOTH_ENABLE
+ process_connection(keycode, record) &&
#endif
true)) {
return false;
@@ -431,17 +454,6 @@ bool process_record_quantum(keyrecord_t *record) {
velocikey_toggle();
return false;
#endif
-#ifdef BLUETOOTH_ENABLE
- case QK_OUTPUT_AUTO:
- set_output(OUTPUT_AUTO);
- return false;
- case QK_OUTPUT_USB:
- set_output(OUTPUT_USB);
- return false;
- case QK_OUTPUT_BLUETOOTH:
- set_output(OUTPUT_BLUETOOTH);
- return false;
-#endif
#ifndef NO_ACTION_ONESHOT
case QK_ONE_SHOT_TOGGLE:
oneshot_toggle();
@@ -486,14 +498,18 @@ bool process_record_quantum(keyrecord_t *record) {
return process_action_kb(record);
}
-void set_single_persistent_default_layer(uint8_t default_layer) {
+void set_single_default_layer(uint8_t default_layer) {
#if defined(AUDIO_ENABLE) && defined(DEFAULT_LAYER_SONGS)
PLAY_SONG(default_layer_songs[default_layer]);
#endif
- eeconfig_update_default_layer((layer_state_t)1 << default_layer);
default_layer_set((layer_state_t)1 << default_layer);
}
+void set_single_persistent_default_layer(uint8_t default_layer) {
+ eeconfig_update_default_layer((layer_state_t)1 << default_layer);
+ set_single_default_layer(default_layer);
+}
+
//------------------------------------------------------------------------------
// Override these functions in your keymap file to play different tunes on
// different events such as startup and bootloader jump
diff --git a/quantum/quantum.h b/quantum/quantum.h
index 5446ab1ad719..9db88a54d4ba 100644
--- a/quantum/quantum.h
+++ b/quantum/quantum.h
@@ -240,6 +240,11 @@ extern layer_state_t layer_state;
# include "os_detection.h"
#endif
+#ifdef LAYER_LOCK_ENABLE
+# include "layer_lock.h"
+#endif
+
+void set_single_default_layer(uint8_t default_layer);
void set_single_persistent_default_layer(uint8_t default_layer);
#define IS_LAYER_ON(layer) layer_state_is(layer)
diff --git a/quantum/quantum_keycodes.h b/quantum/quantum_keycodes.h
index 882e1d07aec6..bcaf94af8b9d 100644
--- a/quantum/quantum_keycodes.h
+++ b/quantum/quantum_keycodes.h
@@ -92,6 +92,10 @@
#define DF(layer) (QK_DEF_LAYER | ((layer)&0x1F))
#define QK_DEF_LAYER_GET_LAYER(kc) ((kc)&0x1F)
+// Set persistent default layer - 32 layer max
+#define PDF(layer) (QK_PERSISTENT_DEF_LAYER | ((layer)&0x1F))
+#define QK_PERSISTENT_DEF_LAYER_GET_LAYER(kc) ((kc)&0x1F)
+
// Toggle to layer - 32 layer max
#define TG(layer) (QK_TOGGLE_LAYER | ((layer)&0x1F))
#define QK_TOGGLE_LAYER_GET_LAYER(kc) ((kc)&0x1F)
diff --git a/quantum/quantum_keycodes_legacy.h b/quantum/quantum_keycodes_legacy.h
index e1562077e5f3..21aec90675a1 100644
--- a/quantum/quantum_keycodes_legacy.h
+++ b/quantum/quantum_keycodes_legacy.h
@@ -55,3 +55,5 @@
#define KC_ACL1 QK_MOUSE_ACCELERATION_1
#define KC_MS_ACCEL2 QK_MOUSE_ACCELERATION_2
#define KC_ACL2 QK_MOUSE_ACCELERATION_2
+
+#define QK_OUTPUT_AUTO OU_AUTO
diff --git a/quantum/rgb_matrix/animations/alpha_mods_anim.h b/quantum/rgb_matrix/animations/alpha_mods_anim.h
index 59b8381d6984..2f76feb0fc41 100644
--- a/quantum/rgb_matrix/animations/alpha_mods_anim.h
+++ b/quantum/rgb_matrix/animations/alpha_mods_anim.h
@@ -6,10 +6,10 @@ RGB_MATRIX_EFFECT(ALPHAS_MODS)
bool ALPHAS_MODS(effect_params_t* params) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
- HSV hsv = rgb_matrix_config.hsv;
- RGB rgb1 = rgb_matrix_hsv_to_rgb(hsv);
+ hsv_t hsv = rgb_matrix_config.hsv;
+ rgb_t rgb1 = rgb_matrix_hsv_to_rgb(hsv);
hsv.h += rgb_matrix_config.speed;
- RGB rgb2 = rgb_matrix_hsv_to_rgb(hsv);
+ rgb_t rgb2 = rgb_matrix_hsv_to_rgb(hsv);
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
diff --git a/quantum/rgb_matrix/animations/breathing_anim.h b/quantum/rgb_matrix/animations/breathing_anim.h
index e9a3c96e1bb8..8fa8e3dad4d4 100644
--- a/quantum/rgb_matrix/animations/breathing_anim.h
+++ b/quantum/rgb_matrix/animations/breathing_anim.h
@@ -2,18 +2,13 @@
RGB_MATRIX_EFFECT(BREATHING)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-bool BREATHING(effect_params_t* params) {
- RGB_MATRIX_USE_LIMITS(led_min, led_max);
+hsv_t BREATHING_math(hsv_t hsv, uint8_t i, uint8_t time) {
+ hsv.v = scale8(abs8(sin8(time / 2) - 128) * 2, hsv.v);
+ return hsv;
+}
- HSV hsv = rgb_matrix_config.hsv;
- uint16_t time = scale16by8(g_rgb_timer, rgb_matrix_config.speed / 8);
- hsv.v = scale8(abs8(sin8(time) - 128) * 2, hsv.v);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
- for (uint8_t i = led_min; i < led_max; i++) {
- RGB_MATRIX_TEST_LED_FLAGS();
- rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
- }
- return rgb_matrix_check_finished_leds(led_max);
+bool BREATHING(effect_params_t* params) {
+ return effect_runner_i(params, &BREATHING_math);
}
# endif // RGB_MATRIX_CUSTOM_EFFECT_IMPLS
diff --git a/quantum/rgb_matrix/animations/colorband_pinwheel_sat_anim.h b/quantum/rgb_matrix/animations/colorband_pinwheel_sat_anim.h
index 06aa8b5ed5f4..5ae5b193b083 100644
--- a/quantum/rgb_matrix/animations/colorband_pinwheel_sat_anim.h
+++ b/quantum/rgb_matrix/animations/colorband_pinwheel_sat_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(BAND_PINWHEEL_SAT)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV BAND_PINWHEEL_SAT_math(HSV hsv, int16_t dx, int16_t dy, uint8_t time) {
+static hsv_t BAND_PINWHEEL_SAT_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t time) {
hsv.s = scale8(hsv.s - time - atan2_8(dy, dx) * 3, hsv.s);
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/colorband_pinwheel_val_anim.h b/quantum/rgb_matrix/animations/colorband_pinwheel_val_anim.h
index bcbc31949814..157a8c1c198d 100644
--- a/quantum/rgb_matrix/animations/colorband_pinwheel_val_anim.h
+++ b/quantum/rgb_matrix/animations/colorband_pinwheel_val_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(BAND_PINWHEEL_VAL)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV BAND_PINWHEEL_VAL_math(HSV hsv, int16_t dx, int16_t dy, uint8_t time) {
+static hsv_t BAND_PINWHEEL_VAL_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t time) {
hsv.v = scale8(hsv.v - time - atan2_8(dy, dx) * 3, hsv.v);
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/colorband_sat_anim.h b/quantum/rgb_matrix/animations/colorband_sat_anim.h
index cb0897ad3e9a..a0d0e6e81162 100644
--- a/quantum/rgb_matrix/animations/colorband_sat_anim.h
+++ b/quantum/rgb_matrix/animations/colorband_sat_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(BAND_SAT)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV BAND_SAT_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t BAND_SAT_math(hsv_t hsv, uint8_t i, uint8_t time) {
int16_t s = hsv.s - abs(scale8(g_led_config.point[i].x, 228) + 28 - time) * 8;
hsv.s = scale8(s < 0 ? 0 : s, hsv.s);
return hsv;
diff --git a/quantum/rgb_matrix/animations/colorband_spiral_sat_anim.h b/quantum/rgb_matrix/animations/colorband_spiral_sat_anim.h
index d26eb378558a..7d2e5b326912 100644
--- a/quantum/rgb_matrix/animations/colorband_spiral_sat_anim.h
+++ b/quantum/rgb_matrix/animations/colorband_spiral_sat_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(BAND_SPIRAL_SAT)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV BAND_SPIRAL_SAT_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
+static hsv_t BAND_SPIRAL_SAT_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
hsv.s = scale8(hsv.s + dist - time - atan2_8(dy, dx), hsv.s);
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/colorband_spiral_val_anim.h b/quantum/rgb_matrix/animations/colorband_spiral_val_anim.h
index 3ae34bb6f097..9cd9c084d117 100644
--- a/quantum/rgb_matrix/animations/colorband_spiral_val_anim.h
+++ b/quantum/rgb_matrix/animations/colorband_spiral_val_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(BAND_SPIRAL_VAL)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV BAND_SPIRAL_VAL_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
+static hsv_t BAND_SPIRAL_VAL_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
hsv.v = scale8(hsv.v + dist - time - atan2_8(dy, dx), hsv.v);
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/colorband_val_anim.h b/quantum/rgb_matrix/animations/colorband_val_anim.h
index 69c29f53a355..ccffae259f90 100644
--- a/quantum/rgb_matrix/animations/colorband_val_anim.h
+++ b/quantum/rgb_matrix/animations/colorband_val_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(BAND_VAL)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV BAND_VAL_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t BAND_VAL_math(hsv_t hsv, uint8_t i, uint8_t time) {
int16_t v = hsv.v - abs(scale8(g_led_config.point[i].x, 228) + 28 - time) * 8;
hsv.v = scale8(v < 0 ? 0 : v, hsv.v);
return hsv;
diff --git a/quantum/rgb_matrix/animations/cycle_all_anim.h b/quantum/rgb_matrix/animations/cycle_all_anim.h
index d8c7220d95e7..8fafcf8d11ec 100644
--- a/quantum/rgb_matrix/animations/cycle_all_anim.h
+++ b/quantum/rgb_matrix/animations/cycle_all_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(CYCLE_ALL)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV CYCLE_ALL_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t CYCLE_ALL_math(hsv_t hsv, uint8_t i, uint8_t time) {
hsv.h = time;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/cycle_left_right_anim.h b/quantum/rgb_matrix/animations/cycle_left_right_anim.h
index 84c2127aff9a..2d8871a300e0 100644
--- a/quantum/rgb_matrix/animations/cycle_left_right_anim.h
+++ b/quantum/rgb_matrix/animations/cycle_left_right_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(CYCLE_LEFT_RIGHT)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV CYCLE_LEFT_RIGHT_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t CYCLE_LEFT_RIGHT_math(hsv_t hsv, uint8_t i, uint8_t time) {
hsv.h = g_led_config.point[i].x - time;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/cycle_out_in_anim.h b/quantum/rgb_matrix/animations/cycle_out_in_anim.h
index 9513fe959344..faf920a60830 100644
--- a/quantum/rgb_matrix/animations/cycle_out_in_anim.h
+++ b/quantum/rgb_matrix/animations/cycle_out_in_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(CYCLE_OUT_IN)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV CYCLE_OUT_IN_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
+static hsv_t CYCLE_OUT_IN_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
hsv.h = 3 * dist / 2 + time;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/cycle_out_in_dual_anim.h b/quantum/rgb_matrix/animations/cycle_out_in_dual_anim.h
index 3cca45f27a57..4203a8ffd2be 100644
--- a/quantum/rgb_matrix/animations/cycle_out_in_dual_anim.h
+++ b/quantum/rgb_matrix/animations/cycle_out_in_dual_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(CYCLE_OUT_IN_DUAL)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV CYCLE_OUT_IN_DUAL_math(HSV hsv, int16_t dx, int16_t dy, uint8_t time) {
+static hsv_t CYCLE_OUT_IN_DUAL_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t time) {
dx = (k_rgb_matrix_center.x / 2) - abs8(dx);
uint8_t dist = sqrt16(dx * dx + dy * dy);
hsv.h = 3 * dist + time;
diff --git a/quantum/rgb_matrix/animations/cycle_pinwheel_anim.h b/quantum/rgb_matrix/animations/cycle_pinwheel_anim.h
index de5993992cbe..d557ffeb780a 100644
--- a/quantum/rgb_matrix/animations/cycle_pinwheel_anim.h
+++ b/quantum/rgb_matrix/animations/cycle_pinwheel_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(CYCLE_PINWHEEL)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV CYCLE_PINWHEEL_math(HSV hsv, int16_t dx, int16_t dy, uint8_t time) {
+static hsv_t CYCLE_PINWHEEL_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t time) {
hsv.h = atan2_8(dy, dx) + time;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/cycle_spiral_anim.h b/quantum/rgb_matrix/animations/cycle_spiral_anim.h
index 904450179eb1..6d7a2dc5b48b 100644
--- a/quantum/rgb_matrix/animations/cycle_spiral_anim.h
+++ b/quantum/rgb_matrix/animations/cycle_spiral_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(CYCLE_SPIRAL)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV CYCLE_SPIRAL_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
+static hsv_t CYCLE_SPIRAL_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time) {
hsv.h = dist - time - atan2_8(dy, dx);
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/cycle_up_down_anim.h b/quantum/rgb_matrix/animations/cycle_up_down_anim.h
index dce05fecff0c..09c8ace46bbb 100644
--- a/quantum/rgb_matrix/animations/cycle_up_down_anim.h
+++ b/quantum/rgb_matrix/animations/cycle_up_down_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(CYCLE_UP_DOWN)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV CYCLE_UP_DOWN_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t CYCLE_UP_DOWN_math(hsv_t hsv, uint8_t i, uint8_t time) {
hsv.h = g_led_config.point[i].y - time;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/dual_beacon_anim.h b/quantum/rgb_matrix/animations/dual_beacon_anim.h
index 5585015b8694..7279f1ce5303 100644
--- a/quantum/rgb_matrix/animations/dual_beacon_anim.h
+++ b/quantum/rgb_matrix/animations/dual_beacon_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(DUAL_BEACON)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV DUAL_BEACON_math(HSV hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time) {
+static hsv_t DUAL_BEACON_math(hsv_t hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time) {
hsv.h += ((g_led_config.point[i].y - k_rgb_matrix_center.y) * cos + (g_led_config.point[i].x - k_rgb_matrix_center.x) * sin) / 128;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/flower_blooming_anim.h b/quantum/rgb_matrix/animations/flower_blooming_anim.h
index 7629fde858ca..91f70c8d520b 100644
--- a/quantum/rgb_matrix/animations/flower_blooming_anim.h
+++ b/quantum/rgb_matrix/animations/flower_blooming_anim.h
@@ -18,7 +18,7 @@
RGB_MATRIX_EFFECT(FLOWER_BLOOMING)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-typedef HSV (*flower_blooming_f)(HSV hsv, uint8_t i, uint8_t time);
+typedef hsv_t (*flower_blooming_f)(hsv_t hsv, uint8_t i, uint8_t time);
bool effect_runner_bloom(effect_params_t* params, flower_blooming_f effect_func) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
@@ -27,17 +27,17 @@ bool effect_runner_bloom(effect_params_t* params, flower_blooming_f effect_func)
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
if (g_led_config.point[i].y > k_rgb_matrix_center.y) {
- RGB bgr = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, i, time));
+ rgb_t bgr = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, i, time));
rgb_matrix_set_color(i, bgr.b, bgr.g, bgr.r);
} else {
- RGB rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, i, time));
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, i, time));
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
}
return rgb_matrix_check_finished_leds(led_max);
}
-static HSV FLOWER_BLOOMING_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t FLOWER_BLOOMING_math(hsv_t hsv, uint8_t i, uint8_t time) {
if (g_led_config.point[i].y > k_rgb_matrix_center.y)
hsv.h = g_led_config.point[i].x * 3 - g_led_config.point[i].y * 3 + time;
else
diff --git a/quantum/rgb_matrix/animations/gradient_left_right_anim.h b/quantum/rgb_matrix/animations/gradient_left_right_anim.h
index ebb06f59f278..4175ab330dc3 100644
--- a/quantum/rgb_matrix/animations/gradient_left_right_anim.h
+++ b/quantum/rgb_matrix/animations/gradient_left_right_anim.h
@@ -5,14 +5,14 @@ RGB_MATRIX_EFFECT(GRADIENT_LEFT_RIGHT)
bool GRADIENT_LEFT_RIGHT(effect_params_t* params) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
- HSV hsv = rgb_matrix_config.hsv;
+ hsv_t hsv = rgb_matrix_config.hsv;
uint8_t scale = scale8(64, rgb_matrix_config.speed);
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
// The x range will be 0..224, map this to 0..7
// Relies on hue being 8-bit and wrapping
- hsv.h = rgb_matrix_config.hsv.h + (scale * g_led_config.point[i].x >> 5);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ hsv.h = rgb_matrix_config.hsv.h + (scale * g_led_config.point[i].x >> 5);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/gradient_up_down_anim.h b/quantum/rgb_matrix/animations/gradient_up_down_anim.h
index febc3919a888..e3953fb035ed 100644
--- a/quantum/rgb_matrix/animations/gradient_up_down_anim.h
+++ b/quantum/rgb_matrix/animations/gradient_up_down_anim.h
@@ -5,14 +5,14 @@ RGB_MATRIX_EFFECT(GRADIENT_UP_DOWN)
bool GRADIENT_UP_DOWN(effect_params_t* params) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
- HSV hsv = rgb_matrix_config.hsv;
+ hsv_t hsv = rgb_matrix_config.hsv;
uint8_t scale = scale8(64, rgb_matrix_config.speed);
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
// The y range will be 0..64, map this to 0..4
// Relies on hue being 8-bit and wrapping
- hsv.h = rgb_matrix_config.hsv.h + scale * (g_led_config.point[i].y >> 4);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ hsv.h = rgb_matrix_config.hsv.h + scale * (g_led_config.point[i].y >> 4);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/hue_breathing_anim.h b/quantum/rgb_matrix/animations/hue_breathing_anim.h
index 853776283298..5316e92dbdc5 100644
--- a/quantum/rgb_matrix/animations/hue_breathing_anim.h
+++ b/quantum/rgb_matrix/animations/hue_breathing_anim.h
@@ -7,10 +7,10 @@ RGB_MATRIX_EFFECT(HUE_BREATHING)
bool HUE_BREATHING(effect_params_t* params) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
uint8_t huedelta = 12;
- HSV hsv = rgb_matrix_config.hsv;
+ hsv_t hsv = rgb_matrix_config.hsv;
uint16_t time = scale16by8(g_rgb_timer, rgb_matrix_config.speed / 8);
hsv.h = hsv.h + scale8(abs8(sin8(time) - 128) * 2, huedelta);
- RGB rgb = hsv_to_rgb(hsv);
+ rgb_t rgb = hsv_to_rgb(hsv);
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
diff --git a/quantum/rgb_matrix/animations/hue_pendulum_anim.h b/quantum/rgb_matrix/animations/hue_pendulum_anim.h
index 7d8cbcdfb243..ba0a5b45a4de 100644
--- a/quantum/rgb_matrix/animations/hue_pendulum_anim.h
+++ b/quantum/rgb_matrix/animations/hue_pendulum_anim.h
@@ -5,7 +5,7 @@ RGB_MATRIX_EFFECT(HUE_PENDULUM)
// Change huedelta to adjust range of hue change. 0-255.
// Looks better with a low value and slow speed for subtle change.
// Hue Pendulum - color changes in a wave to the right before reversing direction
-static HSV HUE_PENDULUM_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t HUE_PENDULUM_math(hsv_t hsv, uint8_t i, uint8_t time) {
uint8_t huedelta = 12;
hsv.h = hsv.h + scale8(abs8(sin8(time) + (g_led_config.point[i].x) - 128) * 2, huedelta);
return hsv;
diff --git a/quantum/rgb_matrix/animations/hue_wave_anim.h b/quantum/rgb_matrix/animations/hue_wave_anim.h
index 81aa7e139e9a..7b729a1816fb 100644
--- a/quantum/rgb_matrix/animations/hue_wave_anim.h
+++ b/quantum/rgb_matrix/animations/hue_wave_anim.h
@@ -5,7 +5,7 @@ RGB_MATRIX_EFFECT(HUE_WAVE)
// Change huedelta to adjust range of hue change. 0-255.
// Looks better with a low value and slow speed for subtle change.
// Hue Wave - color changes in a wave to the right
-static HSV HUE_WAVE_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t HUE_WAVE_math(hsv_t hsv, uint8_t i, uint8_t time) {
uint8_t huedelta = 24;
hsv.h = hsv.h + scale8(abs8(g_led_config.point[i].x - time), huedelta);
return hsv;
diff --git a/quantum/rgb_matrix/animations/jellybean_raindrops_anim.h b/quantum/rgb_matrix/animations/jellybean_raindrops_anim.h
index 5d3df1059e5c..5790b2736731 100644
--- a/quantum/rgb_matrix/animations/jellybean_raindrops_anim.h
+++ b/quantum/rgb_matrix/animations/jellybean_raindrops_anim.h
@@ -2,25 +2,33 @@
RGB_MATRIX_EFFECT(JELLYBEAN_RAINDROPS)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static void jellybean_raindrops_set_color(int i, effect_params_t* params) {
+static void jellybean_raindrops_set_color(uint8_t i, effect_params_t* params) {
if (!HAS_ANY_FLAGS(g_led_config.flags[i], params->flags)) return;
- HSV hsv = {random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v};
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+
+ hsv_t hsv = {random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v};
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
bool JELLYBEAN_RAINDROPS(effect_params_t* params) {
+ static uint16_t index = RGB_MATRIX_LED_COUNT + 1;
+
+ // Periodic trigger for LED change
+ if ((params->iter == 0) && (scale16by8(g_rgb_timer, qadd8(rgb_matrix_config.speed, 16)) % 5 == 0)) {
+ index = random8_max(RGB_MATRIX_LED_COUNT);
+ }
+
RGB_MATRIX_USE_LIMITS(led_min, led_max);
- if (!params->init) {
- // Change one LED every tick, make sure speed is not 0
- if (scale16by8(g_rgb_timer, qadd8(rgb_matrix_config.speed, 16)) % 5 == 0) {
- jellybean_raindrops_set_color(random8_max(RGB_MATRIX_LED_COUNT), params);
- }
- } else {
- for (int i = led_min; i < led_max; i++) {
+ if (params->init) {
+ for (uint8_t i = led_min; i < led_max; i++) {
jellybean_raindrops_set_color(i, params);
}
}
+ // Change LED once and set index out of range till next trigger
+ else if (led_min <= index && index < led_max) {
+ jellybean_raindrops_set_color(index, params);
+ index = RGB_MATRIX_LED_COUNT + 1;
+ }
return rgb_matrix_check_finished_leds(led_max);
}
diff --git a/quantum/rgb_matrix/animations/pixel_flow_anim.h b/quantum/rgb_matrix/animations/pixel_flow_anim.h
index 27567b4f3a53..35170f9588e5 100644
--- a/quantum/rgb_matrix/animations/pixel_flow_anim.h
+++ b/quantum/rgb_matrix/animations/pixel_flow_anim.h
@@ -7,7 +7,7 @@ RGB_MATRIX_EFFECT(PIXEL_FLOW)
static bool PIXEL_FLOW(effect_params_t* params) {
// LED state array
- static RGB led[RGB_MATRIX_LED_COUNT];
+ static rgb_t led[RGB_MATRIX_LED_COUNT];
static uint32_t wait_timer = 0;
if (wait_timer > g_rgb_timer) {
@@ -22,7 +22,7 @@ static bool PIXEL_FLOW(effect_params_t* params) {
// Clear LEDs and fill the state array
rgb_matrix_set_color_all(0, 0, 0);
for (uint8_t j = 0; j < RGB_MATRIX_LED_COUNT; ++j) {
- led[j] = (random8() & 2) ? (RGB){0, 0, 0} : hsv_to_rgb((HSV){random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v});
+ led[j] = (random8() & 2) ? (rgb_t){0, 0, 0} : hsv_to_rgb((hsv_t){random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v});
}
}
@@ -39,7 +39,7 @@ static bool PIXEL_FLOW(effect_params_t* params) {
led[j] = led[j + 1];
}
// Fill last LED
- led[led_max - 1] = (random8() & 2) ? (RGB){0, 0, 0} : hsv_to_rgb((HSV){random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v});
+ led[led_max - 1] = (random8() & 2) ? (rgb_t){0, 0, 0} : hsv_to_rgb((hsv_t){random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v});
// Set pulse timer
wait_timer = g_rgb_timer + interval();
}
diff --git a/quantum/rgb_matrix/animations/pixel_fractal_anim.h b/quantum/rgb_matrix/animations/pixel_fractal_anim.h
index 90a75ed321bb..bf5c22a64e43 100644
--- a/quantum/rgb_matrix/animations/pixel_fractal_anim.h
+++ b/quantum/rgb_matrix/animations/pixel_fractal_anim.h
@@ -26,11 +26,11 @@ static bool PIXEL_FRACTAL(effect_params_t* params) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
if (g_rgb_timer > wait_timer) {
- RGB rgb = rgb_matrix_hsv_to_rgb(rgb_matrix_config.hsv);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(rgb_matrix_config.hsv);
for (uint8_t h = 0; h < MATRIX_ROWS; ++h) {
// Light and copy columns outward
for (uint8_t l = 0; l < MID_COL - 1; ++l) {
- RGB index_rgb = led[h][l] ? (RGB){rgb.r, rgb.g, rgb.b} : (RGB){0, 0, 0};
+ rgb_t index_rgb = led[h][l] ? (rgb_t){rgb.r, rgb.g, rgb.b} : (rgb_t){0, 0, 0};
if (HAS_ANY_FLAGS(g_led_config.flags[g_led_config.matrix_co[h][l]], params->flags)) {
rgb_matrix_set_color(g_led_config.matrix_co[h][l], index_rgb.r, index_rgb.g, index_rgb.b);
}
@@ -41,7 +41,7 @@ static bool PIXEL_FRACTAL(effect_params_t* params) {
}
// Light both middle columns
- RGB index_rgb = led[h][MID_COL - 1] ? (RGB){rgb.r, rgb.g, rgb.b} : (RGB){0, 0, 0};
+ rgb_t index_rgb = led[h][MID_COL - 1] ? (rgb_t){rgb.r, rgb.g, rgb.b} : (rgb_t){0, 0, 0};
if (HAS_ANY_FLAGS(g_led_config.flags[g_led_config.matrix_co[h][MID_COL - 1]], params->flags)) {
rgb_matrix_set_color(g_led_config.matrix_co[h][MID_COL - 1], index_rgb.r, index_rgb.g, index_rgb.b);
}
diff --git a/quantum/rgb_matrix/animations/pixel_rain_anim.h b/quantum/rgb_matrix/animations/pixel_rain_anim.h
index 26cd73b57804..c0370831d80c 100644
--- a/quantum/rgb_matrix/animations/pixel_rain_anim.h
+++ b/quantum/rgb_matrix/animations/pixel_rain_anim.h
@@ -6,25 +6,20 @@ RGB_MATRIX_EFFECT(PIXEL_RAIN)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
static bool PIXEL_RAIN(effect_params_t* params) {
- static uint32_t wait_timer = 0;
+ static fast_timer_t timer = 0;
+ static uint16_t index = RGB_MATRIX_LED_COUNT + 1;
- inline uint32_t interval(void) {
- return 500 / scale16by8(qadd8(rgb_matrix_config.speed, 16), 16);
- }
-
- inline void rain_pixel(uint8_t led_index) {
- if (!HAS_ANY_FLAGS(g_led_config.flags[led_index], params->flags)) {
- return;
- }
- HSV hsv = (random8() & 2) ? (HSV){0, 0, 0} : (HSV){random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v};
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
- rgb_matrix_set_color(led_index, rgb.r, rgb.g, rgb.b);
- wait_timer = g_rgb_timer + interval();
+ if ((params->iter == 0) && (timer_elapsed_fast(timer) > (320 - rgb_matrix_config.speed))) {
+ index = random8_max(RGB_MATRIX_LED_COUNT);
+ timer = timer_read_fast();
}
RGB_MATRIX_USE_LIMITS(led_min, led_max);
- if (g_rgb_timer > wait_timer) {
- rain_pixel(random8_max(RGB_MATRIX_LED_COUNT));
+ if (led_min <= index && index < led_max && HAS_ANY_FLAGS(g_led_config.flags[index], params->flags)) {
+ hsv_t hsv = (random8() & 2) ? (hsv_t){0, 0, 0} : (hsv_t){random8(), random8_min_max(127, 255), rgb_matrix_config.hsv.v};
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
+ rgb_matrix_set_color(index, rgb.r, rgb.g, rgb.b);
+ index = RGB_MATRIX_LED_COUNT + 1;
}
return rgb_matrix_check_finished_leds(led_max);
}
diff --git a/quantum/rgb_matrix/animations/rainbow_beacon_anim.h b/quantum/rgb_matrix/animations/rainbow_beacon_anim.h
index bdcca5530fd4..3c7d8e59d236 100644
--- a/quantum/rgb_matrix/animations/rainbow_beacon_anim.h
+++ b/quantum/rgb_matrix/animations/rainbow_beacon_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(RAINBOW_BEACON)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV RAINBOW_BEACON_math(HSV hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time) {
+static hsv_t RAINBOW_BEACON_math(hsv_t hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time) {
hsv.h += ((g_led_config.point[i].y - k_rgb_matrix_center.y) * 2 * cos + (g_led_config.point[i].x - k_rgb_matrix_center.x) * 2 * sin) / 128;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/rainbow_moving_chevron_anim.h b/quantum/rgb_matrix/animations/rainbow_moving_chevron_anim.h
index f7b8f6c2f324..309ea829758e 100644
--- a/quantum/rgb_matrix/animations/rainbow_moving_chevron_anim.h
+++ b/quantum/rgb_matrix/animations/rainbow_moving_chevron_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(RAINBOW_MOVING_CHEVRON)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV RAINBOW_MOVING_CHEVRON_math(HSV hsv, uint8_t i, uint8_t time) {
+static hsv_t RAINBOW_MOVING_CHEVRON_math(hsv_t hsv, uint8_t i, uint8_t time) {
hsv.h += abs8(g_led_config.point[i].y - k_rgb_matrix_center.y) + (g_led_config.point[i].x - time);
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/rainbow_pinwheels_anim.h b/quantum/rgb_matrix/animations/rainbow_pinwheels_anim.h
index 91e31ea8cc0f..5d2558d492e0 100644
--- a/quantum/rgb_matrix/animations/rainbow_pinwheels_anim.h
+++ b/quantum/rgb_matrix/animations/rainbow_pinwheels_anim.h
@@ -2,7 +2,7 @@
RGB_MATRIX_EFFECT(RAINBOW_PINWHEELS)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV RAINBOW_PINWHEELS_math(HSV hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time) {
+static hsv_t RAINBOW_PINWHEELS_math(hsv_t hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time) {
hsv.h += ((g_led_config.point[i].y - k_rgb_matrix_center.y) * 3 * cos + (56 - abs8(g_led_config.point[i].x - k_rgb_matrix_center.x)) * 3 * sin) / 128;
return hsv;
}
diff --git a/quantum/rgb_matrix/animations/raindrops_anim.h b/quantum/rgb_matrix/animations/raindrops_anim.h
index e8e1f6de0439..a682156da241 100644
--- a/quantum/rgb_matrix/animations/raindrops_anim.h
+++ b/quantum/rgb_matrix/animations/raindrops_anim.h
@@ -4,7 +4,7 @@ RGB_MATRIX_EFFECT(RAINDROPS)
static void raindrops_set_color(int i, effect_params_t* params) {
if (!HAS_ANY_FLAGS(g_led_config.flags[i], params->flags)) return;
- HSV hsv = {0, rgb_matrix_config.hsv.s, rgb_matrix_config.hsv.v};
+ hsv_t hsv = {0, rgb_matrix_config.hsv.s, rgb_matrix_config.hsv.v};
// Take the shortest path between hues
int16_t deltaH = ((rgb_matrix_config.hsv.h + 180) % 360 - rgb_matrix_config.hsv.h) / 4;
@@ -14,8 +14,8 @@ static void raindrops_set_color(int i, effect_params_t* params) {
deltaH += 256;
}
- hsv.h = rgb_matrix_config.hsv.h + (deltaH * (random8() & 0x03));
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ hsv.h = rgb_matrix_config.hsv.h + (deltaH * (random8() & 0x03));
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
diff --git a/quantum/rgb_matrix/animations/riverflow_anim.h b/quantum/rgb_matrix/animations/riverflow_anim.h
index 195d15986db5..e9ef25f70ce4 100644
--- a/quantum/rgb_matrix/animations/riverflow_anim.h
+++ b/quantum/rgb_matrix/animations/riverflow_anim.h
@@ -4,18 +4,14 @@ RGB_MATRIX_EFFECT(RIVERFLOW)
// inspired by @PleasureTek's Massdrop Alt LED animation
-bool RIVERFLOW(effect_params_t* params) {
- RGB_MATRIX_USE_LIMITS(led_min, led_max);
- for (uint8_t i = led_min; i < led_max; i++) {
- RGB_MATRIX_TEST_LED_FLAGS();
- HSV hsv = rgb_matrix_config.hsv;
- uint16_t time = scale16by8(g_rgb_timer + (i * 315), rgb_matrix_config.speed / 8);
- hsv.v = scale8(abs8(sin8(time) - 128) * 2, hsv.v);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
- rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
- }
+hsv_t RIVERFLOW_math(hsv_t hsv, uint8_t i, uint8_t time) {
+ time = scale16by8(g_rgb_timer + (i * 315), rgb_matrix_config.speed / 8);
+ hsv.v = scale8(abs8(sin8(time) - 128) * 2, hsv.v);
+ return hsv;
+}
- return rgb_matrix_check_finished_leds(led_max);
+bool RIVERFLOW(effect_params_t* params) {
+ return effect_runner_i(params, &RIVERFLOW_math);
}
# endif // RGB_MATRIX_CUSTOM_EFFECT_IMPLS
diff --git a/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy.h b/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy.h
index 2ad0f22c287d..d43f1c0d7097 100644
--- a/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy.h
+++ b/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy.h
@@ -1,6 +1,6 @@
#pragma once
-typedef HSV (*dx_dy_f)(HSV hsv, int16_t dx, int16_t dy, uint8_t time);
+typedef hsv_t (*dx_dy_f)(hsv_t hsv, int16_t dx, int16_t dy, uint8_t time);
bool effect_runner_dx_dy(effect_params_t* params, dx_dy_f effect_func) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
@@ -10,7 +10,7 @@ bool effect_runner_dx_dy(effect_params_t* params, dx_dy_f effect_func) {
RGB_MATRIX_TEST_LED_FLAGS();
int16_t dx = g_led_config.point[i].x - k_rgb_matrix_center.x;
int16_t dy = g_led_config.point[i].y - k_rgb_matrix_center.y;
- RGB rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, dx, dy, time));
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, dx, dy, time));
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy_dist.h b/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy_dist.h
index bcae7c79b6b8..29fa42a0ed6d 100644
--- a/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy_dist.h
+++ b/quantum/rgb_matrix/animations/runners/effect_runner_dx_dy_dist.h
@@ -1,6 +1,6 @@
#pragma once
-typedef HSV (*dx_dy_dist_f)(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time);
+typedef hsv_t (*dx_dy_dist_f)(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint8_t time);
bool effect_runner_dx_dy_dist(effect_params_t* params, dx_dy_dist_f effect_func) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
@@ -11,7 +11,7 @@ bool effect_runner_dx_dy_dist(effect_params_t* params, dx_dy_dist_f effect_func)
int16_t dx = g_led_config.point[i].x - k_rgb_matrix_center.x;
int16_t dy = g_led_config.point[i].y - k_rgb_matrix_center.y;
uint8_t dist = sqrt16(dx * dx + dy * dy);
- RGB rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, dx, dy, dist, time));
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, dx, dy, dist, time));
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/runners/effect_runner_i.h b/quantum/rgb_matrix/animations/runners/effect_runner_i.h
index b4de2992b64a..670fd83ebece 100644
--- a/quantum/rgb_matrix/animations/runners/effect_runner_i.h
+++ b/quantum/rgb_matrix/animations/runners/effect_runner_i.h
@@ -1,6 +1,6 @@
#pragma once
-typedef HSV (*i_f)(HSV hsv, uint8_t i, uint8_t time);
+typedef hsv_t (*i_f)(hsv_t hsv, uint8_t i, uint8_t time);
bool effect_runner_i(effect_params_t* params, i_f effect_func) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
@@ -8,7 +8,7 @@ bool effect_runner_i(effect_params_t* params, i_f effect_func) {
uint8_t time = scale16by8(g_rgb_timer, qadd8(rgb_matrix_config.speed / 4, 1));
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
- RGB rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, i, time));
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, i, time));
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/runners/effect_runner_reactive.h b/quantum/rgb_matrix/animations/runners/effect_runner_reactive.h
index f9584d707191..958db170aedb 100644
--- a/quantum/rgb_matrix/animations/runners/effect_runner_reactive.h
+++ b/quantum/rgb_matrix/animations/runners/effect_runner_reactive.h
@@ -2,7 +2,7 @@
#ifdef RGB_MATRIX_KEYREACTIVE_ENABLED
-typedef HSV (*reactive_f)(HSV hsv, uint16_t offset);
+typedef hsv_t (*reactive_f)(hsv_t hsv, uint16_t offset);
bool effect_runner_reactive(effect_params_t* params, reactive_f effect_func) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
@@ -20,7 +20,7 @@ bool effect_runner_reactive(effect_params_t* params, reactive_f effect_func) {
}
uint16_t offset = scale16by8(tick, qadd8(rgb_matrix_config.speed, 1));
- RGB rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, offset));
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, offset));
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/runners/effect_runner_reactive_splash.h b/quantum/rgb_matrix/animations/runners/effect_runner_reactive_splash.h
index 41020eb47f82..2e18491450a3 100644
--- a/quantum/rgb_matrix/animations/runners/effect_runner_reactive_splash.h
+++ b/quantum/rgb_matrix/animations/runners/effect_runner_reactive_splash.h
@@ -2,7 +2,7 @@
#ifdef RGB_MATRIX_KEYREACTIVE_ENABLED
-typedef HSV (*reactive_splash_f)(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick);
+typedef hsv_t (*reactive_splash_f)(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick);
bool effect_runner_reactive_splash(uint8_t start, effect_params_t* params, reactive_splash_f effect_func) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
@@ -10,8 +10,8 @@ bool effect_runner_reactive_splash(uint8_t start, effect_params_t* params, react
uint8_t count = g_last_hit_tracker.count;
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
- HSV hsv = rgb_matrix_config.hsv;
- hsv.v = 0;
+ hsv_t hsv = rgb_matrix_config.hsv;
+ hsv.v = 0;
for (uint8_t j = start; j < count; j++) {
int16_t dx = g_led_config.point[i].x - g_last_hit_tracker.x[j];
int16_t dy = g_led_config.point[i].y - g_last_hit_tracker.y[j];
@@ -19,8 +19,8 @@ bool effect_runner_reactive_splash(uint8_t start, effect_params_t* params, react
uint16_t tick = scale16by8(g_last_hit_tracker.tick[j], qadd8(rgb_matrix_config.speed, 1));
hsv = effect_func(hsv, dx, dy, dist, tick);
}
- hsv.v = scale8(hsv.v, rgb_matrix_config.hsv.v);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ hsv.v = scale8(hsv.v, rgb_matrix_config.hsv.v);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/runners/effect_runner_sin_cos_i.h b/quantum/rgb_matrix/animations/runners/effect_runner_sin_cos_i.h
index 7776491d5125..b96530aa5f02 100644
--- a/quantum/rgb_matrix/animations/runners/effect_runner_sin_cos_i.h
+++ b/quantum/rgb_matrix/animations/runners/effect_runner_sin_cos_i.h
@@ -1,6 +1,6 @@
#pragma once
-typedef HSV (*sin_cos_i_f)(HSV hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time);
+typedef hsv_t (*sin_cos_i_f)(hsv_t hsv, int8_t sin, int8_t cos, uint8_t i, uint8_t time);
bool effect_runner_sin_cos_i(effect_params_t* params, sin_cos_i_f effect_func) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
@@ -10,7 +10,7 @@ bool effect_runner_sin_cos_i(effect_params_t* params, sin_cos_i_f effect_func) {
int8_t sin_value = sin8(time) - 128;
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
- RGB rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, cos_value, sin_value, i, time));
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(effect_func(rgb_matrix_config.hsv, cos_value, sin_value, i, time));
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
return rgb_matrix_check_finished_leds(led_max);
diff --git a/quantum/rgb_matrix/animations/solid_color_anim.h b/quantum/rgb_matrix/animations/solid_color_anim.h
index c8762dcbc2ef..82b0007df952 100644
--- a/quantum/rgb_matrix/animations/solid_color_anim.h
+++ b/quantum/rgb_matrix/animations/solid_color_anim.h
@@ -4,7 +4,7 @@ RGB_MATRIX_EFFECT(SOLID_COLOR)
bool SOLID_COLOR(effect_params_t* params) {
RGB_MATRIX_USE_LIMITS(led_min, led_max);
- RGB rgb = rgb_matrix_hsv_to_rgb(rgb_matrix_config.hsv);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(rgb_matrix_config.hsv);
for (uint8_t i = led_min; i < led_max; i++) {
RGB_MATRIX_TEST_LED_FLAGS();
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
diff --git a/quantum/rgb_matrix/animations/solid_reactive_anim.h b/quantum/rgb_matrix/animations/solid_reactive_anim.h
index e18ffb5f2b05..67f568ca385e 100644
--- a/quantum/rgb_matrix/animations/solid_reactive_anim.h
+++ b/quantum/rgb_matrix/animations/solid_reactive_anim.h
@@ -3,7 +3,7 @@
RGB_MATRIX_EFFECT(SOLID_REACTIVE)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV SOLID_REACTIVE_math(HSV hsv, uint16_t offset) {
+static hsv_t SOLID_REACTIVE_math(hsv_t hsv, uint16_t offset) {
# ifdef RGB_MATRIX_SOLID_REACTIVE_GRADIENT_MODE
hsv.h = scale16by8(g_rgb_timer, qadd8(rgb_matrix_config.speed, 8) >> 4);
# endif
diff --git a/quantum/rgb_matrix/animations/solid_reactive_cross.h b/quantum/rgb_matrix/animations/solid_reactive_cross.h
index a18d6b03dd6b..e52a7d8481fd 100644
--- a/quantum/rgb_matrix/animations/solid_reactive_cross.h
+++ b/quantum/rgb_matrix/animations/solid_reactive_cross.h
@@ -11,7 +11,7 @@ RGB_MATRIX_EFFECT(SOLID_REACTIVE_MULTICROSS)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV SOLID_REACTIVE_CROSS_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
+static hsv_t SOLID_REACTIVE_CROSS_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
uint16_t effect = tick + dist;
dx = dx < 0 ? dx * -1 : dx;
dy = dy < 0 ? dy * -1 : dy;
diff --git a/quantum/rgb_matrix/animations/solid_reactive_nexus.h b/quantum/rgb_matrix/animations/solid_reactive_nexus.h
index 53cc008616de..471a2682caab 100644
--- a/quantum/rgb_matrix/animations/solid_reactive_nexus.h
+++ b/quantum/rgb_matrix/animations/solid_reactive_nexus.h
@@ -11,7 +11,7 @@ RGB_MATRIX_EFFECT(SOLID_REACTIVE_MULTINEXUS)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV SOLID_REACTIVE_NEXUS_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
+static hsv_t SOLID_REACTIVE_NEXUS_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
uint16_t effect = tick - dist;
if (effect > 255) effect = 255;
if (dist > 72) effect = 255;
diff --git a/quantum/rgb_matrix/animations/solid_reactive_simple_anim.h b/quantum/rgb_matrix/animations/solid_reactive_simple_anim.h
index 7f4e48747a6c..f20f1b1fb6af 100644
--- a/quantum/rgb_matrix/animations/solid_reactive_simple_anim.h
+++ b/quantum/rgb_matrix/animations/solid_reactive_simple_anim.h
@@ -3,7 +3,7 @@
RGB_MATRIX_EFFECT(SOLID_REACTIVE_SIMPLE)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV SOLID_REACTIVE_SIMPLE_math(HSV hsv, uint16_t offset) {
+static hsv_t SOLID_REACTIVE_SIMPLE_math(hsv_t hsv, uint16_t offset) {
# ifdef RGB_MATRIX_SOLID_REACTIVE_GRADIENT_MODE
hsv.h = scale16by8(g_rgb_timer, qadd8(rgb_matrix_config.speed, 8) >> 4);
# endif
diff --git a/quantum/rgb_matrix/animations/solid_reactive_wide.h b/quantum/rgb_matrix/animations/solid_reactive_wide.h
index feca1266483d..b780c13d27ad 100644
--- a/quantum/rgb_matrix/animations/solid_reactive_wide.h
+++ b/quantum/rgb_matrix/animations/solid_reactive_wide.h
@@ -11,7 +11,7 @@ RGB_MATRIX_EFFECT(SOLID_REACTIVE_MULTIWIDE)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-static HSV SOLID_REACTIVE_WIDE_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
+static hsv_t SOLID_REACTIVE_WIDE_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
uint16_t effect = tick + dist * 5;
if (effect > 255) effect = 255;
# ifdef RGB_MATRIX_SOLID_REACTIVE_GRADIENT_MODE
diff --git a/quantum/rgb_matrix/animations/solid_splash_anim.h b/quantum/rgb_matrix/animations/solid_splash_anim.h
index 77d6f8c5eb0c..839ab05b3877 100644
--- a/quantum/rgb_matrix/animations/solid_splash_anim.h
+++ b/quantum/rgb_matrix/animations/solid_splash_anim.h
@@ -11,7 +11,7 @@ RGB_MATRIX_EFFECT(SOLID_MULTISPLASH)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-HSV SOLID_SPLASH_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
+hsv_t SOLID_SPLASH_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
uint16_t effect = tick - dist;
if (effect > 255) effect = 255;
hsv.v = qadd8(hsv.v, 255 - effect);
diff --git a/quantum/rgb_matrix/animations/splash_anim.h b/quantum/rgb_matrix/animations/splash_anim.h
index 06459e1b0a2e..a28cadb9f43e 100644
--- a/quantum/rgb_matrix/animations/splash_anim.h
+++ b/quantum/rgb_matrix/animations/splash_anim.h
@@ -11,7 +11,7 @@ RGB_MATRIX_EFFECT(MULTISPLASH)
# ifdef RGB_MATRIX_CUSTOM_EFFECT_IMPLS
-HSV SPLASH_math(HSV hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
+hsv_t SPLASH_math(hsv_t hsv, int16_t dx, int16_t dy, uint8_t dist, uint16_t tick) {
uint16_t effect = tick - dist;
if (effect > 255) effect = 255;
hsv.h += effect;
diff --git a/quantum/rgb_matrix/animations/starlight_anim.h b/quantum/rgb_matrix/animations/starlight_anim.h
index 91626a4663e9..742e843b575c 100644
--- a/quantum/rgb_matrix/animations/starlight_anim.h
+++ b/quantum/rgb_matrix/animations/starlight_anim.h
@@ -4,9 +4,9 @@ RGB_MATRIX_EFFECT(STARLIGHT)
void set_starlight_color(uint8_t i, effect_params_t* params) {
uint16_t time = scale16by8(g_rgb_timer, rgb_matrix_config.speed / 8);
- HSV hsv = rgb_matrix_config.hsv;
+ hsv_t hsv = rgb_matrix_config.hsv;
hsv.v = scale8(abs8(sin8(time) - 128) * 2, hsv.v);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
diff --git a/quantum/rgb_matrix/animations/starlight_dual_hue_anim.h b/quantum/rgb_matrix/animations/starlight_dual_hue_anim.h
index 5ef831476f32..50ce5d6ab478 100644
--- a/quantum/rgb_matrix/animations/starlight_dual_hue_anim.h
+++ b/quantum/rgb_matrix/animations/starlight_dual_hue_anim.h
@@ -4,10 +4,10 @@ RGB_MATRIX_EFFECT(STARLIGHT_DUAL_HUE)
void set_starlight_dual_hue_color(uint8_t i, effect_params_t* params) {
uint16_t time = scale16by8(g_rgb_timer, rgb_matrix_config.speed / 8);
- HSV hsv = rgb_matrix_config.hsv;
+ hsv_t hsv = rgb_matrix_config.hsv;
hsv.v = scale8(abs8(sin8(time) - 128) * 2, hsv.v);
hsv.h = hsv.h + random8_max((30 + 1 - -30) + -30);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
diff --git a/quantum/rgb_matrix/animations/starlight_dual_sat_anim.h b/quantum/rgb_matrix/animations/starlight_dual_sat_anim.h
index 1994aba8a8ad..6def4eea098b 100644
--- a/quantum/rgb_matrix/animations/starlight_dual_sat_anim.h
+++ b/quantum/rgb_matrix/animations/starlight_dual_sat_anim.h
@@ -4,10 +4,10 @@ RGB_MATRIX_EFFECT(STARLIGHT_DUAL_SAT)
void set_starlight_dual_sat_color(uint8_t i, effect_params_t* params) {
uint16_t time = scale16by8(g_rgb_timer, rgb_matrix_config.speed / 8);
- HSV hsv = rgb_matrix_config.hsv;
+ hsv_t hsv = rgb_matrix_config.hsv;
hsv.v = scale8(abs8(sin8(time) - 128) * 2, hsv.v);
hsv.s = hsv.s + random8_max((30 + 1 - -30) + -30);
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(i, rgb.r, rgb.g, rgb.b);
}
diff --git a/quantum/rgb_matrix/animations/typing_heatmap_anim.h b/quantum/rgb_matrix/animations/typing_heatmap_anim.h
index d09bdc463171..060673889184 100644
--- a/quantum/rgb_matrix/animations/typing_heatmap_anim.h
+++ b/quantum/rgb_matrix/animations/typing_heatmap_anim.h
@@ -82,8 +82,8 @@ bool TYPING_HEATMAP(effect_params_t* params) {
uint8_t val = g_rgb_frame_buffer[row][col];
if (!HAS_ANY_FLAGS(g_led_config.flags[g_led_config.matrix_co[row][col]], params->flags)) continue;
- HSV hsv = {170 - qsub8(val, 85), rgb_matrix_config.hsv.s, scale8((qadd8(170, val) - 170) * 3, rgb_matrix_config.hsv.v)};
- RGB rgb = rgb_matrix_hsv_to_rgb(hsv);
+ hsv_t hsv = {170 - qsub8(val, 85), rgb_matrix_config.hsv.s, scale8((qadd8(170, val) - 170) * 3, rgb_matrix_config.hsv.v)};
+ rgb_t rgb = rgb_matrix_hsv_to_rgb(hsv);
rgb_matrix_set_color(g_led_config.matrix_co[row][col], rgb.r, rgb.g, rgb.b);
if (decrease_heatmap_values) {
diff --git a/quantum/rgb_matrix/rgb_matrix.c b/quantum/rgb_matrix/rgb_matrix.c
index 70175f9d50e9..484d177546a6 100644
--- a/quantum/rgb_matrix/rgb_matrix.c
+++ b/quantum/rgb_matrix/rgb_matrix.c
@@ -35,7 +35,7 @@ const led_point_t k_rgb_matrix_center = {112, 32};
const led_point_t k_rgb_matrix_center = RGB_MATRIX_CENTER;
#endif
-__attribute__((weak)) RGB rgb_matrix_hsv_to_rgb(HSV hsv) {
+__attribute__((weak)) rgb_t rgb_matrix_hsv_to_rgb(hsv_t hsv) {
return hsv_to_rgb(hsv);
}
@@ -98,7 +98,7 @@ void eeconfig_update_rgb_matrix_default(void) {
dprintf("eeconfig_update_rgb_matrix_default\n");
rgb_matrix_config.enable = RGB_MATRIX_DEFAULT_ON;
rgb_matrix_config.mode = RGB_MATRIX_DEFAULT_MODE;
- rgb_matrix_config.hsv = (HSV){RGB_MATRIX_DEFAULT_HUE, RGB_MATRIX_DEFAULT_SAT, RGB_MATRIX_DEFAULT_VAL};
+ rgb_matrix_config.hsv = (hsv_t){RGB_MATRIX_DEFAULT_HUE, RGB_MATRIX_DEFAULT_SAT, RGB_MATRIX_DEFAULT_VAL};
rgb_matrix_config.speed = RGB_MATRIX_DEFAULT_SPD;
rgb_matrix_config.flags = RGB_MATRIX_DEFAULT_FLAGS;
eeconfig_flush_rgb_matrix(true);
@@ -143,8 +143,17 @@ void rgb_matrix_update_pwm_buffers(void) {
rgb_matrix_driver.flush();
}
+__attribute__((weak)) int rgb_matrix_led_index(int index) {
+#if defined(RGB_MATRIX_SPLIT)
+ if (!is_keyboard_left() && index >= k_rgb_matrix_split[0]) {
+ return index - k_rgb_matrix_split[0];
+ }
+#endif
+ return index;
+}
+
void rgb_matrix_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
- rgb_matrix_driver.set_color(index, red, green, blue);
+ rgb_matrix_driver.set_color(rgb_matrix_led_index(index), red, green, blue);
}
void rgb_matrix_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
@@ -404,7 +413,6 @@ struct rgb_matrix_limits_t rgb_matrix_get_limits(uint8_t iter) {
limits.led_min_index = RGB_MATRIX_LED_PROCESS_LIMIT * (iter);
limits.led_max_index = limits.led_min_index + RGB_MATRIX_LED_PROCESS_LIMIT;
if (limits.led_max_index > RGB_MATRIX_LED_COUNT) limits.led_max_index = RGB_MATRIX_LED_COUNT;
- uint8_t k_rgb_matrix_split[2] = RGB_MATRIX_SPLIT;
if (is_keyboard_left() && (limits.led_max_index > k_rgb_matrix_split[0])) limits.led_max_index = k_rgb_matrix_split[0];
if (!(is_keyboard_left()) && (limits.led_min_index < k_rgb_matrix_split[0])) limits.led_min_index = k_rgb_matrix_split[0];
# else
@@ -414,9 +422,8 @@ struct rgb_matrix_limits_t rgb_matrix_get_limits(uint8_t iter) {
# endif
#else
# if defined(RGB_MATRIX_SPLIT)
- limits.led_min_index = 0;
- limits.led_max_index = RGB_MATRIX_LED_COUNT;
- const uint8_t k_rgb_matrix_split[2] = RGB_MATRIX_SPLIT;
+ limits.led_min_index = 0;
+ limits.led_max_index = RGB_MATRIX_LED_COUNT;
if (is_keyboard_left() && (limits.led_max_index > k_rgb_matrix_split[0])) limits.led_max_index = k_rgb_matrix_split[0];
if (!(is_keyboard_left()) && (limits.led_min_index < k_rgb_matrix_split[0])) limits.led_min_index = k_rgb_matrix_split[0];
# else
@@ -584,7 +591,7 @@ void rgb_matrix_sethsv(uint16_t hue, uint8_t sat, uint8_t val) {
rgb_matrix_sethsv_eeprom_helper(hue, sat, val, true);
}
-HSV rgb_matrix_get_hsv(void) {
+hsv_t rgb_matrix_get_hsv(void) {
return rgb_matrix_config.hsv;
}
uint8_t rgb_matrix_get_hue(void) {
diff --git a/quantum/rgb_matrix/rgb_matrix.h b/quantum/rgb_matrix/rgb_matrix.h
index ceb3185d1a81..33f7e06a639e 100644
--- a/quantum/rgb_matrix/rgb_matrix.h
+++ b/quantum/rgb_matrix/rgb_matrix.h
@@ -145,6 +145,8 @@ void eeconfig_update_rgb_matrix(void);
uint8_t rgb_matrix_map_row_column_to_led_kb(uint8_t row, uint8_t column, uint8_t *led_i);
uint8_t rgb_matrix_map_row_column_to_led(uint8_t row, uint8_t column, uint8_t *led_i);
+int rgb_matrix_led_index(int index);
+
void rgb_matrix_set_color(int index, uint8_t red, uint8_t green, uint8_t blue);
void rgb_matrix_set_color_all(uint8_t red, uint8_t green, uint8_t blue);
@@ -184,7 +186,7 @@ void rgb_matrix_step_reverse(void);
void rgb_matrix_step_reverse_noeeprom(void);
void rgb_matrix_sethsv(uint16_t hue, uint8_t sat, uint8_t val);
void rgb_matrix_sethsv_noeeprom(uint16_t hue, uint8_t sat, uint8_t val);
-HSV rgb_matrix_get_hsv(void);
+hsv_t rgb_matrix_get_hsv(void);
uint8_t rgb_matrix_get_hue(void);
uint8_t rgb_matrix_get_sat(void);
uint8_t rgb_matrix_get_val(void);
@@ -210,6 +212,7 @@ void rgb_matrix_decrease_speed_noeeprom(void);
led_flags_t rgb_matrix_get_flags(void);
void rgb_matrix_set_flags(led_flags_t flags);
void rgb_matrix_set_flags_noeeprom(led_flags_t flags);
+void rgb_matrix_update_pwm_buffers(void);
#ifndef RGBLIGHT_ENABLE
# define eeconfig_update_rgblight_current eeconfig_update_rgb_matrix
diff --git a/quantum/rgb_matrix/rgb_matrix_drivers.c b/quantum/rgb_matrix/rgb_matrix_drivers.c
index bf5209a9d322..3b45e82cb919 100644
--- a/quantum/rgb_matrix/rgb_matrix_drivers.c
+++ b/quantum/rgb_matrix/rgb_matrix_drivers.c
@@ -146,61 +146,11 @@ const rgb_matrix_driver_t rgb_matrix_driver = {
# pragma message "You need to use a custom driver, or re-implement the WS2812 driver to use a different configuration."
# endif
-// LED color buffer
-rgb_led_t rgb_matrix_ws2812_array[WS2812_LED_COUNT];
-bool ws2812_dirty = false;
-
-static void init(void) {
- ws2812_init();
- ws2812_dirty = false;
-}
-
-static void flush(void) {
- if (ws2812_dirty) {
- ws2812_setleds(rgb_matrix_ws2812_array, WS2812_LED_COUNT);
- ws2812_dirty = false;
- }
-}
-
-// Set an led in the buffer to a color
-static inline void setled(int i, uint8_t r, uint8_t g, uint8_t b) {
-# if defined(RGB_MATRIX_SPLIT)
- const uint8_t k_rgb_matrix_split[2] = RGB_MATRIX_SPLIT;
- if (!is_keyboard_left()) {
- if (i >= k_rgb_matrix_split[0]) {
- i -= k_rgb_matrix_split[0];
- } else {
- return;
- }
- } else if (i >= k_rgb_matrix_split[0]) {
- return;
- }
-# endif
-
- if (rgb_matrix_ws2812_array[i].r == r && rgb_matrix_ws2812_array[i].g == g && rgb_matrix_ws2812_array[i].b == b) {
- return;
- }
-
- ws2812_dirty = true;
- rgb_matrix_ws2812_array[i].r = r;
- rgb_matrix_ws2812_array[i].g = g;
- rgb_matrix_ws2812_array[i].b = b;
-# ifdef WS2812_RGBW
- convert_rgb_to_rgbw(&rgb_matrix_ws2812_array[i]);
-# endif
-}
-
-static void setled_all(uint8_t r, uint8_t g, uint8_t b) {
- for (int i = 0; i < ARRAY_SIZE(rgb_matrix_ws2812_array); i++) {
- setled(i, r, g, b);
- }
-}
-
const rgb_matrix_driver_t rgb_matrix_driver = {
- .init = init,
- .flush = flush,
- .set_color = setled,
- .set_color_all = setled_all,
+ .init = ws2812_init,
+ .flush = ws2812_flush,
+ .set_color = ws2812_set_color,
+ .set_color_all = ws2812_set_color_all,
};
#endif
diff --git a/quantum/rgb_matrix/rgb_matrix_types.h b/quantum/rgb_matrix/rgb_matrix_types.h
index 0a3fd7cc0d11..0834a7067c4d 100644
--- a/quantum/rgb_matrix/rgb_matrix_types.h
+++ b/quantum/rgb_matrix/rgb_matrix_types.h
@@ -78,7 +78,7 @@ typedef union {
struct PACKED {
uint8_t enable : 2;
uint8_t mode : 6;
- HSV hsv;
+ hsv_t hsv;
uint8_t speed;
led_flags_t flags;
};
diff --git a/quantum/rgblight/rgblight.c b/quantum/rgblight/rgblight.c
index b0f2dfdc1d8b..ddccc9bae36d 100644
--- a/quantum/rgblight/rgblight.c
+++ b/quantum/rgblight/rgblight.c
@@ -115,11 +115,6 @@ static bool pre_suspend_enabled;
animation_status_t animation_status = {};
#endif
-#ifndef LED_ARRAY
-rgb_led_t led[RGBLIGHT_LED_COUNT];
-# define LED_ARRAY led
-#endif
-
#ifdef RGBLIGHT_LAYERS
rgblight_segment_t const *const *rgblight_layers = NULL;
@@ -141,27 +136,30 @@ void rgblight_set_effect_range(uint8_t start_pos, uint8_t num_leds) {
rgblight_ranges.effect_num_leds = num_leds;
}
-__attribute__((weak)) RGB rgblight_hsv_to_rgb(HSV hsv) {
+__attribute__((weak)) rgb_t rgblight_hsv_to_rgb(hsv_t hsv) {
return hsv_to_rgb(hsv);
}
-void setrgb(uint8_t r, uint8_t g, uint8_t b, rgb_led_t *led1) {
- led1->r = r;
- led1->g = g;
- led1->b = b;
-#ifdef WS2812_RGBW
- led1->w = 0;
+uint8_t rgblight_led_index(uint8_t index) {
+#if defined(RGBLIGHT_LED_MAP)
+ return pgm_read_byte(&led_map[index]) - rgblight_ranges.clipping_start_pos;
+#else
+ return index - rgblight_ranges.clipping_start_pos;
#endif
}
-void sethsv_raw(uint8_t hue, uint8_t sat, uint8_t val, rgb_led_t *led1) {
- HSV hsv = {hue, sat, val};
- RGB rgb = rgblight_hsv_to_rgb(hsv);
- setrgb(rgb.r, rgb.g, rgb.b, led1);
+void setrgb(uint8_t r, uint8_t g, uint8_t b, int index) {
+ rgblight_driver.set_color(rgblight_led_index(index), r, g, b);
}
-void sethsv(uint8_t hue, uint8_t sat, uint8_t val, rgb_led_t *led1) {
- sethsv_raw(hue, sat, val > RGBLIGHT_LIMIT_VAL ? RGBLIGHT_LIMIT_VAL : val, led1);
+void sethsv_raw(uint8_t hue, uint8_t sat, uint8_t val, int index) {
+ hsv_t hsv = {hue, sat, val};
+ rgb_t rgb = rgblight_hsv_to_rgb(hsv);
+ setrgb(rgb.r, rgb.g, rgb.b, index);
+}
+
+void sethsv(uint8_t hue, uint8_t sat, uint8_t val, int index) {
+ sethsv_raw(hue, sat, val > RGBLIGHT_LIMIT_VAL ? RGBLIGHT_LIMIT_VAL : val, index);
}
void rgblight_check_config(void) {
@@ -515,9 +513,8 @@ void rgblight_decrease_speed_noeeprom(void) {
void rgblight_sethsv_noeeprom_old(uint8_t hue, uint8_t sat, uint8_t val) {
if (rgblight_config.enable) {
- rgb_led_t tmp_led;
- sethsv(hue, sat, val, &tmp_led);
- rgblight_setrgb(tmp_led.r, tmp_led.g, tmp_led.b);
+ rgb_t rgb = hsv_to_rgb((hsv_t){hue, sat, val > RGBLIGHT_LIMIT_VAL ? RGBLIGHT_LIMIT_VAL : val});
+ rgblight_setrgb(rgb.r, rgb.g, rgb.b);
}
}
@@ -531,13 +528,12 @@ void rgblight_sethsv_eeprom_helper(uint8_t hue, uint8_t sat, uint8_t val, bool w
rgblight_status.base_mode = mode_base_table[rgblight_config.mode];
if (rgblight_config.mode == RGBLIGHT_MODE_STATIC_LIGHT) {
// same static color
- rgb_led_t tmp_led;
#ifdef RGBLIGHT_LAYERS_RETAIN_VAL
// needed for rgblight_layers_write() to get the new val, since it reads rgblight_config.val
rgblight_config.val = val;
#endif
- sethsv(hue, sat, val, &tmp_led);
- rgblight_setrgb(tmp_led.r, tmp_led.g, tmp_led.b);
+ rgb_t rgb = hsv_to_rgb((hsv_t){hue, sat, val > RGBLIGHT_LIMIT_VAL ? RGBLIGHT_LIMIT_VAL : val});
+ rgblight_setrgb(rgb.r, rgb.g, rgb.b);
} else {
// all LEDs in same color
if (1 == 0) { // dummy
@@ -575,7 +571,7 @@ void rgblight_sethsv_eeprom_helper(uint8_t hue, uint8_t sat, uint8_t val, bool w
_hue = hue - _hue;
}
dprintf("rgblight rainbow set hsv: %d,%d,%d,%u\n", i, _hue, direction, range);
- sethsv(_hue, sat, val, (rgb_led_t *)&led[i + rgblight_ranges.effect_start_pos]);
+ sethsv(_hue, sat, val, i + rgblight_ranges.effect_start_pos);
}
# ifdef RGBLIGHT_LAYERS_RETAIN_VAL
// needed for rgblight_layers_write() to get the new val, since it reads rgblight_config.val
@@ -639,8 +635,8 @@ uint8_t rgblight_get_val(void) {
return rgblight_config.val;
}
-HSV rgblight_get_hsv(void) {
- return (HSV){rgblight_config.hue, rgblight_config.sat, rgblight_config.val};
+hsv_t rgblight_get_hsv(void) {
+ return (hsv_t){rgblight_config.hue, rgblight_config.sat, rgblight_config.val};
}
void rgblight_setrgb(uint8_t r, uint8_t g, uint8_t b) {
@@ -649,12 +645,7 @@ void rgblight_setrgb(uint8_t r, uint8_t g, uint8_t b) {
}
for (uint8_t i = rgblight_ranges.effect_start_pos; i < rgblight_ranges.effect_end_pos; i++) {
- led[i].r = r;
- led[i].g = g;
- led[i].b = b;
-#ifdef WS2812_RGBW
- led[i].w = 0;
-#endif
+ rgblight_driver.set_color(rgblight_led_index(i), r, g, b);
}
rgblight_set();
}
@@ -664,12 +655,7 @@ void rgblight_setrgb_at(uint8_t r, uint8_t g, uint8_t b, uint8_t index) {
return;
}
- led[index].r = r;
- led[index].g = g;
- led[index].b = b;
-#ifdef WS2812_RGBW
- led[index].w = 0;
-#endif
+ rgblight_driver.set_color(rgblight_led_index(index), r, g, b);
rgblight_set();
}
@@ -678,9 +664,8 @@ void rgblight_sethsv_at(uint8_t hue, uint8_t sat, uint8_t val, uint8_t index) {
return;
}
- rgb_led_t tmp_led;
- sethsv(hue, sat, val, &tmp_led);
- rgblight_setrgb_at(tmp_led.r, tmp_led.g, tmp_led.b, index);
+ rgb_t rgb = hsv_to_rgb((hsv_t){hue, sat, val > RGBLIGHT_LIMIT_VAL ? RGBLIGHT_LIMIT_VAL : val});
+ rgblight_setrgb_at(rgb.r, rgb.g, rgb.b, index);
}
#if defined(RGBLIGHT_EFFECT_BREATHING) || defined(RGBLIGHT_EFFECT_RAINBOW_MOOD) || defined(RGBLIGHT_EFFECT_RAINBOW_SWIRL) || defined(RGBLIGHT_EFFECT_SNAKE) || defined(RGBLIGHT_EFFECT_KNIGHT) || defined(RGBLIGHT_EFFECT_TWINKLE)
@@ -701,12 +686,7 @@ void rgblight_setrgb_range(uint8_t r, uint8_t g, uint8_t b, uint8_t start, uint8
}
for (uint8_t i = start; i < end; i++) {
- led[i].r = r;
- led[i].g = g;
- led[i].b = b;
-#ifdef WS2812_RGBW
- led[i].w = 0;
-#endif
+ rgblight_driver.set_color(rgblight_led_index(i), r, g, b);
}
rgblight_set();
}
@@ -716,9 +696,8 @@ void rgblight_sethsv_range(uint8_t hue, uint8_t sat, uint8_t val, uint8_t start,
return;
}
- rgb_led_t tmp_led;
- sethsv(hue, sat, val, &tmp_led);
- rgblight_setrgb_range(tmp_led.r, tmp_led.g, tmp_led.b, start, end);
+ rgb_t rgb = hsv_to_rgb((hsv_t){hue, sat, val > RGBLIGHT_LIMIT_VAL ? RGBLIGHT_LIMIT_VAL : val});
+ rgblight_setrgb_range(rgb.r, rgb.g, rgb.b, start, end);
}
#ifndef RGBLIGHT_SPLIT
@@ -785,12 +764,12 @@ static void rgblight_layers_write(void) {
break; // No more segments
}
// Write segment.count LEDs
- rgb_led_t *const limit = &led[MIN(segment.index + segment.count, RGBLIGHT_LED_COUNT)];
- for (rgb_led_t *led_ptr = &led[segment.index]; led_ptr < limit; led_ptr++) {
+ int limit = MIN(segment.index + segment.count, RGBLIGHT_LED_COUNT);
+ for (int i = segment.index; i < limit; i++) {
# ifdef RGBLIGHT_LAYERS_RETAIN_VAL
- sethsv(segment.hue, segment.sat, current_val, led_ptr);
+ sethsv(segment.hue, segment.sat, current_val, i);
# else
- sethsv(segment.hue, segment.sat, segment.val, led_ptr);
+ sethsv(segment.hue, segment.sat, segment.val, i);
# endif
}
segment_ptr++;
@@ -897,17 +876,9 @@ void rgblight_wakeup(void) {
#endif
void rgblight_set(void) {
- rgb_led_t *start_led;
- uint8_t num_leds = rgblight_ranges.clipping_num_leds;
-
if (!rgblight_config.enable) {
for (uint8_t i = rgblight_ranges.effect_start_pos; i < rgblight_ranges.effect_end_pos; i++) {
- led[i].r = 0;
- led[i].g = 0;
- led[i].b = 0;
-#ifdef WS2812_RGBW
- led[i].w = 0;
-#endif
+ rgblight_driver.set_color(rgblight_led_index(i), 0, 0, 0);
}
}
@@ -923,22 +894,7 @@ void rgblight_set(void) {
}
#endif
-#ifdef RGBLIGHT_LED_MAP
- rgb_led_t led0[RGBLIGHT_LED_COUNT];
- for (uint8_t i = 0; i < RGBLIGHT_LED_COUNT; i++) {
- led0[i] = led[pgm_read_byte(&led_map[i])];
- }
- start_led = led0 + rgblight_ranges.clipping_start_pos;
-#else
- start_led = led + rgblight_ranges.clipping_start_pos;
-#endif
-
-#ifdef WS2812_RGBW
- for (uint8_t i = 0; i < num_leds; i++) {
- convert_rgb_to_rgbw(&start_led[i]);
- }
-#endif
- rgblight_driver.setleds(start_led, num_leds);
+ rgblight_driver.flush();
}
#ifdef RGBLIGHT_SPLIT
@@ -1222,7 +1178,7 @@ void rgblight_effect_rainbow_swirl(animation_status_t *anim) {
for (i = 0; i < rgblight_ranges.effect_num_leds; i++) {
hue = (RGBLIGHT_RAINBOW_SWIRL_RANGE / rgblight_ranges.effect_num_leds * i + anim->current_hue);
- sethsv(hue, rgblight_config.sat, rgblight_config.val, (rgb_led_t *)&led[i + rgblight_ranges.effect_start_pos]);
+ sethsv(hue, rgblight_config.sat, rgblight_config.val, i + rgblight_ranges.effect_start_pos);
}
rgblight_set();
@@ -1259,13 +1215,8 @@ void rgblight_effect_snake(animation_status_t *anim) {
# endif
for (i = 0; i < rgblight_ranges.effect_num_leds; i++) {
- rgb_led_t *ledp = led + i + rgblight_ranges.effect_start_pos;
- ledp->r = 0;
- ledp->g = 0;
- ledp->b = 0;
-# ifdef WS2812_RGBW
- ledp->w = 0;
-# endif
+ rgblight_driver.set_color(rgblight_led_index(i + rgblight_ranges.effect_start_pos), 0, 0, 0);
+
for (j = 0; j < RGBLIGHT_EFFECT_SNAKE_LENGTH; j++) {
k = pos + j * increment;
if (k > RGBLIGHT_LED_COUNT) {
@@ -1275,7 +1226,7 @@ void rgblight_effect_snake(animation_status_t *anim) {
k = k + rgblight_ranges.effect_num_leds;
}
if (i == k) {
- sethsv(rgblight_config.hue, rgblight_config.sat, (uint8_t)(rgblight_config.val * (RGBLIGHT_EFFECT_SNAKE_LENGTH - j) / RGBLIGHT_EFFECT_SNAKE_LENGTH), ledp);
+ sethsv(rgblight_config.hue, rgblight_config.sat, (uint8_t)(rgblight_config.val * (RGBLIGHT_EFFECT_SNAKE_LENGTH - j) / RGBLIGHT_EFFECT_SNAKE_LENGTH), i + rgblight_ranges.effect_start_pos);
}
}
}
@@ -1320,26 +1271,16 @@ void rgblight_effect_knight(animation_status_t *anim) {
# endif
// Set all the LEDs to 0
for (i = rgblight_ranges.effect_start_pos; i < rgblight_ranges.effect_end_pos; i++) {
- led[i].r = 0;
- led[i].g = 0;
- led[i].b = 0;
-# ifdef WS2812_RGBW
- led[i].w = 0;
-# endif
+ rgblight_driver.set_color(rgblight_led_index(i), 0, 0, 0);
}
// Determine which LEDs should be lit up
for (i = 0; i < RGBLIGHT_EFFECT_KNIGHT_LED_NUM; i++) {
cur = (i + RGBLIGHT_EFFECT_KNIGHT_OFFSET) % rgblight_ranges.effect_num_leds + rgblight_ranges.effect_start_pos;
if (i >= low_bound && i <= high_bound) {
- sethsv(rgblight_config.hue, rgblight_config.sat, rgblight_config.val, (rgb_led_t *)&led[cur]);
+ sethsv(rgblight_config.hue, rgblight_config.sat, rgblight_config.val, cur);
} else {
- led[cur].r = 0;
- led[cur].g = 0;
- led[cur].b = 0;
-# ifdef WS2812_RGBW
- led[cur].w = 0;
-# endif
+ rgblight_driver.set_color(rgblight_led_index(cur), 0, 0, 0);
}
}
rgblight_set();
@@ -1384,7 +1325,7 @@ void rgblight_effect_christmas(animation_status_t *anim) {
for (i = 0; i < rgblight_ranges.effect_num_leds; i++) {
uint8_t local_hue = (i / RGBLIGHT_EFFECT_CHRISTMAS_STEP) % 2 ? hue : hue_green - hue;
- sethsv(local_hue, rgblight_config.sat, val, (rgb_led_t *)&led[i + rgblight_ranges.effect_start_pos]);
+ sethsv(local_hue, rgblight_config.sat, val, i + rgblight_ranges.effect_start_pos);
}
rgblight_set();
@@ -1401,43 +1342,25 @@ void rgblight_effect_christmas(animation_status_t *anim) {
__attribute__((weak)) const uint16_t RGBLED_RGBTEST_INTERVALS[] PROGMEM = {1024};
void rgblight_effect_rgbtest(animation_status_t *anim) {
- static uint8_t maxval = 0;
- uint8_t g;
- uint8_t r;
- uint8_t b;
-
- if (maxval == 0) {
- rgb_led_t tmp_led;
- sethsv(0, 255, RGBLIGHT_LIMIT_VAL, &tmp_led);
- maxval = tmp_led.r;
- }
- g = r = b = 0;
- switch (anim->pos) {
- case 0:
- r = maxval;
- break;
- case 1:
- g = maxval;
- break;
- case 2:
- b = maxval;
- break;
- }
+ uint8_t val = rgblight_get_val();
+
+ uint8_t r = anim->pos & 1 ? val : 0;
+ uint8_t g = anim->pos & 2 ? val : 0;
+ uint8_t b = anim->pos & 4 ? val : 0;
rgblight_setrgb(r, g, b);
- anim->pos = (anim->pos + 1) % 3;
+ anim->pos = (anim->pos + 1) % 8;
}
#endif
#ifdef RGBLIGHT_EFFECT_ALTERNATING
void rgblight_effect_alternating(animation_status_t *anim) {
for (int i = 0; i < rgblight_ranges.effect_num_leds; i++) {
- rgb_led_t *ledp = led + i + rgblight_ranges.effect_start_pos;
if (i < rgblight_ranges.effect_num_leds / 2 && anim->pos) {
- sethsv(rgblight_config.hue, rgblight_config.sat, rgblight_config.val, ledp);
+ sethsv(rgblight_config.hue, rgblight_config.sat, rgblight_config.val, i + rgblight_ranges.effect_start_pos);
} else if (i >= rgblight_ranges.effect_num_leds / 2 && !anim->pos) {
- sethsv(rgblight_config.hue, rgblight_config.sat, rgblight_config.val, ledp);
+ sethsv(rgblight_config.hue, rgblight_config.sat, rgblight_config.val, i + rgblight_ranges.effect_start_pos);
} else {
- sethsv(rgblight_config.hue, rgblight_config.sat, 0, ledp);
+ sethsv(rgblight_config.hue, rgblight_config.sat, 0, i + rgblight_ranges.effect_start_pos);
}
}
rgblight_set();
@@ -1449,7 +1372,7 @@ void rgblight_effect_alternating(animation_status_t *anim) {
__attribute__((weak)) const uint8_t RGBLED_TWINKLE_INTERVALS[] PROGMEM = {30, 15, 5};
typedef struct PACKED {
- HSV hsv;
+ hsv_t hsv;
uint8_t life;
uint8_t max_life;
} TwinkleState;
@@ -1475,7 +1398,7 @@ void rgblight_effect_twinkle(animation_status_t *anim) {
for (uint8_t i = 0; i < rgblight_ranges.effect_num_leds; i++) {
TwinkleState *t = &(led_twinkle_state[i]);
- HSV * c = &(t->hsv);
+ hsv_t * c = &(t->hsv);
if (!random_color) {
c->h = rgblight_config.hue;
@@ -1504,8 +1427,7 @@ void rgblight_effect_twinkle(animation_status_t *anim) {
// This LED is off, and was NOT selected to start brightening
}
- rgb_led_t *ledp = led + i + rgblight_ranges.effect_start_pos;
- sethsv(c->h, c->s, c->v, ledp);
+ sethsv(c->h, c->s, c->v, i + rgblight_ranges.effect_start_pos);
}
rgblight_set();
diff --git a/quantum/rgblight/rgblight.h b/quantum/rgblight/rgblight.h
index 0ed67ff6e3df..f4b6e621e40b 100644
--- a/quantum/rgblight/rgblight.h
+++ b/quantum/rgblight/rgblight.h
@@ -169,7 +169,6 @@ enum RGBLIGHT_EFFECT_MODE {
#include "rgblight_drivers.h"
#include "progmem.h"
#include "eeconfig.h"
-#include "ws2812.h"
#include "color.h"
#ifdef RGBLIGHT_LAYERS
@@ -363,7 +362,7 @@ uint8_t rgblight_get_hue(void);
uint8_t rgblight_get_sat(void);
uint8_t rgblight_get_val(void);
bool rgblight_is_enabled(void);
-HSV rgblight_get_hsv(void);
+hsv_t rgblight_get_hsv(void);
/* === qmk_firmware (core)internal Functions === */
void rgblight_init(void);
diff --git a/quantum/rgblight/rgblight_drivers.c b/quantum/rgblight/rgblight_drivers.c
index 76e9031aec92..ef986ee13c55 100644
--- a/quantum/rgblight/rgblight_drivers.c
+++ b/quantum/rgblight/rgblight_drivers.c
@@ -7,24 +7,20 @@
# include "ws2812.h"
const rgblight_driver_t rgblight_driver = {
- .init = ws2812_init,
- .setleds = ws2812_setleds,
+ .init = ws2812_init,
+ .set_color = ws2812_set_color,
+ .set_color_all = ws2812_set_color_all,
+ .flush = ws2812_flush,
};
#elif defined(RGBLIGHT_APA102)
# include "apa102.h"
-// Temporary shim
-static void apa102_setleds(rgb_led_t *ledarray, uint16_t number_of_leds) {
- for (uint16_t i = 0; i < number_of_leds; i++) {
- apa102_set_color(i, ledarray[i].r, ledarray[i].g, ledarray[i].b);
- }
- apa102_flush();
-}
-
const rgblight_driver_t rgblight_driver = {
- .init = apa102_init,
- .setleds = apa102_setleds,
+ .init = apa102_init,
+ .set_color = apa102_set_color,
+ .set_color_all = apa102_set_color_all,
+ .flush = apa102_flush,
};
#endif
diff --git a/quantum/rgblight/rgblight_drivers.h b/quantum/rgblight/rgblight_drivers.h
index af28b918e17b..16fb4cebd638 100644
--- a/quantum/rgblight/rgblight_drivers.h
+++ b/quantum/rgblight/rgblight_drivers.h
@@ -4,11 +4,12 @@
#pragma once
#include
-#include "color.h"
typedef struct {
void (*init)(void);
- void (*setleds)(rgb_led_t *ledarray, uint16_t number_of_leds);
+ void (*set_color)(int index, uint8_t red, uint8_t green, uint8_t blue);
+ void (*set_color_all)(uint8_t red, uint8_t green, uint8_t blue);
+ void (*flush)(void);
} rgblight_driver_t;
extern const rgblight_driver_t rgblight_driver;
diff --git a/quantum/split_common/transactions.c b/quantum/split_common/transactions.c
index 6c1aeb284d3d..f66b2ad89fb5 100644
--- a/quantum/split_common/transactions.c
+++ b/quantum/split_common/transactions.c
@@ -733,7 +733,7 @@ static bool pointing_handlers_master(matrix_row_t master_matrix[], matrix_row_t
return okay;
}
-extern const pointing_device_driver_t pointing_device_driver;
+extern const pointing_device_driver_t *pointing_device_driver;
static void pointing_handlers_slave(matrix_row_t master_matrix[], matrix_row_t slave_matrix[]) {
# if defined(POINTING_DEVICE_LEFT)
@@ -753,18 +753,18 @@ static void pointing_handlers_slave(matrix_row_t master_matrix[], matrix_row_t s
last_exec = timer_read32();
# endif
- uint16_t temp_cpi = !pointing_device_driver.get_cpi ? 0 : pointing_device_driver.get_cpi(); // check for NULL
+ uint16_t temp_cpi = !pointing_device_driver->get_cpi ? 0 : pointing_device_driver->get_cpi(); // check for NULL
split_shared_memory_lock();
split_slave_pointing_sync_t pointing;
memcpy(&pointing, &split_shmem->pointing, sizeof(split_slave_pointing_sync_t));
split_shared_memory_unlock();
- if (pointing.cpi && pointing.cpi != temp_cpi && pointing_device_driver.set_cpi) {
- pointing_device_driver.set_cpi(pointing.cpi);
+ if (pointing.cpi && pointing.cpi != temp_cpi && pointing_device_driver->set_cpi) {
+ pointing_device_driver->set_cpi(pointing.cpi);
}
- pointing.report = pointing_device_driver.get_report((report_mouse_t){0});
+ pointing.report = pointing_device_driver->get_report((report_mouse_t){0});
// Now update the checksum given that the pointing has been written to
pointing.checksum = crc8(&pointing.report, sizeof(report_mouse_t));
diff --git a/quantum/util.h b/quantum/util.h
index 94d9f2231796..61ec7ac153f7 100644
--- a/quantum/util.h
+++ b/quantum/util.h
@@ -4,6 +4,7 @@
#pragma once
+#include "bits.h"
#include "bitwise.h"
// convert to string
diff --git a/tests/combo/combo_repress/config.h b/tests/combo/combo_repress/config.h
new file mode 100644
index 000000000000..61ba58177eb5
--- /dev/null
+++ b/tests/combo/combo_repress/config.h
@@ -0,0 +1,10 @@
+// Copyright 2024 @Filios92
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
+
+#define TAPPING_TERM 200
+
+#define COMBO_PROCESS_KEY_REPRESS
diff --git a/tests/combo/combo_repress/test.mk b/tests/combo/combo_repress/test.mk
new file mode 100644
index 000000000000..cc3f482f4bbc
--- /dev/null
+++ b/tests/combo/combo_repress/test.mk
@@ -0,0 +1,6 @@
+# Copyright 2024 @Filios92
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+COMBO_ENABLE = yes
+
+INTROSPECTION_KEYMAP_C = test_combos_repress.c
diff --git a/tests/combo/combo_repress/test_combo.cpp b/tests/combo/combo_repress/test_combo.cpp
new file mode 100644
index 000000000000..1488d5c1bdc0
--- /dev/null
+++ b/tests/combo/combo_repress/test_combo.cpp
@@ -0,0 +1,158 @@
+// Copyright 2024 @Filios92
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "keyboard_report_util.hpp"
+#include "quantum.h"
+#include "keycode.h"
+#include "test_common.h"
+#include "test_driver.hpp"
+#include "test_fixture.hpp"
+#include "test_keymap_key.hpp"
+
+using testing::_;
+using testing::InSequence;
+
+class ComboRepress : public TestFixture {};
+
+TEST_F(ComboRepress, combo_repress_tapped) {
+ TestDriver driver;
+ KeymapKey key_f(0, 0, 0, KC_F);
+ KeymapKey key_g(0, 0, 1, KC_G);
+ set_keymap({key_f, key_g});
+
+ EXPECT_REPORT(driver, (KC_LEFT_ALT)).Times(2);
+ EXPECT_REPORT(driver, (KC_TAB, KC_LEFT_ALT));
+ EXPECT_EMPTY_REPORT(driver);
+ tap_combo({key_f, key_g}, 20);
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(ComboRepress, combo_repress_held_released_one_key_and_repressed) {
+ TestDriver driver;
+ KeymapKey key_f(0, 0, 0, KC_F);
+ KeymapKey key_g(0, 0, 1, KC_G);
+ KeymapKey key_h(0, 0, 2, KC_H);
+ KeymapKey key_j(0, 0, 3, KC_J);
+ set_keymap({key_f, key_g, key_h, key_j});
+
+ /* Press combo F+G */
+ EXPECT_REPORT(driver, (KC_LEFT_ALT)).Times(2);
+ EXPECT_REPORT(driver, (KC_TAB, KC_LEFT_ALT));
+ key_f.press();
+ run_one_scan_loop();
+ key_g.press();
+ run_one_scan_loop();
+ idle_for(COMBO_TERM + 1);
+ VERIFY_AND_CLEAR(driver);
+
+ /* Release G */
+ EXPECT_NO_REPORT(driver);
+ key_g.release();
+ idle_for(80);
+ VERIFY_AND_CLEAR(driver);
+
+ /* Tap G */
+ EXPECT_REPORT(driver, (KC_TAB, KC_LEFT_ALT));
+ EXPECT_REPORT(driver, (KC_LEFT_ALT));
+ tap_key(key_g, TAPPING_TERM + 1);
+ VERIFY_AND_CLEAR(driver);
+
+ /* Tap G, but hold for longer */
+ EXPECT_REPORT(driver, (KC_TAB, KC_LEFT_ALT));
+ EXPECT_REPORT(driver, (KC_LEFT_ALT));
+ tap_key(key_g, TAPPING_TERM * 2);
+ VERIFY_AND_CLEAR(driver);
+
+ idle_for(500);
+
+ /* Tap other combo while holding F */
+ EXPECT_REPORT(driver, (KC_ESCAPE, KC_LEFT_ALT));
+ EXPECT_REPORT(driver, (KC_LEFT_ALT));
+ tap_combo({key_h, key_j}, TAPPING_TERM + 1);
+ VERIFY_AND_CLEAR(driver);
+
+ /* G press and hold */
+ EXPECT_REPORT(driver, (KC_TAB, KC_LEFT_ALT));
+ EXPECT_REPORT(driver, (KC_LEFT_ALT));
+ key_g.press();
+ run_one_scan_loop();
+ VERIFY_AND_CLEAR(driver);
+
+ /* F release and tap */
+ EXPECT_REPORT(driver, (KC_LEFT_ALT, KC_LEFT_SHIFT)).Times(2);
+ EXPECT_REPORT(driver, (KC_TAB, KC_LEFT_ALT, KC_LEFT_SHIFT));
+ EXPECT_REPORT(driver, (KC_LEFT_ALT));
+ key_f.release();
+ run_one_scan_loop();
+ tap_key(key_f);
+ VERIFY_AND_CLEAR(driver);
+
+ /* Release G */
+ EXPECT_EMPTY_REPORT(driver);
+ key_g.release();
+ run_one_scan_loop();
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(ComboRepress, combo_repress_normal_combo) {
+ TestDriver driver;
+ KeymapKey key_f(0, 0, 0, KC_F);
+ KeymapKey key_g(0, 0, 1, KC_G);
+ KeymapKey key_h(0, 0, 2, KC_H);
+ KeymapKey key_j(0, 0, 3, KC_J);
+ set_keymap({key_f, key_g, key_h, key_j});
+
+ /* Press combo H+J */
+ EXPECT_REPORT(driver, (KC_ESCAPE));
+ key_h.press();
+ run_one_scan_loop();
+ key_j.press();
+ run_one_scan_loop();
+ idle_for(COMBO_TERM + 10);
+ VERIFY_AND_CLEAR(driver);
+
+ /* Release H */
+ EXPECT_NO_REPORT(driver);
+ key_h.release();
+ idle_for(80);
+ VERIFY_AND_CLEAR(driver);
+
+ /* Tap H */
+ EXPECT_REPORT(driver, (KC_H, KC_ESCAPE));
+ EXPECT_REPORT(driver, (KC_ESCAPE));
+ tap_key(key_h);
+ VERIFY_AND_CLEAR(driver);
+
+ /* Tap H, but hold for longer */
+ EXPECT_REPORT(driver, (KC_H, KC_ESCAPE));
+ EXPECT_REPORT(driver, (KC_ESCAPE));
+ tap_key(key_h, TAPPING_TERM + 1);
+ VERIFY_AND_CLEAR(driver);
+
+ idle_for(500);
+
+ /* Tap other combo while holding K */
+ EXPECT_REPORT(driver, (KC_ESCAPE, KC_LEFT_ALT)).Times(2);
+ EXPECT_REPORT(driver, (KC_ESCAPE, KC_TAB, KC_LEFT_ALT));
+ EXPECT_REPORT(driver, (KC_ESCAPE));
+ tap_combo({key_f, key_g}, TAPPING_TERM + 1);
+ VERIFY_AND_CLEAR(driver);
+
+ /* H press and hold */
+ EXPECT_REPORT(driver, (KC_H, KC_ESCAPE));
+ key_h.press();
+ run_one_scan_loop();
+ VERIFY_AND_CLEAR(driver);
+
+ /* J release and tap */
+ EXPECT_REPORT(driver, (KC_H));
+ key_j.release();
+ run_one_scan_loop();
+ VERIFY_AND_CLEAR(driver);
+
+ /* Release G */
+ EXPECT_EMPTY_REPORT(driver);
+ key_h.release();
+ run_one_scan_loop();
+ VERIFY_AND_CLEAR(driver);
+}
diff --git a/tests/combo/combo_repress/test_combos_repress.c b/tests/combo/combo_repress/test_combos_repress.c
new file mode 100644
index 000000000000..73fa77b0aabe
--- /dev/null
+++ b/tests/combo/combo_repress/test_combos_repress.c
@@ -0,0 +1,43 @@
+// Copyright 2024 @Filios92
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include "quantum.h"
+
+enum combos { alttab, esc };
+
+uint16_t const alttab_combo[] = {KC_F, KC_G, COMBO_END};
+uint16_t const esc_combo[] = {KC_H, KC_J, COMBO_END};
+
+// clang-format off
+combo_t key_combos[] = {
+ [alttab] = COMBO(alttab_combo, KC_NO),
+ [esc] = COMBO(esc_combo, KC_ESC)
+};
+// clang-format on
+
+void process_combo_event(uint16_t combo_index, bool pressed) {
+ switch (combo_index) {
+ case alttab:
+ if (pressed) {
+ register_mods(MOD_LALT);
+ tap_code(KC_TAB);
+ } else {
+ unregister_mods(MOD_LALT);
+ }
+ break;
+ }
+}
+
+bool process_combo_key_repress(uint16_t combo_index, combo_t *combo, uint8_t key_index, uint16_t keycode) {
+ switch (combo_index) {
+ case alttab:
+ switch (keycode) {
+ case KC_F:
+ tap_code16(S(KC_TAB));
+ return true;
+ case KC_G:
+ tap_code(KC_TAB);
+ return true;
+ }
+ }
+ return false;
+}
diff --git a/tests/layer_lock/config.h b/tests/layer_lock/config.h
new file mode 100644
index 000000000000..25d0b20c0ead
--- /dev/null
+++ b/tests/layer_lock/config.h
@@ -0,0 +1,8 @@
+// Copyright 2021 Christopher Courtney, aka Drashna Jael're (@drashna)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
+
+#define LAYER_LOCK_IDLE_TIMEOUT 1000
diff --git a/tests/layer_lock/test.mk b/tests/layer_lock/test.mk
new file mode 100644
index 000000000000..05771e4dbf89
--- /dev/null
+++ b/tests/layer_lock/test.mk
@@ -0,0 +1,8 @@
+# Copyright 2021 Christopher Courtney, aka Drashna Jael're (@drashna)
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# --------------------------------------------------------------------------------
+# Keep this file, even if it is empty, as a marker that this folder contains tests
+# --------------------------------------------------------------------------------
+
+LAYER_LOCK_ENABLE = yes
diff --git a/tests/layer_lock/test_layer_lock.cpp b/tests/layer_lock/test_layer_lock.cpp
new file mode 100644
index 000000000000..00742c3b4361
--- /dev/null
+++ b/tests/layer_lock/test_layer_lock.cpp
@@ -0,0 +1,284 @@
+// Copyright 2021 Christopher Courtney, aka Drashna Jael're (@drashna)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "keycodes.h"
+#include "test_common.hpp"
+
+using testing::_;
+
+class LayerLock : public TestFixture {};
+
+TEST_F(LayerLock, LayerLockState) {
+ TestDriver driver;
+ KeymapKey key_a = KeymapKey(0, 0, 0, KC_A);
+ KeymapKey key_b = KeymapKey(1, 0, 0, KC_B);
+ KeymapKey key_c = KeymapKey(2, 0, 0, KC_C);
+ KeymapKey key_d = KeymapKey(3, 0, 0, KC_C);
+
+ set_keymap({key_a, key_b, key_c, key_d});
+
+ EXPECT_FALSE(is_layer_locked(1));
+ EXPECT_FALSE(is_layer_locked(2));
+ EXPECT_FALSE(is_layer_locked(3));
+
+ layer_lock_invert(1); // Layer 1: unlocked -> locked
+ layer_lock_on(2); // Layer 2: unlocked -> locked
+ layer_lock_off(3); // Layer 3: stays unlocked
+
+ // Layers 1 and 2 are now on.
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(layer_state_is(2));
+ // Layers 1 and 2 are now locked.
+ EXPECT_TRUE(is_layer_locked(1));
+ EXPECT_TRUE(is_layer_locked(2));
+ EXPECT_FALSE(is_layer_locked(3));
+
+ layer_lock_invert(1); // Layer 1: locked -> unlocked
+ layer_lock_on(2); // Layer 2: stays locked
+ layer_lock_on(3); // Layer 3: unlocked -> locked
+
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_TRUE(layer_state_is(2));
+ EXPECT_TRUE(layer_state_is(3));
+ EXPECT_FALSE(is_layer_locked(1));
+ EXPECT_TRUE(is_layer_locked(2));
+ EXPECT_TRUE(is_layer_locked(3));
+
+ layer_lock_invert(1); // Layer 1: unlocked -> locked
+ layer_lock_off(2); // Layer 2: locked -> unlocked
+
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_FALSE(layer_state_is(2));
+ EXPECT_TRUE(layer_state_is(3));
+ EXPECT_TRUE(is_layer_locked(1));
+ EXPECT_FALSE(is_layer_locked(2));
+ EXPECT_TRUE(is_layer_locked(3));
+
+ layer_lock_all_off(); // Layers 1 and 3: locked -> unlocked
+
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(layer_state_is(2));
+ EXPECT_FALSE(layer_state_is(3));
+ EXPECT_FALSE(is_layer_locked(1));
+ EXPECT_FALSE(is_layer_locked(2));
+ EXPECT_FALSE(is_layer_locked(3));
+}
+
+TEST_F(LayerLock, LayerLockMomentaryTest) {
+ TestDriver driver;
+ KeymapKey key_layer = KeymapKey(0, 0, 0, MO(1));
+ KeymapKey key_a = KeymapKey(0, 1, 0, KC_A);
+ KeymapKey key_trns = KeymapKey(1, 0, 0, KC_TRNS);
+ KeymapKey key_ll = KeymapKey(1, 1, 0, QK_LAYER_LOCK);
+
+ set_keymap({key_layer, key_a, key_trns, key_ll});
+
+ EXPECT_NO_REPORT(driver);
+ key_layer.press();
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ tap_key(key_ll);
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ key_layer.release();
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ // Pressing Layer Lock again unlocks the lock.
+ EXPECT_NO_REPORT(driver);
+ key_ll.press();
+ run_one_scan_loop();
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(LayerLock, LayerLockLayerTapTest) {
+ TestDriver driver;
+ KeymapKey key_layer = KeymapKey(0, 0, 0, LT(1, KC_B));
+ KeymapKey key_a = KeymapKey(0, 1, 0, KC_A);
+ KeymapKey key_trns = KeymapKey(1, 0, 0, KC_TRNS);
+ KeymapKey key_ll = KeymapKey(1, 1, 0, QK_LAYER_LOCK);
+
+ set_keymap({key_layer, key_a, key_trns, key_ll});
+
+ EXPECT_NO_REPORT(driver);
+ key_layer.press();
+ idle_for(TAPPING_TERM);
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ tap_key(key_ll);
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ // Pressing Layer Lock again unlocks the lock.
+ EXPECT_NO_REPORT(driver);
+ key_ll.press();
+ run_one_scan_loop();
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(LayerLock, LayerLockOneshotTapTest) {
+ TestDriver driver;
+ KeymapKey key_layer = KeymapKey(0, 0, 0, OSL(1));
+ KeymapKey key_a = KeymapKey(0, 1, 0, KC_A);
+ KeymapKey key_trns = KeymapKey(1, 0, 0, KC_TRNS);
+ KeymapKey key_ll = KeymapKey(1, 1, 0, QK_LAYER_LOCK);
+
+ set_keymap({key_layer, key_a, key_trns, key_ll});
+
+ EXPECT_NO_REPORT(driver);
+ tap_key(key_layer);
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ tap_key(key_ll);
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ // Pressing Layer Lock again unlocks the lock.
+ EXPECT_NO_REPORT(driver);
+ key_ll.press();
+ run_one_scan_loop();
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(LayerLock, LayerLockOneshotHoldTest) {
+ TestDriver driver;
+ KeymapKey key_layer = KeymapKey(0, 0, 0, OSL(1));
+ KeymapKey key_a = KeymapKey(0, 1, 0, KC_A);
+ KeymapKey key_trns = KeymapKey(1, 0, 0, KC_TRNS);
+ KeymapKey key_ll = KeymapKey(1, 1, 0, QK_LAYER_LOCK);
+
+ set_keymap({key_layer, key_a, key_trns, key_ll});
+
+ EXPECT_NO_REPORT(driver);
+ key_layer.press();
+ idle_for(TAPPING_TERM);
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ tap_key(key_ll);
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ key_layer.release();
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ // Pressing Layer Lock again unlocks the lock.
+ EXPECT_NO_REPORT(driver);
+ key_ll.press();
+ run_one_scan_loop();
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(LayerLock, LayerLockTimeoutTest) {
+ TestDriver driver;
+ KeymapKey key_layer = KeymapKey(0, 0, 0, MO(1));
+ KeymapKey key_a = KeymapKey(0, 1, 0, KC_A);
+ KeymapKey key_trns = KeymapKey(1, 0, 0, KC_TRNS);
+ KeymapKey key_ll = KeymapKey(1, 1, 0, QK_LAYER_LOCK);
+
+ set_keymap({key_layer, key_a, key_trns, key_ll});
+
+ EXPECT_NO_REPORT(driver);
+ key_layer.press();
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ tap_key(key_ll);
+ EXPECT_TRUE(layer_state_is(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ key_layer.release();
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ idle_for(LAYER_LOCK_IDLE_TIMEOUT);
+ run_one_scan_loop();
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(LayerLock, ToKeyOverridesLayerLock) {
+ TestDriver driver;
+ KeymapKey key_layer = KeymapKey(0, 0, 0, MO(1));
+ KeymapKey key_to0 = KeymapKey(1, 0, 0, TO(0));
+ KeymapKey key_ll = KeymapKey(1, 1, 0, QK_LAYER_LOCK);
+
+ set_keymap({key_layer, key_to0, key_ll});
+
+ EXPECT_NO_REPORT(driver);
+ layer_lock_on(1);
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_NO_REPORT(driver);
+ tap_key(key_to0); // TO(0) overrides Layer Lock and unlocks layer 1.
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(LayerLock, LayerClearOverridesLayerLock) {
+ TestDriver driver;
+ KeymapKey key_layer = KeymapKey(0, 0, 0, MO(1));
+ KeymapKey key_a = KeymapKey(0, 1, 0, KC_A);
+ KeymapKey key_ll = KeymapKey(1, 1, 0, QK_LAYER_LOCK);
+
+ set_keymap({key_layer, key_a, key_ll});
+
+ EXPECT_NO_REPORT(driver);
+ layer_lock_on(1);
+ run_one_scan_loop();
+ EXPECT_TRUE(layer_state_is(1));
+ EXPECT_TRUE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+
+ EXPECT_REPORT(driver, (KC_A));
+ layer_clear(); // layer_clear() overrides Layer Lock and unlocks layer 1.
+ key_a.press();
+ run_one_scan_loop();
+ EXPECT_FALSE(layer_state_is(1));
+ EXPECT_FALSE(is_layer_locked(1));
+ VERIFY_AND_CLEAR(driver);
+}
diff --git a/tests/mousekeys/config.h b/tests/mousekeys/config.h
new file mode 100644
index 000000000000..76bbbe8daea8
--- /dev/null
+++ b/tests/mousekeys/config.h
@@ -0,0 +1,6 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
diff --git a/tests/mousekeys/test.mk b/tests/mousekeys/test.mk
new file mode 100644
index 000000000000..6c605daecf53
--- /dev/null
+++ b/tests/mousekeys/test.mk
@@ -0,0 +1 @@
+MOUSEKEY_ENABLE = yes
diff --git a/tests/mousekeys/test_mousekeys.cpp b/tests/mousekeys/test_mousekeys.cpp
new file mode 100644
index 000000000000..a1b8e06cf7a3
--- /dev/null
+++ b/tests/mousekeys/test_mousekeys.cpp
@@ -0,0 +1,109 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "gtest/gtest.h"
+#include "mouse_report_util.hpp"
+#include "test_common.hpp"
+
+using testing::_;
+
+struct MouseKeyExpectations {
+ int16_t x;
+ int16_t y;
+ int16_t h;
+ int16_t v;
+ uint16_t button_mask;
+};
+
+class Mousekey : public TestFixture {};
+class MousekeyParametrized : public ::testing::WithParamInterface>, public Mousekey {};
+
+TEST_F(Mousekey, SendMouseNotCalledWhenNoKeyIsPressed) {
+ TestDriver driver;
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+}
+
+TEST_F(Mousekey, PressAndHoldCursorUpIsCorrectlyReported) {
+ TestDriver driver;
+ KeymapKey mouse_key = KeymapKey{0, 0, 0, QK_MOUSE_CURSOR_UP};
+
+ set_keymap({mouse_key});
+
+ EXPECT_MOUSE_REPORT(driver, (0, -8, 0, 0, 0));
+ mouse_key.press();
+ run_one_scan_loop();
+
+ EXPECT_MOUSE_REPORT(driver, (0, -2, 0, 0, 0));
+ idle_for(MOUSEKEY_INTERVAL);
+
+ EXPECT_EMPTY_MOUSE_REPORT(driver);
+ mouse_key.release();
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(Mousekey, PressAndHoldButtonOneCorrectlyReported) {
+ TestDriver driver;
+ KeymapKey mouse_key = KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_1};
+
+ set_keymap({mouse_key});
+
+ EXPECT_MOUSE_REPORT(driver, (0, 0, 0, 0, 1));
+ mouse_key.press();
+ run_one_scan_loop();
+
+ idle_for(MOUSEKEY_INTERVAL);
+
+ EXPECT_EMPTY_MOUSE_REPORT(driver);
+ mouse_key.release();
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_P(MousekeyParametrized, PressAndReleaseIsCorrectlyReported) {
+ TestDriver driver;
+ KeymapKey mouse_key = GetParam().first;
+ MouseKeyExpectations expectations = GetParam().second;
+
+ set_keymap({mouse_key});
+
+ EXPECT_MOUSE_REPORT(driver, (expectations.x, expectations.y, expectations.h, expectations.v, expectations.button_mask));
+ mouse_key.press();
+ run_one_scan_loop();
+
+ EXPECT_EMPTY_MOUSE_REPORT(driver);
+ mouse_key.release();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+// clang-format off
+INSTANTIATE_TEST_CASE_P(
+ Keys,
+ MousekeyParametrized,
+ ::testing::Values(
+ // Key , X, Y, H, V, Buttons Mask
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_1}, MouseKeyExpectations{ 0, 0, 0, 0, 1}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_2}, MouseKeyExpectations{ 0, 0, 0, 0, 2}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_3}, MouseKeyExpectations{ 0, 0, 0, 0, 4}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_4}, MouseKeyExpectations{ 0, 0, 0, 0, 8}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_5}, MouseKeyExpectations{ 0, 0, 0, 0, 16}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_6}, MouseKeyExpectations{ 0, 0, 0, 0, 32}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_7}, MouseKeyExpectations{ 0, 0, 0, 0, 64}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_8}, MouseKeyExpectations{ 0, 0, 0, 0, 128}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_CURSOR_UP}, MouseKeyExpectations{ 0,-8, 0, 0, 0}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_CURSOR_DOWN}, MouseKeyExpectations{ 0, 8, 0, 0, 0}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_CURSOR_LEFT}, MouseKeyExpectations{-8, 0, 0, 0, 0}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_CURSOR_RIGHT}, MouseKeyExpectations{ 8, 0, 0, 0, 0}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_WHEEL_UP}, MouseKeyExpectations{ 0, 0, 0, 1, 0}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_WHEEL_DOWN}, MouseKeyExpectations{ 0, 0, 0,-1, 0}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_WHEEL_LEFT}, MouseKeyExpectations{ 0, 0,-1, 0, 0}),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_WHEEL_RIGHT}, MouseKeyExpectations{ 0, 0, 1, 0, 0})
+ ));
+// clang-format on
diff --git a/tests/pointing/config.h b/tests/pointing/config.h
new file mode 100644
index 000000000000..76bbbe8daea8
--- /dev/null
+++ b/tests/pointing/config.h
@@ -0,0 +1,6 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
diff --git a/tests/pointing/invertandrotate/config.h b/tests/pointing/invertandrotate/config.h
new file mode 100644
index 000000000000..a3f3df7a54e8
--- /dev/null
+++ b/tests/pointing/invertandrotate/config.h
@@ -0,0 +1,9 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
+
+#define POINTING_DEVICE_INVERT_X
+#define POINTING_DEVICE_ROTATION_90
diff --git a/tests/pointing/invertandrotate/test.mk b/tests/pointing/invertandrotate/test.mk
new file mode 100644
index 000000000000..ba224d74f0ab
--- /dev/null
+++ b/tests/pointing/invertandrotate/test.mk
@@ -0,0 +1,2 @@
+POINTING_DEVICE_ENABLE = yes
+POINTING_DEVICE_DRIVER = custom
diff --git a/tests/pointing/invertandrotate/test_invertandrotate.cpp b/tests/pointing/invertandrotate/test_invertandrotate.cpp
new file mode 100644
index 000000000000..b47739f415b7
--- /dev/null
+++ b/tests/pointing/invertandrotate/test_invertandrotate.cpp
@@ -0,0 +1,59 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "gtest/gtest.h"
+#include "mouse_report_util.hpp"
+#include "test_common.hpp"
+#include "test_pointing_device_driver.h"
+
+using testing::_;
+
+struct SimpleReport {
+ int16_t x;
+ int16_t y;
+ int16_t h;
+ int16_t v;
+};
+
+class Pointing : public TestFixture {};
+class PointingInvertAndRotateParametrized : public ::testing::WithParamInterface>, public Pointing {};
+
+TEST_P(PointingInvertAndRotateParametrized, PointingInvertAndRotateOrder) {
+ TestDriver driver;
+ SimpleReport input = GetParam().first;
+ SimpleReport expectations = GetParam().second;
+
+ pd_set_x(input.x);
+ pd_set_y(input.y);
+ pd_set_h(input.h);
+ pd_set_v(input.v);
+
+ EXPECT_MOUSE_REPORT(driver, (expectations.x, expectations.y, expectations.h, expectations.v, 0));
+ run_one_scan_loop();
+
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ pd_clear_movement();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+// clang-format off
+INSTANTIATE_TEST_CASE_P(
+ InvertAndRotate,
+ PointingInvertAndRotateParametrized,
+ ::testing::Values(
+ // Input Expected // Actual Result - Rotate 90 then Invert X
+ std::make_pair(SimpleReport{ -1, 0, 0, 0}, SimpleReport{ 0, 1, 0, 0}), // LEFT - DOWN
+ std::make_pair(SimpleReport{ 0, -1, 0, 0}, SimpleReport{ 1, 0, 0, 0}), // UP - RIGHT
+ std::make_pair(SimpleReport{ 1, 0, 0, 0}, SimpleReport{ 0, -1, 0, 0}), // RIGHT - UP
+ std::make_pair(SimpleReport{ 0, 1, 0, 0}, SimpleReport{ -1, 0, 0, 0}) // DOWN - LEFT
+ // Input Expected // Invert X then Rotate 90
+ // std::make_pair(SimpleReport{ -1, 0, 0, 0}, SimpleReport{ 0, -1, 0, 0}), // LEFT - UP
+ // std::make_pair(SimpleReport{ 0, -1, 0, 0}, SimpleReport{ -1, 0, 0, 0}), // UP - LEFT
+ // std::make_pair(SimpleReport{ 1, 0, 0, 0}, SimpleReport{ 0, 1, 0, 0}), // RIGHT - DOWN
+ // std::make_pair(SimpleReport{ 0, 1, 0, 0}, SimpleReport{ 1, 0, 0, 0}) // DOWN - RIGHT
+ ));
+// clang-format on
diff --git a/tests/pointing/invertxy/config.h b/tests/pointing/invertxy/config.h
new file mode 100644
index 000000000000..6b29185d371b
--- /dev/null
+++ b/tests/pointing/invertxy/config.h
@@ -0,0 +1,9 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
+
+#define POINTING_DEVICE_INVERT_X
+#define POINTING_DEVICE_INVERT_Y
diff --git a/tests/pointing/invertxy/test.mk b/tests/pointing/invertxy/test.mk
new file mode 100644
index 000000000000..ba224d74f0ab
--- /dev/null
+++ b/tests/pointing/invertxy/test.mk
@@ -0,0 +1,2 @@
+POINTING_DEVICE_ENABLE = yes
+POINTING_DEVICE_DRIVER = custom
diff --git a/tests/pointing/invertxy/test_invertxy.cpp b/tests/pointing/invertxy/test_invertxy.cpp
new file mode 100644
index 000000000000..014f6f3cd032
--- /dev/null
+++ b/tests/pointing/invertxy/test_invertxy.cpp
@@ -0,0 +1,53 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "gtest/gtest.h"
+#include "mouse_report_util.hpp"
+#include "test_common.hpp"
+#include "test_pointing_device_driver.h"
+
+using testing::_;
+
+struct SimpleReport {
+ int16_t x;
+ int16_t y;
+ int16_t h;
+ int16_t v;
+};
+
+class Pointing : public TestFixture {};
+class PointingInvertXYParametrized : public ::testing::WithParamInterface>, public Pointing {};
+
+TEST_P(PointingInvertXYParametrized, PointingInvertXY) {
+ TestDriver driver;
+ SimpleReport input = GetParam().first;
+ SimpleReport expectations = GetParam().second;
+
+ pd_set_x(input.x);
+ pd_set_y(input.y);
+ pd_set_h(input.h);
+ pd_set_v(input.v);
+
+ EXPECT_MOUSE_REPORT(driver, (expectations.x, expectations.y, expectations.h, expectations.v, 0));
+ run_one_scan_loop();
+
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ pd_clear_movement();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+// clang-format off
+INSTANTIATE_TEST_CASE_P(
+ X_Y_XY,
+ PointingInvertXYParametrized,
+ ::testing::Values(
+ // Input Expected
+ std::make_pair(SimpleReport{ 33, 0, 0, 0}, SimpleReport{ -33, 0, 0, 0}),
+ std::make_pair(SimpleReport{ 0, -127, 0, 0}, SimpleReport{ 0, 127, 0, 0}),
+ std::make_pair(SimpleReport{ 10, -20, 0, 0}, SimpleReport{ -10, 20, 0, 0})
+ ));
+// clang-format on
diff --git a/tests/pointing/rotate180/config.h b/tests/pointing/rotate180/config.h
new file mode 100644
index 000000000000..a80f5482fd4d
--- /dev/null
+++ b/tests/pointing/rotate180/config.h
@@ -0,0 +1,8 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
+
+#define POINTING_DEVICE_ROTATION_180
diff --git a/tests/pointing/rotate180/test.mk b/tests/pointing/rotate180/test.mk
new file mode 100644
index 000000000000..ba224d74f0ab
--- /dev/null
+++ b/tests/pointing/rotate180/test.mk
@@ -0,0 +1,2 @@
+POINTING_DEVICE_ENABLE = yes
+POINTING_DEVICE_DRIVER = custom
diff --git a/tests/pointing/rotate180/test_rotate180.cpp b/tests/pointing/rotate180/test_rotate180.cpp
new file mode 100644
index 000000000000..736cf9ea25cc
--- /dev/null
+++ b/tests/pointing/rotate180/test_rotate180.cpp
@@ -0,0 +1,55 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "gtest/gtest.h"
+#include "mouse_report_util.hpp"
+#include "test_common.hpp"
+#include "test_pointing_device_driver.h"
+
+using testing::_;
+
+struct SimpleReport {
+ int16_t x;
+ int16_t y;
+ int16_t h;
+ int16_t v;
+};
+
+class Pointing : public TestFixture {};
+class PointingRotateParametrized : public ::testing::WithParamInterface>, public Pointing {};
+
+TEST_P(PointingRotateParametrized, PointingRotateXY) {
+ TestDriver driver;
+ SimpleReport input = GetParam().first;
+ SimpleReport expectations = GetParam().second;
+
+ pd_set_x(input.x);
+ pd_set_y(input.y);
+ pd_set_h(input.h);
+ pd_set_v(input.v);
+
+ EXPECT_MOUSE_REPORT(driver, (expectations.x, expectations.y, expectations.h, expectations.v, 0));
+ run_one_scan_loop();
+
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ pd_clear_movement();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+// clang-format off
+INSTANTIATE_TEST_CASE_P(
+ Rotate180,
+ PointingRotateParametrized,
+ ::testing::Values(
+ // Input Expected
+ // Rotate Clockwise
+ std::make_pair(SimpleReport{ 0,-1, 0, 0}, SimpleReport{ 0, 1, 0, 0}), // UP - DOWN
+ std::make_pair(SimpleReport{ 0, 1, 0, 0}, SimpleReport{ 0,-1, 0, 0}), // DOWN - UP
+ std::make_pair(SimpleReport{ 1, 0, 0, 0}, SimpleReport{-1, 0, 0, 0}), // RIGHT - LEFT
+ std::make_pair(SimpleReport{ -1, 0, 0, 0}, SimpleReport{ 1, 0, 0, 0}) // LEFT - RIGHT
+ ));
+// clang-format on
diff --git a/tests/pointing/rotate270/config.h b/tests/pointing/rotate270/config.h
new file mode 100644
index 000000000000..3977dd95e6c3
--- /dev/null
+++ b/tests/pointing/rotate270/config.h
@@ -0,0 +1,8 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
+
+#define POINTING_DEVICE_ROTATION_270
diff --git a/tests/pointing/rotate270/test.mk b/tests/pointing/rotate270/test.mk
new file mode 100644
index 000000000000..ba224d74f0ab
--- /dev/null
+++ b/tests/pointing/rotate270/test.mk
@@ -0,0 +1,2 @@
+POINTING_DEVICE_ENABLE = yes
+POINTING_DEVICE_DRIVER = custom
diff --git a/tests/pointing/rotate270/test_rotate270.cpp b/tests/pointing/rotate270/test_rotate270.cpp
new file mode 100644
index 000000000000..6735f0624895
--- /dev/null
+++ b/tests/pointing/rotate270/test_rotate270.cpp
@@ -0,0 +1,60 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "gtest/gtest.h"
+#include "mouse_report_util.hpp"
+#include "test_common.hpp"
+#include "test_pointing_device_driver.h"
+
+using testing::_;
+
+struct SimpleReport {
+ int16_t x;
+ int16_t y;
+ int16_t h;
+ int16_t v;
+};
+
+class Pointing : public TestFixture {};
+class PointingRotateParametrized : public ::testing::WithParamInterface>, public Pointing {};
+
+TEST_P(PointingRotateParametrized, PointingRotateXY) {
+ TestDriver driver;
+ SimpleReport input = GetParam().first;
+ SimpleReport expectations = GetParam().second;
+
+ pd_set_x(input.x);
+ pd_set_y(input.y);
+ pd_set_h(input.h);
+ pd_set_v(input.v);
+
+ EXPECT_MOUSE_REPORT(driver, (expectations.x, expectations.y, expectations.h, expectations.v, 0));
+ run_one_scan_loop();
+
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ pd_clear_movement();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+// clang-format off
+INSTANTIATE_TEST_CASE_P(
+ Rotate270,
+ PointingRotateParametrized,
+ ::testing::Values(
+ // Input Expected
+ // Actual Result - Rotate Anticlockwise
+ std::make_pair(SimpleReport{ 0,-1, 0, 0}, SimpleReport{ 1, 0, 0, 0}), // UP - RIGHT
+ std::make_pair(SimpleReport{ 0, 1, 0, 0}, SimpleReport{-1, 0, 0, 0}), // DOWN - LEFT
+ std::make_pair(SimpleReport{ 1, 0, 0, 0}, SimpleReport{ 0, 1, 0, 0}), // RIGHT - DOWN
+ std::make_pair(SimpleReport{ -1, 0, 0, 0}, SimpleReport{ 0,-1, 0, 0}) // LEFT - UP
+ // Rotate Clockwise
+ // std::make_pair(SimpleReport{ 0,-1, 0, 0}, SimpleReport{-1, 0, 0, 0}), // UP - LEFT
+ // std::make_pair(SimpleReport{ 0, 1, 0, 0}, SimpleReport{ 1, 0, 0, 0}), // DOWN - RIGHT
+ // std::make_pair(SimpleReport{ 1, 0, 0, 0}, SimpleReport{ 0,-1, 0, 0}), // RIGHT - UP
+ // std::make_pair(SimpleReport{ -1, 0, 0, 0}, SimpleReport{ 0, 1, 0, 0}) // LEFT - DOWN
+ ));
+// clang-format on
diff --git a/tests/pointing/rotate90/config.h b/tests/pointing/rotate90/config.h
new file mode 100644
index 000000000000..3a18ec92e947
--- /dev/null
+++ b/tests/pointing/rotate90/config.h
@@ -0,0 +1,8 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include "test_common.h"
+
+#define POINTING_DEVICE_ROTATION_90
diff --git a/tests/pointing/rotate90/test.mk b/tests/pointing/rotate90/test.mk
new file mode 100644
index 000000000000..ba224d74f0ab
--- /dev/null
+++ b/tests/pointing/rotate90/test.mk
@@ -0,0 +1,2 @@
+POINTING_DEVICE_ENABLE = yes
+POINTING_DEVICE_DRIVER = custom
diff --git a/tests/pointing/rotate90/test_rotate90.cpp b/tests/pointing/rotate90/test_rotate90.cpp
new file mode 100644
index 000000000000..5c44faad0ab4
--- /dev/null
+++ b/tests/pointing/rotate90/test_rotate90.cpp
@@ -0,0 +1,60 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "gtest/gtest.h"
+#include "mouse_report_util.hpp"
+#include "test_common.hpp"
+#include "test_pointing_device_driver.h"
+
+using testing::_;
+
+struct SimpleReport {
+ int16_t x;
+ int16_t y;
+ int16_t h;
+ int16_t v;
+};
+
+class Pointing : public TestFixture {};
+class PointingRotateParametrized : public ::testing::WithParamInterface>, public Pointing {};
+
+TEST_P(PointingRotateParametrized, PointingRotateXY) {
+ TestDriver driver;
+ SimpleReport input = GetParam().first;
+ SimpleReport expectations = GetParam().second;
+
+ pd_set_x(input.x);
+ pd_set_y(input.y);
+ pd_set_h(input.h);
+ pd_set_v(input.v);
+
+ EXPECT_MOUSE_REPORT(driver, (expectations.x, expectations.y, expectations.h, expectations.v, 0));
+ run_one_scan_loop();
+
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ pd_clear_movement();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+// clang-format off
+INSTANTIATE_TEST_CASE_P(
+ Rotate90,
+ PointingRotateParametrized,
+ ::testing::Values(
+ // Input Expected
+ // Actual Result - Rotate Anticlockwise
+ std::make_pair(SimpleReport{ 0,-1, 0, 0}, SimpleReport{-1, 0, 0, 0}), // UP - LEFT
+ std::make_pair(SimpleReport{ 0, 1, 0, 0}, SimpleReport{ 1, 0, 0, 0}), // DOWN - RIGHT
+ std::make_pair(SimpleReport{ 1, 0, 0, 0}, SimpleReport{ 0,-1, 0, 0}), // RIGHT - UP
+ std::make_pair(SimpleReport{ -1, 0, 0, 0}, SimpleReport{ 0, 1, 0, 0}) // LEFT - DOWN
+ // Rotate Clockwise
+ // std::make_pair(SimpleReport{ 0,-1, 0, 0}, SimpleReport{ 1, 0, 0, 0}), // UP - RIGHT
+ // std::make_pair(SimpleReport{ 0, 1, 0, 0}, SimpleReport{-1, 0, 0, 0}), // DOWN - LEFT
+ // std::make_pair(SimpleReport{ 1, 0, 0, 0}, SimpleReport{ 0,-1, 0, 0}), // RIGHT - DOWN
+ // std::make_pair(SimpleReport{ -1, 0, 0, 0}, SimpleReport{ 0, 1, 0, 0}) // LEFT - UP
+ ));
+// clang-format on
diff --git a/tests/pointing/test.mk b/tests/pointing/test.mk
new file mode 100644
index 000000000000..95fde21cb92c
--- /dev/null
+++ b/tests/pointing/test.mk
@@ -0,0 +1,4 @@
+POINTING_DEVICE_ENABLE = yes
+MOUSEKEY_ENABLE = no
+POINTING_DEVICE_DRIVER = custom
+
diff --git a/tests/pointing/test_pointing.cpp b/tests/pointing/test_pointing.cpp
new file mode 100644
index 000000000000..d59d01492517
--- /dev/null
+++ b/tests/pointing/test_pointing.cpp
@@ -0,0 +1,166 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "gtest/gtest.h"
+#include "mouse_report_util.hpp"
+#include "test_common.hpp"
+#include "test_pointing_device_driver.h"
+#include "mousekey.h"
+
+using testing::_;
+
+class Pointing : public TestFixture {};
+class PointingButtonsViaMousekeysParametrized : public ::testing::WithParamInterface>, public Pointing {};
+
+TEST_F(Pointing, SendMouseIsNotCalledWithNoInput) {
+ TestDriver driver;
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+}
+
+TEST_F(Pointing, Xnegative) {
+ TestDriver driver;
+
+ pd_set_x(-10);
+ EXPECT_MOUSE_REPORT(driver, (-10, 0, 0, 0, 0));
+ run_one_scan_loop();
+
+ pd_clear_movement();
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(Pointing, Xpositive) {
+ TestDriver driver;
+
+ pd_set_x(10);
+ EXPECT_MOUSE_REPORT(driver, (10, 0, 0, 0, 0));
+ run_one_scan_loop();
+
+ pd_clear_movement();
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(Pointing, Ynegative) {
+ TestDriver driver;
+
+ pd_set_y(-20);
+ EXPECT_MOUSE_REPORT(driver, (0, -20, 0, 0, 0));
+ run_one_scan_loop();
+
+ pd_clear_movement();
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(Pointing, Ypositive) {
+ TestDriver driver;
+
+ pd_set_y(20);
+ EXPECT_MOUSE_REPORT(driver, (0, 20, 0, 0, 0));
+ run_one_scan_loop();
+
+ pd_clear_movement();
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(Pointing, XandY) {
+ TestDriver driver;
+
+ pd_set_x(-50);
+ pd_set_y(100);
+ EXPECT_MOUSE_REPORT(driver, (-50, 100, 0, 0, 0));
+ run_one_scan_loop();
+
+ pd_clear_movement();
+ // EXPECT_EMPTY_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(Pointing, CorrectButtonIsReportedWhenPressed) {
+ TestDriver driver;
+
+ EXPECT_MOUSE_REPORT(driver, (0, 0, 0, 0, 1));
+ pd_press_button(POINTING_DEVICE_BUTTON1);
+ run_one_scan_loop();
+
+ EXPECT_EMPTY_MOUSE_REPORT(driver);
+ pd_release_button(POINTING_DEVICE_BUTTON1);
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ pd_clear_all_buttons();
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_F(Pointing, CorrectButtonIsReportedWhenKeyPressed) {
+ TestDriver driver;
+ auto key = KeymapKey(0, 0, 0, KC_MS_BTN1);
+ set_keymap({key});
+
+ EXPECT_MOUSE_REPORT(driver, (0, 0, 0, 0, 1));
+ key.press();
+ run_one_scan_loop();
+
+ EXPECT_EMPTY_MOUSE_REPORT(driver);
+ key.release();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+
+TEST_P(PointingButtonsViaMousekeysParametrized, MouseKeysViaPointingDriver) {
+ TestDriver driver;
+ KeymapKey mouse_key = GetParam().first;
+ uint8_t button_mask = GetParam().second;
+
+ set_keymap({mouse_key});
+
+ EXPECT_MOUSE_REPORT(driver, (0, 0, 0, 0, button_mask));
+ mouse_key.press();
+ run_one_scan_loop();
+
+ EXPECT_EMPTY_MOUSE_REPORT(driver);
+ mouse_key.release();
+ run_one_scan_loop();
+
+ EXPECT_NO_MOUSE_REPORT(driver);
+ run_one_scan_loop();
+
+ VERIFY_AND_CLEAR(driver);
+}
+// clang-format off
+INSTANTIATE_TEST_CASE_P(
+ ButtonsOneToEight,
+ PointingButtonsViaMousekeysParametrized,
+ ::testing::Values(
+ // Key , Buttons Mask
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_1}, 1),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_2}, 2),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_3}, 4),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_4}, 8),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_5}, 16),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_6}, 32),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_7}, 64),
+ std::make_pair(KeymapKey{0, 0, 0, QK_MOUSE_BUTTON_8}, 128)
+ ));
+// clang-format on
diff --git a/tests/test_common/keyboard_report_util.cpp b/tests/test_common/keyboard_report_util.cpp
index 567648353916..18e0574277d4 100644
--- a/tests/test_common/keyboard_report_util.cpp
+++ b/tests/test_common/keyboard_report_util.cpp
@@ -29,8 +29,6 @@ std::vector get_keys(const report_keyboard_t& report) {
std::vector result;
#if defined(NKRO_ENABLE)
# error NKRO support not implemented yet
-#elif defined(RING_BUFFERED_6KRO_REPORT_ENABLE)
-# error 6KRO support not implemented yet
#else
for (size_t i = 0; i < KEYBOARD_REPORT_KEYS; i++) {
if (report.keys[i]) {
diff --git a/tests/test_common/keycode_table.cpp b/tests/test_common/keycode_table.cpp
index 4c28ab4d20dd..ae1a9edcd0fc 100644
--- a/tests/test_common/keycode_table.cpp
+++ b/tests/test_common/keycode_table.cpp
@@ -562,6 +562,21 @@ std::map KEYCODE_ID_TABLE = {
{QK_MACRO_29, "QK_MACRO_29"},
{QK_MACRO_30, "QK_MACRO_30"},
{QK_MACRO_31, "QK_MACRO_31"},
+ {QK_OUTPUT_AUTO, "QK_OUTPUT_AUTO"},
+ {QK_OUTPUT_NEXT, "QK_OUTPUT_NEXT"},
+ {QK_OUTPUT_PREV, "QK_OUTPUT_PREV"},
+ {QK_OUTPUT_NONE, "QK_OUTPUT_NONE"},
+ {QK_OUTPUT_USB, "QK_OUTPUT_USB"},
+ {QK_OUTPUT_2P4GHZ, "QK_OUTPUT_2P4GHZ"},
+ {QK_OUTPUT_BLUETOOTH, "QK_OUTPUT_BLUETOOTH"},
+ {QK_BLUETOOTH_PROFILE_NEXT, "QK_BLUETOOTH_PROFILE_NEXT"},
+ {QK_BLUETOOTH_PROFILE_PREV, "QK_BLUETOOTH_PROFILE_PREV"},
+ {QK_BLUETOOTH_UNPAIR, "QK_BLUETOOTH_UNPAIR"},
+ {QK_BLUETOOTH_PROFILE1, "QK_BLUETOOTH_PROFILE1"},
+ {QK_BLUETOOTH_PROFILE2, "QK_BLUETOOTH_PROFILE2"},
+ {QK_BLUETOOTH_PROFILE3, "QK_BLUETOOTH_PROFILE3"},
+ {QK_BLUETOOTH_PROFILE4, "QK_BLUETOOTH_PROFILE4"},
+ {QK_BLUETOOTH_PROFILE5, "QK_BLUETOOTH_PROFILE5"},
{QK_BACKLIGHT_ON, "QK_BACKLIGHT_ON"},
{QK_BACKLIGHT_OFF, "QK_BACKLIGHT_OFF"},
{QK_BACKLIGHT_TOGGLE, "QK_BACKLIGHT_TOGGLE"},
@@ -632,9 +647,6 @@ std::map KEYCODE_ID_TABLE = {
{QK_SPACE_CADET_LEFT_ALT_PARENTHESIS_OPEN, "QK_SPACE_CADET_LEFT_ALT_PARENTHESIS_OPEN"},
{QK_SPACE_CADET_RIGHT_ALT_PARENTHESIS_CLOSE, "QK_SPACE_CADET_RIGHT_ALT_PARENTHESIS_CLOSE"},
{QK_SPACE_CADET_RIGHT_SHIFT_ENTER, "QK_SPACE_CADET_RIGHT_SHIFT_ENTER"},
- {QK_OUTPUT_AUTO, "QK_OUTPUT_AUTO"},
- {QK_OUTPUT_USB, "QK_OUTPUT_USB"},
- {QK_OUTPUT_BLUETOOTH, "QK_OUTPUT_BLUETOOTH"},
{QK_UNICODE_MODE_NEXT, "QK_UNICODE_MODE_NEXT"},
{QK_UNICODE_MODE_PREVIOUS, "QK_UNICODE_MODE_PREVIOUS"},
{QK_UNICODE_MODE_MACOS, "QK_UNICODE_MODE_MACOS"},
@@ -687,6 +699,7 @@ std::map KEYCODE_ID_TABLE = {
{QK_TRI_LAYER_UPPER, "QK_TRI_LAYER_UPPER"},
{QK_REPEAT_KEY, "QK_REPEAT_KEY"},
{QK_ALT_REPEAT_KEY, "QK_ALT_REPEAT_KEY"},
+ {QK_LAYER_LOCK, "QK_LAYER_LOCK"},
{QK_KB_0, "QK_KB_0"},
{QK_KB_1, "QK_KB_1"},
{QK_KB_2, "QK_KB_2"},
diff --git a/tests/test_common/keycode_util.cpp b/tests/test_common/keycode_util.cpp
index 9f88d40ec7b8..539cab819ac7 100644
--- a/tests/test_common/keycode_util.cpp
+++ b/tests/test_common/keycode_util.cpp
@@ -94,6 +94,8 @@ std::string generate_identifier(uint16_t kc) {
s << "MO(" << +QK_MOMENTARY_GET_LAYER(kc) << ")";
} else if (IS_QK_DEF_LAYER(kc)) {
s << "DF(" << +QK_DEF_LAYER_GET_LAYER(kc) << ")";
+ } else if (IS_QK_PERSISTENT_DEF_LAYER(kc)) {
+ s << "PDF(" << +QK_PERSISTENT_DEF_LAYER_GET_LAYER(kc) << ")";
} else if (IS_QK_TOGGLE_LAYER(kc)) {
s << "TG(" << +QK_TOGGLE_LAYER_GET_LAYER(kc) << ")";
} else if (IS_QK_LAYER_TAP_TOGGLE(kc)) {
diff --git a/tests/test_common/mouse_report_util.cpp b/tests/test_common/mouse_report_util.cpp
new file mode 100644
index 000000000000..60cdeced24f5
--- /dev/null
+++ b/tests/test_common/mouse_report_util.cpp
@@ -0,0 +1,58 @@
+/* Copyright 2017 Fred Sundvik
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include "mouse_report_util.hpp"
+#include
+#include
+#include
+
+using namespace testing;
+
+bool operator==(const report_mouse_t& lhs, const report_mouse_t& rhs) {
+ return lhs.x == rhs.x && lhs.y == rhs.y && lhs.h == rhs.h && lhs.v == rhs.v && lhs.buttons == rhs.buttons;
+}
+
+std::ostream& operator<<(std::ostream& os, const report_mouse_t& report) {
+ os << std::setw(10) << std::left << "mouse report: ";
+
+ if (report.x == 0 && report.y == 0 && report.h == 0 && report.v == 0 && report.buttons == 0) {
+ return os << "empty" << std::endl;
+ }
+
+ os << "(X:" << (int)report.x << ", Y:" << (int)report.y << ", H:" << (int)report.h << ", V:" << (int)report.v << ", B:" << (int)report.buttons << ")";
+ return os << std::endl;
+}
+
+MouseReportMatcher::MouseReportMatcher(int16_t x, int16_t y, int8_t h, int8_t v, uint8_t button_mask) {
+ memset(&m_report, 0, sizeof(report_mouse_t));
+ m_report.x = x;
+ m_report.y = y;
+ m_report.h = h;
+ m_report.v = v;
+ m_report.buttons = button_mask;
+}
+
+bool MouseReportMatcher::MatchAndExplain(report_mouse_t& report, MatchResultListener* listener) const {
+ return m_report == report;
+}
+
+void MouseReportMatcher::DescribeTo(::std::ostream* os) const {
+ *os << "is equal to " << m_report;
+}
+
+void MouseReportMatcher::DescribeNegationTo(::std::ostream* os) const {
+ *os << "is not equal to " << m_report;
+}
diff --git a/tests/test_common/mouse_report_util.hpp b/tests/test_common/mouse_report_util.hpp
new file mode 100644
index 000000000000..645f6aa58c64
--- /dev/null
+++ b/tests/test_common/mouse_report_util.hpp
@@ -0,0 +1,38 @@
+/* Copyright 2017 Fred Sundvik
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#pragma once
+#include "report.h"
+#include
+#include "gmock/gmock.h"
+
+bool operator==(const report_mouse_t& lhs, const report_mouse_t& rhs);
+std::ostream& operator<<(std::ostream& stream, const report_mouse_t& value);
+
+class MouseReportMatcher : public testing::MatcherInterface {
+ public:
+ MouseReportMatcher(int16_t x, int16_t y, int8_t h, int8_t v, uint8_t button_mask);
+ virtual bool MatchAndExplain(report_mouse_t& report, testing::MatchResultListener* listener) const override;
+ virtual void DescribeTo(::std::ostream* os) const override;
+ virtual void DescribeNegationTo(::std::ostream* os) const override;
+
+ private:
+ report_mouse_t m_report;
+};
+
+inline testing::Matcher MouseReport(int16_t x, int16_t y, int8_t h, int8_t v, uint8_t button_mask) {
+ return testing::MakeMatcher(new MouseReportMatcher(x, y, h, v, button_mask));
+}
diff --git a/tests/test_common/pointing_device_driver.c b/tests/test_common/pointing_device_driver.c
new file mode 100644
index 000000000000..b64dbad50635
--- /dev/null
+++ b/tests/test_common/pointing_device_driver.c
@@ -0,0 +1,109 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "report.h"
+#include "test_pointing_device_driver.h"
+#include
+
+typedef struct {
+ bool pressed;
+ bool dirty;
+} pd_button_state_t;
+
+typedef struct {
+ int16_t x;
+ int16_t y;
+ int16_t h;
+ int16_t v;
+ pd_button_state_t button_state[8];
+ uint16_t cpi;
+ bool initiated;
+} pd_config_t;
+
+static pd_config_t pd_config = {0};
+
+void pointing_device_driver_init(void) {
+ pd_set_init(true);
+}
+
+report_mouse_t pointing_device_driver_get_report(report_mouse_t mouse_report) {
+ for (uint8_t i = 0; i < 8; i++) {
+ if (pd_config.button_state[i].dirty) {
+ pd_config.button_state[i].dirty = false;
+ if (pd_config.button_state[i].pressed) {
+ mouse_report.buttons |= 1 << (i);
+ } else {
+ mouse_report.buttons &= ~(1 << (i));
+ }
+ }
+ }
+ mouse_report.x = pd_config.x;
+ mouse_report.y = pd_config.y;
+ mouse_report.h = pd_config.h;
+ mouse_report.v = pd_config.v;
+ return mouse_report;
+}
+
+__attribute__((weak)) uint16_t pointing_device_driver_get_cpi(void) {
+ return pd_config.cpi;
+}
+
+__attribute__((weak)) void pointing_device_driver_set_cpi(uint16_t cpi) {
+ pd_config.cpi = cpi;
+}
+
+void pd_press_button(uint8_t btn) {
+ pd_config.button_state[btn].dirty = true;
+ pd_config.button_state[btn].pressed = true;
+}
+void pd_release_button(uint8_t btn) {
+ pd_config.button_state[btn].dirty = true;
+ pd_config.button_state[btn].pressed = false;
+}
+
+void pd_clear_all_buttons(void) {
+ for (uint8_t i = 0; i < 8; i++) {
+ pd_config.button_state[i].dirty = true;
+ pd_config.button_state[i].pressed = false;
+ }
+}
+
+void pd_set_x(int16_t x) {
+ pd_config.x = x;
+}
+
+void pd_clear_x(void) {
+ pd_set_x(0);
+}
+
+void pd_set_y(int16_t y) {
+ pd_config.y = y;
+}
+void pd_clear_y(void) {
+ pd_set_y(0);
+}
+
+void pd_set_h(int16_t h) {
+ pd_config.h = h;
+}
+void pd_clear_h(void) {
+ pd_set_h(0);
+}
+
+void pd_set_v(int16_t v) {
+ pd_config.v = v;
+}
+void pd_clear_v(void) {
+ pd_set_v(0);
+}
+
+void pd_clear_movement(void) {
+ pd_set_x(0);
+ pd_set_y(0);
+ pd_set_h(0);
+ pd_set_v(0);
+}
+
+void pd_set_init(bool success) {
+ pd_config.initiated = success;
+}
diff --git a/tests/test_common/test_driver.cpp b/tests/test_common/test_driver.cpp
index d410b225f9d5..70b920ac86ab 100644
--- a/tests/test_common/test_driver.cpp
+++ b/tests/test_common/test_driver.cpp
@@ -54,6 +54,7 @@ void TestDriver::send_nkro(report_nkro_t* report) {
}
void TestDriver::send_mouse(report_mouse_t* report) {
+ test_logger.trace() << std::setw(10) << std::left << "send_mouse: (X:" << (int)report->x << ", Y:" << (int)report->y << ", H:" << (int)report->h << ", V:" << (int)report->v << ", B:" << (int)report->buttons << ")" << std::endl;
m_this->send_mouse_mock(*report);
}
diff --git a/tests/test_common/test_driver.hpp b/tests/test_common/test_driver.hpp
index ec75d3fff226..fea8225953a8 100644
--- a/tests/test_common/test_driver.hpp
+++ b/tests/test_common/test_driver.hpp
@@ -66,6 +66,25 @@ class TestDriver {
*/
#define EXPECT_REPORT(driver, report) EXPECT_CALL((driver), send_keyboard_mock(KeyboardReport report))
+/**
+ * @brief Sets gmock expectation that a mouse report of `report` will be sent.
+ * For this macro to parse correctly, the `report` arg must be surrounded by
+ * parentheses ( ). For instance,
+ *
+ * // Expect that a report of "X:-10 Y:0 H:0 V:10 BTN:1 " is sent to the host.
+ * EXPECT_REPORT(driver, (-10, 0, 0, 0, 1));
+ *
+ * is shorthand for
+ *
+ * EXPECT_CALL(driver, send_mouse_mock(MouseReport(-10, 0, 0, 0, 1)));
+ *
+ * It is possible to use .Times() and other gmock APIS with EXPECT_REPORT, for instance,
+ * allow only single report to be sent:
+ *
+ * EXPECT_REPORT(driver, (-10, 0, 0, 0, 1)).Times(1);
+ */
+#define EXPECT_MOUSE_REPORT(driver, report) EXPECT_CALL((driver), send_mouse_mock(MouseReport report))
+
/**
* @brief Sets gmock expectation that Unicode `code_point` is sent with UNICODE_MODE_LINUX input
* mode. For instance for U+2013,
@@ -87,6 +106,15 @@ class TestDriver {
*/
#define EXPECT_EMPTY_REPORT(driver) EXPECT_REPORT(driver, ())
+/**
+ * @brief Sets gmock expectation that a empty keyboard report will be sent.
+ * It is possible to use .Times() and other gmock APIS with EXPECT_EMPTY_MOUSE_REPORT, for instance,
+ * allow any number of empty reports with:
+ *
+ * EXPECT_EMPTY_MOUSE_REPORT(driver).Times(AnyNumber());
+ */
+#define EXPECT_EMPTY_MOUSE_REPORT(driver) EXPECT_MOUSE_REPORT(driver, (0, 0, 0, 0, 0))
+
/**
* @brief Sets gmock expectation that a keyboard report will be sent, without matching its content.
* It is possible to use .Times() and other gmock APIS with EXPECT_ANY_REPORT, for instance,
@@ -96,11 +124,25 @@ class TestDriver {
*/
#define EXPECT_ANY_REPORT(driver) EXPECT_CALL((driver), send_keyboard_mock(_))
+/**
+ * @brief Sets gmock expectation that a mouse report will be sent, without matching its content.
+ * It is possible to use .Times() and other gmock APIS with EXPECT_ANY_MOUSE_REPORT, for instance,
+ * allow a single arbitrary report with:
+ *
+ * EXPECT_ANY_MOUSE_REPORT(driver).Times(1);
+ */
+#define EXPECT_ANY_MOUSE_REPORT(driver) EXPECT_CALL((driver), send_mouse_mock(_))
+
/**
* @brief Sets gmock expectation that no keyboard report will be sent at all.
*/
#define EXPECT_NO_REPORT(driver) EXPECT_ANY_REPORT(driver).Times(0)
+/**
+ * @brief Sets gmock expectation that no keyboard report will be sent at all.
+ */
+#define EXPECT_NO_MOUSE_REPORT(driver) EXPECT_ANY_MOUSE_REPORT(driver).Times(0)
+
/** @brief Tests whether keycode `actual` is equal to `expected`. */
#define EXPECT_KEYCODE_EQ(actual, expected) EXPECT_THAT((actual), KeycodeEq((expected)))
diff --git a/tests/test_common/test_fixture.cpp b/tests/test_common/test_fixture.cpp
index 3cfb2cb4c292..81806b0e6d27 100644
--- a/tests/test_common/test_fixture.cpp
+++ b/tests/test_common/test_fixture.cpp
@@ -7,6 +7,7 @@
#include "gmock/gmock.h"
#include "gtest/gtest.h"
#include "keyboard_report_util.hpp"
+#include "mouse_report_util.hpp"
#include "keycode.h"
#include "test_driver.hpp"
#include "test_logger.hpp"
@@ -69,6 +70,9 @@ TestFixture::~TestFixture() {
/* Reset keyboard state. */
clear_all_keys();
+#ifdef MOUSEKEY_ENABLE
+ EXPECT_EMPTY_MOUSE_REPORT(driver);
+#endif
clear_keyboard();
clear_oneshot_mods();
diff --git a/tests/test_common/test_pointing_device_driver.h b/tests/test_common/test_pointing_device_driver.h
new file mode 100644
index 000000000000..ae136b21cdf0
--- /dev/null
+++ b/tests/test_common/test_pointing_device_driver.h
@@ -0,0 +1,32 @@
+// Copyright 2024 Dasky (@daskygit)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void pd_press_button(uint8_t btn);
+void pd_release_button(uint8_t btn);
+void pd_clear_all_buttons(void);
+
+void pd_set_x(int16_t x);
+void clear_x(void);
+
+void pd_set_y(int16_t y);
+void pd_clear_y(void);
+
+void pd_set_h(int16_t h);
+void pd_clear_h(void);
+
+void pd_set_v(int16_t v);
+void pd_clear_v(void);
+
+void pd_clear_movement(void);
+
+void pd_set_init(bool success);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/protocol.mk b/tmk_core/protocol.mk
index 796b4e878713..8f019765484a 100644
--- a/tmk_core/protocol.mk
+++ b/tmk_core/protocol.mk
@@ -54,10 +54,6 @@ ifeq ($(strip $(NKRO_ENABLE)), yes)
endif
endif
-ifeq ($(strip $(RING_BUFFERED_6KRO_REPORT_ENABLE)), yes)
- OPT_DEFS += -DRING_BUFFERED_6KRO_REPORT_ENABLE
-endif
-
ifeq ($(strip $(NO_SUSPEND_POWER_DOWN)), yes)
OPT_DEFS += -DNO_SUSPEND_POWER_DOWN
endif
diff --git a/tmk_core/protocol/arm_atsam/adc.c b/tmk_core/protocol/arm_atsam/adc.c
deleted file mode 100644
index 3afcbddf1011..000000000000
--- a/tmk_core/protocol/arm_atsam/adc.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "arm_atsam_protocol.h"
-
-uint16_t v_5v;
-uint16_t v_5v_avg;
-uint16_t v_con_1;
-uint16_t v_con_2;
-uint16_t v_con_1_boot;
-uint16_t v_con_2_boot;
-
-void ADC0_clock_init(void) {
- DBGC(DC_ADC0_CLOCK_INIT_BEGIN);
-
- MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable
-
- GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock
- GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock
-
- DBGC(DC_ADC0_CLOCK_INIT_COMPLETE);
-}
-
-void ADC0_init(void) {
- DBGC(DC_ADC0_INIT_BEGIN);
-
- // MCU
- PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V
- PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2
- PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1
- PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V
- PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2
- PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1
- PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V
- PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2
- PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1
-
- // ADC
- ADC0->CTRLA.bit.SWRST = 1;
- while (ADC0->SYNCBUSY.bit.SWRST) {
- DBGC(DC_ADC0_SWRST_SYNCING_1);
- }
- while (ADC0->CTRLA.bit.SWRST) {
- DBGC(DC_ADC0_SWRST_SYNCING_2);
- }
-
- // Clock divide
- ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV2_Val;
-
- // Averaging
- ADC0->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_4_Val;
- while (ADC0->SYNCBUSY.bit.AVGCTRL) {
- DBGC(DC_ADC0_AVGCTRL_SYNCING_1);
- }
- if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val)
- ADC0->AVGCTRL.bit.ADJRES = 0;
- else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val)
- ADC0->AVGCTRL.bit.ADJRES = 1;
- else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val)
- ADC0->AVGCTRL.bit.ADJRES = 2;
- else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val)
- ADC0->AVGCTRL.bit.ADJRES = 3;
- else
- ADC0->AVGCTRL.bit.ADJRES = 4;
- while (ADC0->SYNCBUSY.bit.AVGCTRL) {
- DBGC(DC_ADC0_AVGCTRL_SYNCING_2);
- }
-
- // Settling
- ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per
- while (ADC0->SYNCBUSY.bit.SAMPCTRL) {
- DBGC(DC_ADC0_SAMPCTRL_SYNCING_1);
- }
-
- // Load factory calibration data
- ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos;
- ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos;
- ADC0->CALIB.bit.BIASREFBUF = ((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR) & ADC0_FUSES_BIASREFBUF_Msk) >> ADC0_FUSES_BIASREFBUF_Pos;
-
- // Enable
- ADC0->CTRLA.bit.ENABLE = 1;
- while (ADC0->SYNCBUSY.bit.ENABLE) {
- DBGC(DC_ADC0_ENABLE_SYNCING_1);
- }
-
- DBGC(DC_ADC0_INIT_COMPLETE);
-}
-
-uint16_t adc_get(uint8_t muxpos) {
- ADC0->INPUTCTRL.bit.MUXPOS = muxpos;
- while (ADC0->SYNCBUSY.bit.INPUTCTRL) {
- }
-
- ADC0->SWTRIG.bit.START = 1;
- while (ADC0->SYNCBUSY.bit.SWTRIG) {
- }
- while (!ADC0->INTFLAG.bit.RESRDY) {
- }
-
- return ADC0->RESULT.reg;
-}
diff --git a/tmk_core/protocol/arm_atsam/adc.h b/tmk_core/protocol/arm_atsam/adc.h
deleted file mode 100644
index 74fbb0e66f71..000000000000
--- a/tmk_core/protocol/arm_atsam/adc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _ADC_H_
-#define _ADC_H_
-
-#define ADC_5V_START_LEVEL 2365
-
-#define ADC_5V ADC_INPUTCTRL_MUXPOS_AIN12_Val
-#define ADC_CON1 ADC_INPUTCTRL_MUXPOS_AIN14_Val
-#define ADC_CON2 ADC_INPUTCTRL_MUXPOS_AIN13_Val
-
-extern uint16_t v_5v;
-extern uint16_t v_5v_avg;
-extern uint16_t v_con_1;
-extern uint16_t v_con_2;
-extern uint16_t v_con_1_boot;
-extern uint16_t v_con_2_boot;
-
-void ADC0_clock_init(void);
-void ADC0_init(void);
-
-#endif //_ADC_H_
diff --git a/tmk_core/protocol/arm_atsam/arm_atsam.mk b/tmk_core/protocol/arm_atsam/arm_atsam.mk
deleted file mode 100644
index ffd1fa9f5027..000000000000
--- a/tmk_core/protocol/arm_atsam/arm_atsam.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-ARM_ATSAM_DIR = protocol/arm_atsam
-
-SRC += $(ARM_ATSAM_DIR)/adc.c
-SRC += $(ARM_ATSAM_DIR)/clks.c
-SRC += $(ARM_ATSAM_DIR)/d51_util.c
-SRC += $(ARM_ATSAM_DIR)/i2c_master.c
-ifeq ($(RGB_MATRIX_DRIVER),custom)
- SRC += $(ARM_ATSAM_DIR)/md_rgb_matrix_programs.c
- SRC += $(ARM_ATSAM_DIR)/md_rgb_matrix.c
-endif
-SRC += $(ARM_ATSAM_DIR)/main_arm_atsam.c
-SRC += $(ARM_ATSAM_DIR)/shift_register.c
-SRC += $(ARM_ATSAM_DIR)/spi_master.c
-SRC += $(ARM_ATSAM_DIR)/startup.c
-
-SRC += $(ARM_ATSAM_DIR)/usb/main_usb.c
-SRC += $(ARM_ATSAM_DIR)/usb/udc.c
-SRC += $(ARM_ATSAM_DIR)/usb/udi_cdc.c
-SRC += $(ARM_ATSAM_DIR)/usb/udi_hid.c
-SRC += $(ARM_ATSAM_DIR)/usb/udi_hid_kbd.c
-SRC += $(ARM_ATSAM_DIR)/usb/udi_hid_kbd_desc.c
-SRC += $(ARM_ATSAM_DIR)/usb/ui.c
-SRC += $(ARM_ATSAM_DIR)/usb/usb.c
-SRC += $(ARM_ATSAM_DIR)/usb/usb_device_udd.c
-SRC += $(ARM_ATSAM_DIR)/usb/usb_hub.c
-SRC += $(ARM_ATSAM_DIR)/usb/usb_util.c
-
-SRC += $(DRIVER_PATH)/usb2422.c
-
-# Search Path
-VPATH += $(TMK_DIR)/$(ARM_ATSAM_DIR)
diff --git a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h
deleted file mode 100644
index db9827f6a2b8..000000000000
--- a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _ARM_ATSAM_PROTOCOL_H_
-#define _ARM_ATSAM_PROTOCOL_H_
-
-#include "samd51j18a.h"
-
-#include "timer.h"
-#include "d51_util.h"
-#include "clks.h"
-#include "wait.h"
-#include "adc.h"
-#include "i2c_master.h"
-#include "shift_register.h"
-
-#include "./usb/usb_hub.h"
-
-#ifndef MD_BOOTLOADER
-
-# include "main_arm_atsam.h"
-# ifdef RGB_MATRIX_ENABLE
-# include "md_rgb_matrix.h"
-# include "rgb_matrix.h"
-# endif
-# include "issi3733_driver.h"
-# include "./usb/compiler.h"
-# include "./usb/udc.h"
-# include "./usb/udi_cdc.h"
-
-#endif // MD_BOOTLOADER
-
-#endif //_ARM_ATSAM_PROTOCOL_H_
diff --git a/tmk_core/protocol/arm_atsam/clks.c b/tmk_core/protocol/arm_atsam/clks.c
deleted file mode 100644
index 9b9475c61659..000000000000
--- a/tmk_core/protocol/arm_atsam/clks.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "arm_atsam_protocol.h"
-
-#include
-
-volatile clk_t system_clks;
-volatile uint64_t ms_clk;
-uint32_t usec_delay_mult;
-#define USEC_DELAY_LOOP_CYCLES 3 // Sum of instruction cycles in us delay loop
-
-const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0, (uint32_t)SERCOM1, (uint32_t)SERCOM2, (uint32_t)SERCOM3, (uint32_t)SERCOM4, (uint32_t)SERCOM5};
-const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35};
-
-#define USE_DPLL_IND 0
-#define USE_DPLL_DEF GCLK_SOURCE_DPLL0
-
-void CLK_oscctrl_init(void) {
- Oscctrl *posctrl = OSCCTRL;
- Gclk * pgclk = GCLK;
-
- DBGC(DC_CLK_OSC_INIT_BEGIN);
-
- // default setup on por
- system_clks.freq_dfll = FREQ_DFLL_DEFAULT;
- system_clks.freq_gclk[0] = system_clks.freq_dfll;
-
- // configure and startup 16MHz xosc0
- posctrl->XOSCCTRL[0].bit.ENABLE = 0;
- posctrl->XOSCCTRL[0].bit.STARTUP = 0xD;
- posctrl->XOSCCTRL[0].bit.ENALC = 1;
- posctrl->XOSCCTRL[0].bit.IMULT = 5;
- posctrl->XOSCCTRL[0].bit.IPTAT = 3;
- posctrl->XOSCCTRL[0].bit.ONDEMAND = 0;
- posctrl->XOSCCTRL[0].bit.XTALEN = 1;
- posctrl->XOSCCTRL[0].bit.ENABLE = 1;
- while (posctrl->STATUS.bit.XOSCRDY0 == 0) {
- DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC);
- }
- system_clks.freq_xosc0 = FREQ_XOSC0;
-
- // configure and startup DPLL
- posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 0;
- while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) {
- DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE);
- }
- posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; // select XOSC0 (16MHz)
- posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; // 16 MHz / (2 * (7 + 1)) = 1 MHz
- posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz
- while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) {
- DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO);
- }
- posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ONDEMAND = 0;
- posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 1;
- while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) {
- DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE);
- }
- while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) {
- DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK);
- }
- while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) {
- DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY);
- }
- system_clks.freq_dpll[0] = (system_clks.freq_xosc0 / 2 / (posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV + 1)) * (posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR + 1);
-
- // change gclk0 to DPLL
- pgclk->GENCTRL[GEN_DPLL0].bit.SRC = USE_DPLL_DEF;
- while (pgclk->SYNCBUSY.bit.GENCTRL0) {
- DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0);
- }
-
- system_clks.freq_gclk[0] = system_clks.freq_dpll[0];
-
- usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000);
- if (usec_delay_mult < 1) usec_delay_mult = 1; // Never allow a multiplier of zero
-
- DBGC(DC_CLK_OSC_INIT_COMPLETE);
-}
-
-// configure for 1MHz (1 usec timebase)
-// call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
-uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) {
- Gclk *pgclk = GCLK;
-
- DBGC(DC_CLK_SET_GCLK_FREQ_BEGIN);
-
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1);
- }
- pgclk->GENCTRL[gclkn].bit.SRC = USE_DPLL_DEF;
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2);
- }
- pgclk->GENCTRL[gclkn].bit.DIV = (uint8_t)(system_clks.freq_dpll[0] / freq);
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3);
- }
- pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4);
- }
- pgclk->GENCTRL[gclkn].bit.GENEN = 1;
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5);
- }
- system_clks.freq_gclk[gclkn] = system_clks.freq_dpll[0] / pgclk->GENCTRL[gclkn].bit.DIV;
-
- DBGC(DC_CLK_SET_GCLK_FREQ_COMPLETE);
-
- return system_clks.freq_gclk[gclkn];
-}
-
-void CLK_init_osc(void) {
- uint8_t gclkn = GEN_OSC0;
- Gclk * pgclk = GCLK;
-
- DBGC(DC_CLK_INIT_OSC_BEGIN);
-
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_INIT_OSC_SYNC_1);
- }
- pgclk->GENCTRL[gclkn].bit.SRC = GCLK_SOURCE_XOSC0;
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_INIT_OSC_SYNC_2);
- }
- pgclk->GENCTRL[gclkn].bit.DIV = 1;
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_INIT_OSC_SYNC_3);
- }
- pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_INIT_OSC_SYNC_4);
- }
- pgclk->GENCTRL[gclkn].bit.GENEN = 1;
- while (pgclk->SYNCBUSY.vec.GENCTRL) {
- DBGC(DC_CLK_INIT_OSC_SYNC_5);
- }
- system_clks.freq_gclk[gclkn] = system_clks.freq_xosc0;
-
- DBGC(DC_CLK_INIT_OSC_COMPLETE);
-}
-
-void CLK_reset_time(void) {
- Tc *ptc4 = TC4;
- Tc *ptc0 = TC0;
-
- ms_clk = 0;
-
- DBGC(DC_CLK_RESET_TIME_BEGIN);
-
- // stop counters
- ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
- while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {
- }
- ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
- while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {
- }
- // zero counters
- ptc4->COUNT16.COUNT.reg = 0;
- while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) {
- }
- ptc0->COUNT32.COUNT.reg = 0;
- while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) {
- }
- // start counters
- ptc0->COUNT32.CTRLA.bit.ENABLE = 1;
- while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {
- }
- ptc4->COUNT16.CTRLA.bit.ENABLE = 1;
- while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {
- }
-
- DBGC(DC_CLK_RESET_TIME_COMPLETE);
-}
-
-void TC4_Handler() {
- if (TC4->COUNT16.INTFLAG.bit.MC0) {
- TC4->COUNT16.INTFLAG.reg = TC_INTENCLR_MC0;
- ms_clk++;
- }
-}
-
-uint32_t CLK_enable_timebase(void) {
- Gclk * pgclk = GCLK;
- Mclk * pmclk = MCLK;
- Tc * ptc4 = TC4;
- Tc * ptc0 = TC0;
- Evsys *pevsys = EVSYS;
-
- DBGC(DC_CLK_ENABLE_TIMEBASE_BEGIN);
-
- // gclk2 highspeed time base
- CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
- CLK_init_osc();
-
- // unmask TC4, sourcegclk2 to TC4
- pmclk->APBCMASK.bit.TC4_ = 1;
- pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45;
- pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1;
-
- // configure TC4
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN);
- ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
- while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE);
- }
- ptc4->COUNT16.CTRLA.bit.SWRST = 1;
- while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1);
- }
- while (ptc4->COUNT16.CTRLA.bit.SWRST) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2);
- }
-
- // CTRLA defaults
- // CTRLB as default, counting up
- ptc4->COUNT16.CTRLBCLR.reg = 5;
- while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB);
- }
- ptc4->COUNT16.CC[0].reg = 999;
- while (ptc4->COUNT16.SYNCBUSY.bit.CC0) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0);
- }
- // ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1;
-
- // wave mode
- ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; // MFRQ match frequency mode, toggle each CC match
- // generate event for next stage
- ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1;
-
- NVIC_EnableIRQ(TC4_IRQn);
- ptc4->COUNT16.INTENSET.bit.MC0 = 1;
-
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE);
-
- // unmask TC0,1, sourcegclk2 to TC0,1
- pmclk->APBAMASK.bit.TC0_ = 1;
- pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45;
- pgclk->PCHCTRL[TC0_GCLK_ID].bit.CHEN = 1;
-
- pmclk->APBAMASK.bit.TC1_ = 1;
- pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN = GEN_TC45;
- pgclk->PCHCTRL[TC1_GCLK_ID].bit.CHEN = 1;
-
- // configure TC0
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN);
- ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
- while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE);
- }
- ptc0->COUNT32.CTRLA.bit.SWRST = 1;
- while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1);
- }
- while (ptc0->COUNT32.CTRLA.bit.SWRST) {
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2);
- }
- // CTRLA as default
- ptc0->COUNT32.CTRLA.bit.MODE = 2; // 32 bit mode
- ptc0->COUNT32.EVCTRL.bit.TCEI = 1; // enable incoming events
- ptc0->COUNT32.EVCTRL.bit.EVACT = 2; // count events
-
- DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE);
-
- DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN);
-
- // configure event system
- pmclk->APBBMASK.bit.EVSYS_ = 1;
- pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN = GEN_TC45;
- pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.CHEN = 1;
- pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; // TC0 will get event channel 0
- pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; // Rising edge
- pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; // Synchronous
- pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; // TC4 MC0
-
- DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE);
-
- CLK_reset_time();
-
- ADC0_clock_init();
-
- DBGC(DC_CLK_ENABLE_TIMEBASE_COMPLETE);
-
- return 0;
-}
-
-void CLK_delay_us(uint32_t usec) {
- asm("CBZ R0, return\n\t" // If usec == 0, branch to return label
- );
- asm("MULS R0, %0\n\t" // Multiply R0(usec) by usec_delay_mult and store in R0
- ".balign 16\n\t" // Ensure loop is aligned for fastest performance
- "loop: SUBS R0, #1\n\t" // Subtract 1 from R0 and update flags (1 cycle)
- "BNE loop\n\t" // Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles
- "return:\n\t" // Return label
- : // No output registers
- : "r"(usec_delay_mult) // For %0
- );
- // Note: BX LR generated
-}
-
-void CLK_delay_ms(uint64_t msec) {
- msec += timer_read64();
- while (msec > timer_read64()) {
- }
-}
-
-void clk_enable_sercom_apbmask(int sercomn) {
- Mclk *pmclk = MCLK;
- switch (sercomn) {
- case 0:
- pmclk->APBAMASK.bit.SERCOM0_ = 1;
- break;
- case 1:
- pmclk->APBAMASK.bit.SERCOM1_ = 1;
- break;
- case 2:
- pmclk->APBBMASK.bit.SERCOM2_ = 1;
- break;
- case 3:
- pmclk->APBBMASK.bit.SERCOM3_ = 1;
- break;
- default:
- break;
- }
-}
-
-// call CLK_oscctrl_init first
-// call CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
-uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq) {
- DBGC(DC_CLK_SET_SPI_FREQ_BEGIN);
-
- Gclk * pgclk = GCLK;
- Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
- clk_enable_sercom_apbmask(sercomn);
-
- // all gclk0 for now
- pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
- pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
-
- psercom->I2CM.CTRLA.bit.SWRST = 1;
- while (psercom->I2CM.SYNCBUSY.bit.SWRST) {
- }
- while (psercom->I2CM.CTRLA.bit.SWRST) {
- }
-
- psercom->SPI.BAUD.reg = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 1);
- system_clks.freq_spi = system_clks.freq_gclk[0] / 2 / (psercom->SPI.BAUD.reg + 1);
- system_clks.freq_sercom[sercomn] = system_clks.freq_spi;
-
- DBGC(DC_CLK_SET_SPI_FREQ_COMPLETE);
-
- return system_clks.freq_spi;
-}
-
-// call CLK_oscctrl_init first
-// call CLK_set_i2c0_freq(CHAN_SERCOM_I2C0, FREQ_I2C0_DEFAULT);
-uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq) {
- DBGC(DC_CLK_SET_I2C0_FREQ_BEGIN);
-
- Gclk * pgclk = GCLK;
- Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
- clk_enable_sercom_apbmask(sercomn);
-
- // all gclk0 for now
- pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
- pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
-
- psercom->I2CM.CTRLA.bit.SWRST = 1;
- while (psercom->I2CM.SYNCBUSY.bit.SWRST) {
- }
- while (psercom->I2CM.CTRLA.bit.SWRST) {
- }
-
- psercom->I2CM.BAUD.bit.BAUD = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 1);
- system_clks.freq_i2c0 = system_clks.freq_gclk[0] / 2 / (psercom->I2CM.BAUD.bit.BAUD + 1);
- system_clks.freq_sercom[sercomn] = system_clks.freq_i2c0;
-
- DBGC(DC_CLK_SET_I2C0_FREQ_COMPLETE);
-
- return system_clks.freq_i2c0;
-}
-
-// call CLK_oscctrl_init first
-// call CLK_set_i2c1_freq(CHAN_SERCOM_I2C1, FREQ_I2C1_DEFAULT);
-uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq) {
- DBGC(DC_CLK_SET_I2C1_FREQ_BEGIN);
-
- Gclk * pgclk = GCLK;
- Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
- clk_enable_sercom_apbmask(sercomn);
-
- // all gclk0 for now
- pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
- pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
-
- psercom->I2CM.CTRLA.bit.SWRST = 1;
- while (psercom->I2CM.SYNCBUSY.bit.SWRST) {
- }
- while (psercom->I2CM.CTRLA.bit.SWRST) {
- }
-
- psercom->I2CM.BAUD.bit.BAUD = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 10);
- system_clks.freq_i2c1 = system_clks.freq_gclk[0] / 2 / (psercom->I2CM.BAUD.bit.BAUD + 10);
- system_clks.freq_sercom[sercomn] = system_clks.freq_i2c1;
-
- DBGC(DC_CLK_SET_I2C1_FREQ_COMPLETE);
-
- return system_clks.freq_i2c1;
-}
-
-void CLK_init(void) {
- DBGC(DC_CLK_INIT_BEGIN);
-
- memset((void *)&system_clks, 0, sizeof(system_clks));
-
- CLK_oscctrl_init();
- CLK_enable_timebase();
-
- DBGC(DC_CLK_INIT_COMPLETE);
-}
diff --git a/tmk_core/protocol/arm_atsam/clks.h b/tmk_core/protocol/arm_atsam/clks.h
deleted file mode 100644
index 6ee71aff8fa6..000000000000
--- a/tmk_core/protocol/arm_atsam/clks.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _CLKS_H_
-#define _CLKS_H_
-
-#ifndef MD_BOOTLOADER
-
-// From keyboard
-# include "config_led.h"
-# include "config.h"
-
-#endif // MD_BOOTLOADER
-
-#define PLL_RATIO 47 // mcu frequency ((X+1)MHz)
-#define FREQ_DFLL_DEFAULT 48000000 // DFLL frequency / usb clock
-#define FREQ_SPI_DEFAULT 1000000 // spi to 595 shift regs
-#define FREQ_I2C0_DEFAULT 100000 // i2c to hub
-#define FREQ_I2C1_DEFAULT I2C_HZ // i2c to LED drivers
-#define FREQ_TC45_DEFAULT 1000000 // 1 usec resolution
-
-// I2C1 Set ~Result PWM Time (2x Drivers)
-// 1000000 1090000
-// 900000 1000000 3.82ms
-// 800000 860000
-// 700000 750000
-// 600000 630000
-// 580000 615000 6.08ms
-// 500000 522000
-
-#define FREQ_XOSC0 16000000
-
-#define CHAN_SERCOM_SPI 2 // shift regs
-#define CHAN_SERCOM_I2C0 0 // hub
-#define CHAN_SERCOM_I2C1 1 // led drivers
-#define CHAN_SERCOM_UART 3 // debug util
-
-// Generator clock channels
-#define GEN_DPLL0 0
-#define GEN_OSC0 1
-#define GEN_TC45 2
-
-#define SERCOM_COUNT 5
-#define GCLK_COUNT 12
-
-typedef struct clk_s {
- uint32_t freq_dfll;
- uint32_t freq_dpll[2];
- uint32_t freq_sercom[SERCOM_COUNT];
- uint32_t freq_gclk[GCLK_COUNT];
- uint32_t freq_xosc0;
- uint32_t freq_spi;
- uint32_t freq_i2c0;
- uint32_t freq_i2c1;
- uint32_t freq_uart;
- uint32_t freq_adc0;
-} clk_t;
-
-extern volatile clk_t system_clks;
-extern volatile uint64_t ms_clk;
-
-void CLK_oscctrl_init(void);
-void CLK_reset_time(void);
-uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq);
-uint32_t CLK_enable_timebase(void);
-uint64_t timer_read64(void);
-void CLK_delay_us(uint32_t usec);
-void CLK_delay_ms(uint64_t msec);
-
-uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq);
-uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq);
-uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq);
-void CLK_init(void);
-
-#endif // _CLKS_H_
diff --git a/tmk_core/protocol/arm_atsam/d51_util.c b/tmk_core/protocol/arm_atsam/d51_util.c
deleted file mode 100644
index 590323308563..000000000000
--- a/tmk_core/protocol/arm_atsam/d51_util.c
+++ /dev/null
@@ -1,244 +0,0 @@
-#include "d51_util.h"
-
-static volatile uint32_t w;
-
-// Display unsigned 32-bit number by port toggling DBG_1 (to view on a scope)
-// Read as follows: 1230 = | | | | | | || (note zero is fast double toggle)
-#define DBG_PAUSE 5
-void dbg_print(uint32_t x) {
- int8_t t;
- uint32_t n;
- uint32_t p, p2;
-
- if (x < 10)
- t = 0;
- else if (x < 100)
- t = 1;
- else if (x < 1000)
- t = 2;
- else if (x < 10000)
- t = 3;
- else if (x < 100000)
- t = 4;
- else if (x < 1000000)
- t = 5;
- else if (x < 10000000)
- t = 6;
- else if (x < 100000000)
- t = 7;
- else if (x < 1000000000)
- t = 8;
- else
- t = 9;
-
- while (t >= 0) {
- p2 = t;
- p = 1;
- while (p2--)
- p *= 10;
- n = x / p;
- x -= n * p;
- if (!n) {
- DBG_1_ON;
- DBG_1_OFF;
- DBG_1_ON;
- DBG_1_OFF;
- n--;
- } else {
- while (n > 0) {
- DBG_1_ON;
- DBG_1_OFF;
- n--;
- }
- }
-
- t--;
- }
-
- for (w = DBG_PAUSE; w; w--)
- ; // Long pause after number is complete
-}
-
-// Display unsigned 32-bit number through debug led
-// Read as follows: 1230 = [*] [* *] [* * *] [**] (note zero is fast double flash)
-#define DLED_ONTIME 1000000
-#define DLED_PAUSE 1500000
-void dled_print(uint32_t x, uint8_t long_pause) {
- int8_t t;
- uint32_t n;
- uint32_t p, p2;
-
- if (x < 10)
- t = 0;
- else if (x < 100)
- t = 1;
- else if (x < 1000)
- t = 2;
- else if (x < 10000)
- t = 3;
- else if (x < 100000)
- t = 4;
- else if (x < 1000000)
- t = 5;
- else if (x < 10000000)
- t = 6;
- else if (x < 100000000)
- t = 7;
- else if (x < 1000000000)
- t = 8;
- else
- t = 9;
-
- while (t >= 0) {
- p2 = t;
- p = 1;
- while (p2--)
- p *= 10;
- n = x / p;
- x -= n * p;
- if (!n) {
- DBG_LED_ON;
- for (w = DLED_ONTIME / 4; w; w--)
- ;
- DBG_LED_OFF;
- for (w = DLED_ONTIME / 4; w; w--)
- ;
- DBG_LED_ON;
- for (w = DLED_ONTIME / 4; w; w--)
- ;
- DBG_LED_OFF;
- for (w = DLED_ONTIME / 4; w; w--)
- ;
- n--;
- } else {
- while (n > 0) {
- DBG_LED_ON;
- for (w = DLED_ONTIME; w; w--)
- ;
- DBG_LED_OFF;
- for (w = DLED_ONTIME / 2; w; w--)
- ;
- n--;
- }
- }
-
- for (w = DLED_PAUSE; w; w--)
- ;
- t--;
- }
-
- if (long_pause) {
- for (w = DLED_PAUSE * 4; w; w--)
- ;
- }
-}
-
-#ifdef DEBUG_BOOT_TRACING_ENABLE
-
-volatile uint32_t debug_code;
-
-// These macros are for compile time substitution
-# define DEBUG_BOOT_TRACING_EXTINTn (DEBUG_BOOT_TRACING_PIN % _U_(0x10))
-# define DEBUG_BOOT_TRACING_EXTINTb (_U_(0x1) << DEBUG_BOOT_TRACING_EXTINTn)
-# define DEBUG_BOOT_TRACING_CONFIG_INDn (DEBUG_BOOT_TRACING_EXTINTn / _U_(0x8))
-# define DEBUG_BOOT_TRACING_CONFIG_SENSEn (DEBUG_BOOT_TRACING_EXTINTn % _U_(0x8))
-# define DEBUG_BOOT_TRACING_CONFIG_SENSEb (DEBUG_BOOT_TRACING_CONFIG_SENSEn * _U_(0x4))
-# define DEBUG_BOOT_TRACING_IRQn (EIC_0_IRQn + DEBUG_BOOT_TRACING_EXTINTn)
-
-// These macros perform PORT+PIN definition translation to IRQn in the preprocessor
-# define PORTPIN_TO_IRQn_EXPAND(def) def
-# define PORTPIN_TO_IRQn_DEF(def) PORTPIN_TO_IRQn_EXPAND(def)
-# if DEBUG_BOOT_TRACING_PIN < 10
-# define PORTPIN_TO_IRQn_TODEF(port, pin) PORTPIN_TO_IRQn_DEF(PIN_##port##0##pin##A_EIC_EXTINT_NUM)
-# else
-# define PORTPIN_TO_IRQn_TODEF(port, pin) PORTPIN_TO_IRQn_DEF(PIN_##port##pin##A_EIC_EXTINT_NUM)
-# endif
-# define PORTPIN_TO_IRQn(port, pin) PORTPIN_TO_IRQn_TODEF(port, pin)
-
-// These macros perform function name output in the preprocessor
-# define DEBUG_BOOT_TRACING_HANDLER_CONCAT(irq) void EIC_##irq##_Handler(void)
-# define DEBUG_BOOT_TRACING_HANDLER(irq) DEBUG_BOOT_TRACING_HANDLER_CONCAT(irq)
-
-// To generate the function name of the IRQ handler catching boot tracing,
-// certain macros must be undefined, so save their current values to macro stack
-# pragma push_macro("PA")
-# pragma push_macro("PB")
-# pragma push_macro("_L_")
-
-// Undefine / redefine pushed macros
-# undef PA
-# undef PB
-# undef _L_
-# define _L_(x) x
-
-// Perform the work and output
-// Ex: PORT PB, PIN 31 = void EIC_15_Handler(void)
-DEBUG_BOOT_TRACING_HANDLER(PORTPIN_TO_IRQn(DEBUG_BOOT_TRACING_PORT, DEBUG_BOOT_TRACING_PIN))
-// Restore macros
-# pragma pop_macro("PA")
-# pragma pop_macro("PB")
-# pragma pop_macro("_L_")
-{
- // This is only for non-functional keyboard troubleshooting and should be disabled after boot
- // Intention is to lock up the keyboard here with repeating debug led code
- while (1) {
- dled_print(debug_code, 1);
- }
-}
-
-void debug_code_init(void) {
- DBGC(DC_UNSET);
-
- // Configure Ports for EIC
- PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input
- PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTSET.reg = 1 << DEBUG_BOOT_TRACING_PIN; // High
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 1; // Input Enable
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 1; // Pull Enable
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 1; // Mux Enable
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A
-
- // Enable CLK_EIC_APB
- MCLK->APBAMASK.bit.EIC_ = 1;
-
- // Configure EIC
- EIC->CTRLA.bit.SWRST = 1;
- while (EIC->SYNCBUSY.bit.SWRST) {
- }
- EIC->ASYNCH.reg = DEBUG_BOOT_TRACING_EXTINTb;
- EIC->INTENSET.reg = DEBUG_BOOT_TRACING_EXTINTb;
- EIC->CONFIG[DEBUG_BOOT_TRACING_CONFIG_INDn].reg |= (EIC_CONFIG_SENSE0_FALL_Val << DEBUG_BOOT_TRACING_CONFIG_SENSEb);
- EIC->CTRLA.bit.ENABLE = 1;
- while (EIC->SYNCBUSY.bit.ENABLE) {
- }
-
- // Enable EIC IRQ
- NVIC_EnableIRQ(DEBUG_BOOT_TRACING_IRQn);
-}
-
-void debug_code_disable(void) {
- // Disable EIC IRQ
- NVIC_DisableIRQ(DEBUG_BOOT_TRACING_IRQn);
-
- // Disable EIC
- EIC->CTRLA.bit.ENABLE = 0;
- while (EIC->SYNCBUSY.bit.ENABLE) {
- }
-
- // Default port configuration
- PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input
- PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Low
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 0; // Input Disable
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 0; // Pull Disable
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 0; // Mux Disable
- PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A
-
- // Disable CLK_EIC_APB
- MCLK->APBAMASK.bit.EIC_ = 0;
-}
-
-#else
-
-void debug_code_init(void) {}
-void debug_code_disable(void) {}
-
-#endif // DEBUG_BOOT_TRACING_ENABLE
diff --git a/tmk_core/protocol/arm_atsam/d51_util.h b/tmk_core/protocol/arm_atsam/d51_util.h
deleted file mode 100644
index d301e5541140..000000000000
--- a/tmk_core/protocol/arm_atsam/d51_util.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _D51_UTIL_H_
-#define _D51_UTIL_H_
-
-#include "samd51j18a.h"
-
-/* Debug LED */
-#if DEBUG_LED_ENABLE == 1
-# define DBG_LED_ENA PORT->Group[DEBUG_LED_PORT].DIRSET.reg = (1 << DEBUG_LED_PIN)
-# define DBG_LED_DIS PORT->Group[DEBUG_LED_PORT].DIRCLR.reg = (1 << DEBUG_LED_PIN)
-# define DBG_LED_ON PORT->Group[DEBUG_LED_PORT].OUTSET.reg = (1 << DEBUG_LED_PIN)
-# define DBG_LED_OFF PORT->Group[DEBUG_LED_PORT].OUTCLR.reg = (1 << DEBUG_LED_PIN)
-#else
-# define DBG_LED_ENA
-# define DBG_LED_DIS
-# define DBG_LED_ON
-# define DBG_LED_OFF
-#endif
-
-/* Debug Port 1 */
-#if DEBUG_PORT1_ENABLE == 1
-# define DBG_1_ENA PORT->Group[DEBUG_PORT1_PORT].DIRSET.reg = (1 << DEBUG_PORT1_PIN)
-# define DBG_1_DIS PORT->Group[DEBUG_PORT1_PORT].DIRCLR.reg = (1 << DEBUG_PORT1_PIN)
-# define DBG_1_ON PORT->Group[DEBUG_PORT1_PORT].OUTSET.reg = (1 << DEBUG_PORT1_PIN)
-# define DBG_1_OFF PORT->Group[DEBUG_PORT1_PORT].OUTCLR.reg = (1 << DEBUG_PORT1_PIN)
-#else
-# define DBG_1_ENA
-# define DBG_1_DIS
-# define DBG_1_ON
-# define DBG_1_OFF
-#endif
-
-/* Debug Port 2 */
-#if DEBUG_PORT2_ENABLE == 1
-# define DBG_2_ENA PORT->Group[DEBUG_PORT2_PORT].DIRSET.reg = (1 << DEBUG_PORT2_PIN)
-# define DBG_2_DIS PORT->Group[DEBUG_PORT2_PORT].DIRCLR.reg = (1 << DEBUG_PORT2_PIN)
-# define DBG_2_ON PORT->Group[DEBUG_PORT2_PORT].OUTSET.reg = (1 << DEBUG_PORT2_PIN)
-# define DBG_2_OFF PORT->Group[DEBUG_PORT2_PORT].OUTCLR.reg = (1 << DEBUG_PORT2_PIN)
-#else
-# define DBG_2_ENA
-# define DBG_2_DIS
-# define DBG_2_ON
-# define DBG_2_OFF
-#endif
-
-/* Debug Port 3 */
-#if DEBUG_PORT3_ENABLE == 1
-# define DBG_3_ENA PORT->Group[DEBUG_PORT3_PORT].DIRSET.reg = (1 << DEBUG_PORT3_PIN)
-# define DBG_3_DIS PORT->Group[DEBUG_PORT3_PORT].DIRCLR.reg = (1 << DEBUG_PORT3_PIN)
-# define DBG_3_ON PORT->Group[DEBUG_PORT3_PORT].OUTSET.reg = (1 << DEBUG_PORT3_PIN)
-# define DBG_3_OFF PORT->Group[DEBUG_PORT3_PORT].OUTCLR.reg = (1 << DEBUG_PORT3_PIN)
-#else
-# define DBG_3_ENA
-# define DBG_3_DIS
-# define DBG_3_ON
-# define DBG_3_OFF
-#endif
-
-void dbg_print(uint32_t x);
-void dled_print(uint32_t x, uint8_t long_pause);
-
-void debug_code_init(void);
-void debug_code_disable(void);
-
-#ifdef DEBUG_BOOT_TRACING_ENABLE
-
-# define DBGC(n) debug_code = n
-
-extern volatile uint32_t debug_code;
-
-enum debug_code_list {
- DC_UNSET = 0,
- DC_CLK_INIT_BEGIN,
- DC_CLK_INIT_COMPLETE,
- DC_CLK_SET_I2C1_FREQ_BEGIN,
- DC_CLK_SET_I2C1_FREQ_COMPLETE,
- DC_CLK_SET_I2C0_FREQ_BEGIN,
- DC_CLK_SET_I2C0_FREQ_COMPLETE,
- DC_CLK_SET_SPI_FREQ_BEGIN,
- DC_CLK_SET_SPI_FREQ_COMPLETE,
- DC_CLK_ENABLE_TIMEBASE_BEGIN,
- DC_CLK_ENABLE_TIMEBASE_SYNC_ENABLE,
- DC_CLK_ENABLE_TIMEBASE_SYNC_SWRST_1,
- DC_CLK_ENABLE_TIMEBASE_SYNC_SWRST_2,
- DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN,
- DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE,
- DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1,
- DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2,
- DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB,
- DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0,
- DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE,
- DC_CLK_ENABLE_TIMEBASE_TC5_BEGIN,
- DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_DISABLE,
- DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_1,
- DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_2,
- DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_CLTRB,
- DC_CLK_ENABLE_TIMEBASE_TC5_COMPLETE,
- DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN,
- DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE,
- DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1,
- DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2,
- DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE,
- DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN,
- DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE,
- DC_CLK_ENABLE_TIMEBASE_COMPLETE,
- DC_CLK_SET_GCLK_FREQ_BEGIN,
- DC_CLK_SET_GCLK_FREQ_SYNC_1,
- DC_CLK_SET_GCLK_FREQ_SYNC_2,
- DC_CLK_SET_GCLK_FREQ_SYNC_3,
- DC_CLK_SET_GCLK_FREQ_SYNC_4,
- DC_CLK_SET_GCLK_FREQ_SYNC_5,
- DC_CLK_SET_GCLK_FREQ_COMPLETE,
- DC_CLK_INIT_OSC_BEGIN,
- DC_CLK_INIT_OSC_SYNC_1,
- DC_CLK_INIT_OSC_SYNC_2,
- DC_CLK_INIT_OSC_SYNC_3,
- DC_CLK_INIT_OSC_SYNC_4,
- DC_CLK_INIT_OSC_SYNC_5,
- DC_CLK_INIT_OSC_COMPLETE,
- DC_CLK_RESET_TIME_BEGIN,
- DC_CLK_RESET_TIME_COMPLETE,
- DC_CLK_OSC_INIT_BEGIN,
- DC_CLK_OSC_INIT_XOSC0_SYNC,
- DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE,
- DC_CLK_OSC_INIT_DPLL_SYNC_RATIO,
- DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE,
- DC_CLK_OSC_INIT_DPLL_WAIT_LOCK,
- DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY,
- DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0,
- DC_CLK_OSC_INIT_COMPLETE,
- DC_SPI_INIT_BEGIN,
- DC_SPI_WRITE_DRE,
- DC_SPI_WRITE_TXC_1,
- DC_SPI_WRITE_TXC_2,
- DC_SPI_SYNC_ENABLING,
- DC_SPI_INIT_COMPLETE,
- DC_PORT_DETECT_INIT_BEGIN,
- DC_PORT_DETECT_INIT_FAILED,
- DC_PORT_DETECT_INIT_COMPLETE,
- DC_USB_RESET_BEGIN,
- DC_USB_RESET_COMPLETE,
- DC_USB_SET_HOST_BY_VOLTAGE_BEGIN,
- DC_USB_SET_HOST_5V_LOW_WAITING,
- DC_USB_SET_HOST_BY_VOLTAGE_COMPLETE,
- DC_USB_CONFIGURE_BEGIN,
- DC_USB_CONFIGURE_GET_SERIAL,
- DC_USB_CONFIGURE_COMPLETE,
- DC_USB_WRITE2422_BLOCK_BEGIN,
- DC_USB_WRITE2422_BLOCK_SYNC_SYSOP,
- DC_USB_WRITE2422_BLOCK_COMPLETE,
- DC_ADC0_CLOCK_INIT_BEGIN,
- DC_ADC0_CLOCK_INIT_COMPLETE,
- DC_ADC0_INIT_BEGIN,
- DC_ADC0_SWRST_SYNCING_1,
- DC_ADC0_SWRST_SYNCING_2,
- DC_ADC0_AVGCTRL_SYNCING_1,
- DC_ADC0_AVGCTRL_SYNCING_2,
- DC_ADC0_SAMPCTRL_SYNCING_1,
- DC_ADC0_ENABLE_SYNCING_1,
- DC_ADC0_INIT_COMPLETE,
- DC_I2C0_INIT_BEGIN,
- DC_I2C0_INIT_SYNC_ENABLING,
- DC_I2C0_INIT_SYNC_SYSOP,
- DC_I2C0_INIT_WAIT_IDLE,
- DC_I2C0_INIT_COMPLETE,
- DC_I2C1_INIT_BEGIN,
- DC_I2C1_INIT_SYNC_ENABLING,
- DC_I2C1_INIT_SYNC_SYSOP,
- DC_I2C1_INIT_WAIT_IDLE,
- DC_I2C1_INIT_COMPLETE,
- DC_I2C3733_INIT_CONTROL_BEGIN,
- DC_I2C3733_INIT_CONTROL_COMPLETE,
- DC_I2C3733_INIT_DRIVERS_BEGIN,
- DC_I2C3733_INIT_DRIVERS_COMPLETE,
- DC_I2C_DMAC_LED_INIT_BEGIN,
- DC_I2C_DMAC_LED_INIT_COMPLETE,
- DC_I2C3733_CONTROL_SET_BEGIN,
- DC_I2C3733_CONTROL_SET_COMPLETE,
- DC_LED_MATRIX_INIT_BEGIN,
- DC_LED_MATRIX_INIT_COMPLETE,
- DC_USB2422_INIT_BEGIN,
- DC_USB2422_INIT_WAIT_5V_LOW,
- DC_USB2422_INIT_OSC_SYNC_DISABLING,
- DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_1,
- DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_2,
- DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_3,
- DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_4,
- DC_USB2422_INIT_OSC_SYNC_DFLLMUL,
- DC_USB2422_INIT_OSC_SYNC_ENABLING,
- DC_USB2422_INIT_USB_SYNC_SWRST,
- DC_USB2422_INIT_USB_WAIT_SWRST,
- DC_USB2422_INIT_USB_SYNC_ENABLING,
- DC_USB2422_INIT_COMPLETE,
- DC_MAIN_UDC_START_BEGIN,
- DC_MAIN_UDC_START_COMPLETE,
- DC_MAIN_CDC_INIT_BEGIN,
- DC_MAIN_CDC_INIT_COMPLETE,
- /* Never change the order of error codes! Only add codes to end! */
-};
-
-#else
-
-# define DBGC(n) \
- {}
-
-#endif // DEBUG_BOOT_TRACING_ENABLE
-
-#endif //_D51_UTIL_H_
diff --git a/tmk_core/protocol/arm_atsam/i2c_master.c b/tmk_core/protocol/arm_atsam/i2c_master.c
deleted file mode 100644
index 07ffcc817274..000000000000
--- a/tmk_core/protocol/arm_atsam/i2c_master.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "arm_atsam_protocol.h"
-
-#if !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE)
-
-# include
-
-// From keyboard
-# include "config.h"
-# include "config_led.h"
-# include "matrix.h"
-
-# define I2C_LED_USE_DMA 1 // Set 1 to use background DMA transfers for leds, Set 0 to use inline software transfers
-
-DmacDescriptor dmac_desc;
-DmacDescriptor dmac_desc_wb;
-
-static uint8_t i2c_led_q[I2C_Q_SIZE]; // I2C queue circular buffer
-static uint8_t i2c_led_q_s; // Start of circular buffer
-static uint8_t i2c_led_q_e; // End of circular buffer
-static uint8_t i2c_led_q_full; // Queue full counter for reset
-
-static uint8_t dma_sendbuf[I2C_DMA_MAX_SEND]; // Data being written to I2C
-
-volatile uint8_t i2c_led_q_running;
-
-#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE)
-
-void i2c0_init(void) {
- DBGC(DC_I2C0_INIT_BEGIN);
-
- CLK_set_i2c0_freq(CHAN_SERCOM_I2C0, FREQ_I2C0_DEFAULT);
-
- // MCU
- PORT->Group[0].PMUX[4].bit.PMUXE = 2;
- PORT->Group[0].PMUX[4].bit.PMUXO = 2;
- PORT->Group[0].PINCFG[8].bit.PMUXEN = 1;
- PORT->Group[0].PINCFG[9].bit.PMUXEN = 1;
-
- // I2C
- // Note: SW Reset handled in CLK_set_i2c0_freq clks.c
-
- SERCOM0->I2CM.CTRLA.bit.MODE = 5; // Set master mode
-
- SERCOM0->I2CM.CTRLA.bit.SPEED = 0; // Set to 1 for Fast-mode Plus (FM+) up to 1 MHz
- SERCOM0->I2CM.CTRLA.bit.RUNSTDBY = 1; // Enabled
-
- SERCOM0->I2CM.CTRLA.bit.ENABLE = 1; // Enable the device
- while (SERCOM0->I2CM.SYNCBUSY.bit.ENABLE) {
- DBGC(DC_I2C0_INIT_SYNC_ENABLING);
- } // Wait for SYNCBUSY.ENABLE to clear
-
- SERCOM0->I2CM.STATUS.bit.BUSSTATE = 1; // Force into IDLE state
- while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP) {
- DBGC(DC_I2C0_INIT_SYNC_SYSOP);
- }
- while (SERCOM0->I2CM.STATUS.bit.BUSSTATE != 1) {
- DBGC(DC_I2C0_INIT_WAIT_IDLE);
- } // Wait while not idle
-
- DBGC(DC_I2C0_INIT_COMPLETE);
-}
-
-uint8_t i2c0_start(uint8_t address) {
- SERCOM0->I2CM.ADDR.bit.ADDR = address;
- while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP) {
- }
- while (SERCOM0->I2CM.INTFLAG.bit.MB == 0) {
- }
- while (SERCOM0->I2CM.STATUS.bit.RXNACK) {
- }
-
- return 1;
-}
-
-uint8_t i2c0_transmit(uint8_t address, uint8_t *data, uint16_t length, uint16_t timeout) {
- if (!length) return 0;
-
- i2c0_start(address);
-
- while (length) {
- SERCOM0->I2CM.DATA.bit.DATA = *data;
- while (SERCOM0->I2CM.INTFLAG.bit.MB == 0) {
- }
- while (SERCOM0->I2CM.STATUS.bit.RXNACK) {
- }
-
- data++;
- length--;
- }
-
- i2c0_stop();
-
- return 1;
-}
-
-void i2c0_stop(void) {
- if (SERCOM0->I2CM.STATUS.bit.CLKHOLD || SERCOM0->I2CM.INTFLAG.bit.MB == 1 || SERCOM0->I2CM.STATUS.bit.BUSSTATE != 1) {
- SERCOM0->I2CM.CTRLB.bit.CMD = 3;
- while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP)
- ;
- while (SERCOM0->I2CM.STATUS.bit.CLKHOLD)
- ;
- while (SERCOM0->I2CM.INTFLAG.bit.MB)
- ;
- while (SERCOM0->I2CM.STATUS.bit.BUSSTATE != 1)
- ;
- }
-}
-
-#if !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE)
-void i2c1_init(void) {
- DBGC(DC_I2C1_INIT_BEGIN);
-
- CLK_set_i2c1_freq(CHAN_SERCOM_I2C1, FREQ_I2C1_DEFAULT);
-
- /* MCU */
- PORT->Group[0].PMUX[8].bit.PMUXE = 2;
- PORT->Group[0].PMUX[8].bit.PMUXO = 2;
- PORT->Group[0].PINCFG[16].bit.PMUXEN = 1;
- PORT->Group[0].PINCFG[17].bit.PMUXEN = 1;
-
- /* I2C */
- // Note: SW Reset handled in CLK_set_i2c1_freq clks.c
-
- SERCOM1->I2CM.CTRLA.bit.MODE = 5; // MODE: Set master mode (No sync)
- SERCOM1->I2CM.CTRLA.bit.SPEED = 1; // SPEED: Fm+ up to 1MHz (No sync)
- SERCOM1->I2CM.CTRLA.bit.RUNSTDBY = 1; // RUNSTBY: Enabled (No sync)
-
- SERCOM1->I2CM.CTRLB.bit.SMEN = 1; // SMEN: Smart mode enabled (For DMA)(No sync)
-
- NVIC_EnableIRQ(SERCOM1_0_IRQn);
- SERCOM1->I2CM.INTENSET.bit.ERROR = 1;
-
- SERCOM1->I2CM.CTRLA.bit.ENABLE = 1; // ENABLE: Enable the device (sync SYNCBUSY.ENABLE)
- while (SERCOM1->I2CM.SYNCBUSY.bit.ENABLE) {
- DBGC(DC_I2C1_INIT_SYNC_ENABLING);
- } // Wait for SYNCBUSY.ENABLE to clear
-
- SERCOM1->I2CM.STATUS.bit.BUSSTATE = 1; // BUSSTATE: Force into IDLE state (sync SYNCBUSY.SYSOP)
- while (SERCOM1->I2CM.SYNCBUSY.bit.SYSOP) {
- DBGC(DC_I2C1_INIT_SYNC_SYSOP);
- }
- while (SERCOM1->I2CM.STATUS.bit.BUSSTATE != 1) {
- DBGC(DC_I2C1_INIT_WAIT_IDLE);
- } // Wait while not idle
-
- DBGC(DC_I2C1_INIT_COMPLETE);
-}
-
-uint8_t i2c1_start(uint8_t address) {
- SERCOM1->I2CM.ADDR.bit.ADDR = address;
- while (SERCOM1->I2CM.SYNCBUSY.bit.SYSOP) {
- }
- while (SERCOM1->I2CM.INTFLAG.bit.MB == 0) {
- }
- while (SERCOM1->I2CM.STATUS.bit.RXNACK) {
- }
-
- return 1;
-}
-
-uint8_t i2c1_transmit(uint8_t address, uint8_t *data, uint16_t length, uint16_t timeout) {
- if (!length) return 0;
-
- i2c1_start(address);
-
- while (length) {
- SERCOM1->I2CM.DATA.bit.DATA = *data;
- while (SERCOM1->I2CM.INTFLAG.bit.MB == 0) {
- }
- while (SERCOM1->I2CM.STATUS.bit.RXNACK) {
- }
-
- data++;
- length--;
- }
-
- i2c1_stop();
-
- return 1;
-}
-
-void i2c1_stop(void) {
- if (SERCOM1->I2CM.STATUS.bit.CLKHOLD || SERCOM1->I2CM.INTFLAG.bit.MB == 1 || SERCOM1->I2CM.STATUS.bit.BUSSTATE != 1) {
- SERCOM1->I2CM.CTRLB.bit.CMD = 3;
- while (SERCOM1->I2CM.SYNCBUSY.bit.SYSOP)
- ;
- while (SERCOM1->I2CM.STATUS.bit.CLKHOLD)
- ;
- while (SERCOM1->I2CM.INTFLAG.bit.MB)
- ;
- while (SERCOM1->I2CM.STATUS.bit.BUSSTATE != 1)
- ;
- }
-}
-
-void i2c_led_send_CRWL(uint8_t drvid) {
- uint8_t i2cdata[] = {ISSI3733_CMDRWL, ISSI3733_CMDRWL_WRITE_ENABLE_ONCE};
- i2c1_transmit(issidrv[drvid].addr, i2cdata, sizeof(i2cdata), 0);
-}
-
-void i2c_led_select_page(uint8_t drvid, uint8_t pageno) {
- uint8_t i2cdata[] = {ISSI3733_CMDR, pageno};
- i2c1_transmit(issidrv[drvid].addr, i2cdata, sizeof(i2cdata), 0);
-}
-
-void i2c_led_send_GCR(uint8_t drvid) {
- uint8_t i2cdata[] = {ISSI3733_GCCR, 0x00};
-
- if (gcr_actual > LED_GCR_MAX) gcr_actual = LED_GCR_MAX;
- i2cdata[1] = gcr_actual;
-
- i2c1_transmit(issidrv[drvid].addr, i2cdata, sizeof(i2cdata), 0);
-}
-
-void i2c_led_send_onoff(uint8_t drvid) {
-# if I2C_LED_USE_DMA != 1
- if (!i2c_led_q_running) {
-# endif
- i2c_led_send_CRWL(drvid);
- i2c_led_select_page(drvid, 0);
-# if I2C_LED_USE_DMA != 1
- }
-# endif
-
- *issidrv[drvid].onoff = 0; // Force start location offset to zero
- i2c1_transmit(issidrv[drvid].addr, issidrv[drvid].onoff, ISSI3733_PG0_BYTES, 0);
-}
-
-void i2c_led_send_mode_op_gcr(uint8_t drvid, uint8_t mode, uint8_t operation) {
- uint8_t i2cdata[] = {ISSI3733_CR, mode | operation, gcr_actual};
- i2c1_transmit(issidrv[drvid].addr, i2cdata, sizeof(i2cdata), 0);
-}
-
-void i2c_led_send_pur_pdr(uint8_t drvid, uint8_t pur, uint8_t pdr) {
- uint8_t i2cdata[] = {ISSI3733_SWYR_PUR, pur, pdr};
-
- i2c1_transmit(issidrv[drvid].addr, i2cdata, sizeof(i2cdata), 0);
-}
-
-void i2c_led_send_pwm(uint8_t drvid) {
-# if I2C_LED_USE_DMA != 1
- if (!i2c_led_q_running) {
-# endif
- i2c_led_send_CRWL(drvid);
- i2c_led_select_page(drvid, 0);
-# if I2C_LED_USE_DMA != 1
- }
-# endif
-
- *issidrv[drvid].pwm = 0; // Force start location offset to zero
- i2c1_transmit(issidrv[drvid].addr, issidrv[drvid].pwm, ISSI3733_PG1_BYTES, 0);
-}
-
-uint8_t I2C3733_Init_Control(void) {
- DBGC(DC_I2C3733_INIT_CONTROL_BEGIN);
-
- // Hardware state shutdown on boot
- // USB state machine will enable driver when communication is ready
- I2C3733_Control_Set(0);
-
- wait_ms(1);
-
- sr_exp_data.bit.IRST = 0;
- SR_EXP_WriteData();
-
- wait_ms(1);
-
- DBGC(DC_I2C3733_INIT_CONTROL_COMPLETE);
-
- return 1;
-}
-
-uint8_t I2C3733_Init_Drivers(void) {
- DBGC(DC_I2C3733_INIT_DRIVERS_BEGIN);
-
- gcr_actual = ISSI3733_GCR_DEFAULT;
- gcr_actual_last = gcr_actual;
-
- if (gcr_actual > LED_GCR_MAX) gcr_actual = LED_GCR_MAX;
- gcr_desired = gcr_actual;
-
- void issi3733_prepare_arrays(void);
- issi3733_prepare_arrays();
-
- // Set up master device
- i2c_led_send_CRWL(0);
- i2c_led_select_page(0, 3);
- i2c_led_send_mode_op_gcr(0, 0, ISSI3733_CR_SSD_NORMAL); // No SYNC due to brightness mismatch with second driver
-
- // Set up slave device
- i2c_led_send_CRWL(1);
- i2c_led_select_page(1, 3);
- i2c_led_send_mode_op_gcr(1, 0, ISSI3733_CR_SSD_NORMAL); // No SYNC due to brightness mismatch with first driver and slight flicker at rgb values 1,2
-
- i2c_led_send_CRWL(0);
- i2c_led_select_page(0, 3);
- i2c_led_send_pur_pdr(0, ISSI3733_SWYR_PUR_8000, ISSI3733_CSXR_PDR_8000);
-
- i2c_led_send_CRWL(1);
- i2c_led_select_page(1, 3);
- i2c_led_send_pur_pdr(1, ISSI3733_SWYR_PUR_8000, ISSI3733_CSXR_PDR_8000);
-
- DBGC(DC_I2C3733_INIT_DRIVERS_COMPLETE);
-
- return 1;
-}
-
-void I2C_DMAC_LED_Init(void) {
- Dmac *dmac = DMAC;
-
- DBGC(DC_I2C_DMAC_LED_INIT_BEGIN);
-
- // Disable device
- dmac->CTRL.bit.DMAENABLE = 0; // Disable DMAC
- while (dmac->CTRL.bit.DMAENABLE) {
- } // Wait for disabled state in case of ongoing transfers
- dmac->CTRL.bit.SWRST = 1; // Software Reset DMAC
- while (dmac->CTRL.bit.SWRST) {
- } // Wait for software reset to complete
-
- // Configure device
- dmac->BASEADDR.reg = (uint32_t)&dmac_desc; // Set descriptor base address
- dmac->WRBADDR.reg = (uint32_t)&dmac_desc_wb; // Set descriptor write back address
- dmac->CTRL.reg |= 0x0f00; // Handle all priorities (LVL0-3)
-
- // Disable channel
- dmac->Channel[0].CHCTRLA.bit.ENABLE = 0; // Disable the channel
- while (dmac->Channel[0].CHCTRLA.bit.ENABLE) {
- } // Wait for disabled state in case of ongoing transfers
- dmac->Channel[0].CHCTRLA.bit.SWRST = 1; // Software Reset the channel
- while (dmac->Channel[0].CHCTRLA.bit.SWRST) {
- } // Wait for software reset to complete
-
- // Configure channel
- dmac->Channel[0].CHCTRLA.bit.THRESHOLD = 0; // 1BEAT
- dmac->Channel[0].CHCTRLA.bit.BURSTLEN = 0; // SINGLE
- dmac->Channel[0].CHCTRLA.bit.TRIGACT = 2; // BURST
- dmac->Channel[0].CHCTRLA.bit.TRIGSRC = SERCOM1_DMAC_ID_TX; // Trigger source
- dmac->Channel[0].CHCTRLA.bit.RUNSTDBY = 1; // Run in standby
-
- NVIC_EnableIRQ(DMAC_0_IRQn);
- dmac->Channel[0].CHINTENSET.bit.TCMPL = 1;
- dmac->Channel[0].CHINTENSET.bit.TERR = 1;
-
- // Enable device
- dmac->CTRL.bit.DMAENABLE = 1; // Enable DMAC
- while (dmac->CTRL.bit.DMAENABLE == 0) {
- } // Wait for enable state
-
- DBGC(DC_I2C_DMAC_LED_INIT_COMPLETE);
-}
-
-// state = 1 enable
-// state = 0 disable
-void I2C3733_Control_Set(uint8_t state) {
- DBGC(DC_I2C3733_CONTROL_SET_BEGIN);
-
- sr_exp_data.bit.SDB_N = (state == 1 ? 1 : 0);
- SR_EXP_WriteData();
-
- DBGC(DC_I2C3733_CONTROL_SET_COMPLETE);
-}
-
-void i2c_led_desc_defaults(void) {
- dmac_desc.BTCTRL.bit.STEPSIZE = 0; // SRCINC used in favor for auto 1 inc
- dmac_desc.BTCTRL.bit.STEPSEL = 0; // SRCINC used in favor for auto 1 inc
- dmac_desc.BTCTRL.bit.DSTINC = 0; // The Destination Address Increment is disabled
- dmac_desc.BTCTRL.bit.SRCINC = 1; // The Source Address Increment is enabled (Inc by 1)
- dmac_desc.BTCTRL.bit.BEATSIZE = 0; // 8-bit bus transfer
- dmac_desc.BTCTRL.bit.BLOCKACT = 0; // Channel will be disabled if it is the last block transfer in the transaction
- dmac_desc.BTCTRL.bit.EVOSEL = 0; // Event generation disabled
- dmac_desc.BTCTRL.bit.VALID = 1; // Set dmac valid
-}
-
-void i2c_led_prepare_send_dma(uint8_t *data, uint8_t len) {
- i2c_led_desc_defaults();
-
- dmac_desc.BTCNT.reg = len;
- dmac_desc.SRCADDR.reg = (uint32_t)data + len;
- dmac_desc.DSTADDR.reg = (uint32_t)&SERCOM1->I2CM.DATA.reg;
- dmac_desc.DESCADDR.reg = 0;
-}
-
-void i2c_led_begin_dma(uint8_t drvid) {
- DMAC->Channel[0].CHCTRLA.bit.ENABLE = 1; // Enable the channel
-
- SERCOM1->I2CM.ADDR.reg = (dmac_desc.BTCNT.reg << 16) | 0x2000 | issidrv[drvid].addr; // Begin transfer
-}
-
-void i2c_led_send_CRWL_dma(uint8_t drvid) {
- *(dma_sendbuf + 0) = ISSI3733_CMDRWL;
- *(dma_sendbuf + 1) = ISSI3733_CMDRWL_WRITE_ENABLE_ONCE;
- i2c_led_prepare_send_dma(dma_sendbuf, 2);
-
- i2c_led_begin_dma(drvid);
-}
-
-void i2c_led_select_page_dma(uint8_t drvid, uint8_t pageno) {
- *(dma_sendbuf + 0) = ISSI3733_CMDR;
- *(dma_sendbuf + 1) = pageno;
- i2c_led_prepare_send_dma(dma_sendbuf, 2);
-
- i2c_led_begin_dma(drvid);
-}
-
-void i2c_led_send_GCR_dma(uint8_t drvid) {
- *(dma_sendbuf + 0) = ISSI3733_GCCR;
- *(dma_sendbuf + 1) = gcr_actual;
- i2c_led_prepare_send_dma(dma_sendbuf, 2);
-
- i2c_led_begin_dma(drvid);
-}
-
-void i2c_led_send_pwm_dma(uint8_t drvid) {
- // Note: This copies the CURRENT pwm buffer, which may be getting modified
- memcpy(dma_sendbuf, issidrv[drvid].pwm, ISSI3733_PG1_BYTES);
- *dma_sendbuf = 0; // Force start location offset to zero
- i2c_led_prepare_send_dma(dma_sendbuf, ISSI3733_PG1_BYTES);
-
- i2c_led_begin_dma(drvid);
-}
-
-void i2c_led_send_onoff_dma(uint8_t drvid) {
- // Note: This copies the CURRENT onoff buffer, which may be getting modified
- memcpy(dma_sendbuf, issidrv[drvid].onoff, ISSI3733_PG0_BYTES);
- *dma_sendbuf = 0; // Force start location offset to zero
- i2c_led_prepare_send_dma(dma_sendbuf, ISSI3733_PG0_BYTES);
-
- i2c_led_begin_dma(drvid);
-}
-
-void i2c_led_q_init(void) {
- memset(i2c_led_q, 0, I2C_Q_SIZE);
- i2c_led_q_s = 0;
- i2c_led_q_e = 0;
- i2c_led_q_running = 0;
- i2c_led_q_full = 0;
-}
-
-uint8_t i2c_led_q_isempty(void) {
- return i2c_led_q_s == i2c_led_q_e;
-}
-
-uint8_t i2c_led_q_size(void) {
- return (i2c_led_q_e - i2c_led_q_s) % I2C_Q_SIZE;
-}
-
-uint8_t i2c_led_q_available(void) {
- return I2C_Q_SIZE - i2c_led_q_size() - 1; // Never allow end to meet start
-}
-
-void i2c_led_q_add(uint8_t cmd) {
- // WARNING: Always request room before adding commands!
-
- // Assign command
- i2c_led_q[i2c_led_q_e] = cmd;
-
- i2c_led_q_e = (i2c_led_q_e + 1) % I2C_Q_SIZE; // Move end up one or wrap
-}
-
-void i2c_led_q_s_advance(void) {
- i2c_led_q_s = (i2c_led_q_s + 1) % I2C_Q_SIZE; // Move start up one or wrap
-}
-
-// Always request room before adding commands
-// PS: In case the queue somehow gets filled, it will reset if it can not clear up
-// PS: Could only get this to happen through unrealistic timings to overload the I2C bus
-uint8_t i2c_led_q_request_room(uint8_t request_size) {
- if (request_size > i2c_led_q_available()) {
- i2c_led_q_full++;
-
- if (i2c_led_q_full >= 100) // Give the queue a chance to clear up
- {
- DBG_LED_ON;
- I2C_DMAC_LED_Init();
- i2c_led_q_init();
- return 1;
- }
-
- return 0;
- }
-
- i2c_led_q_full = 0;
-
- return 1;
-}
-
-uint8_t i2c_led_q_run(void) {
- if (i2c_led_q_isempty()) {
- i2c_led_q_running = 0;
- return 0;
- }
-
- if (i2c_led_q_running) return 1;
-
- i2c_led_q_running = 1;
-
-# if I2C_LED_USE_DMA != 1
- while (!i2c_led_q_isempty()) {
-# endif
- // run command
- if (i2c_led_q[i2c_led_q_s] == I2C_Q_CRWL) {
- i2c_led_q_s_advance();
- uint8_t drvid = i2c_led_q[i2c_led_q_s];
-# if I2C_LED_USE_DMA == 1
- i2c_led_send_CRWL_dma(drvid);
-# else
- i2c_led_send_CRWL(drvid);
-# endif
- } else if (i2c_led_q[i2c_led_q_s] == I2C_Q_PAGE_SELECT) {
- i2c_led_q_s_advance();
- uint8_t drvid = i2c_led_q[i2c_led_q_s];
- i2c_led_q_s_advance();
- uint8_t page = i2c_led_q[i2c_led_q_s];
-# if I2C_LED_USE_DMA == 1
- i2c_led_select_page_dma(drvid, page);
-# else
- i2c_led_select_page(drvid, page);
-# endif
- } else if (i2c_led_q[i2c_led_q_s] == I2C_Q_PWM) {
- i2c_led_q_s_advance();
- uint8_t drvid = i2c_led_q[i2c_led_q_s];
-# if I2C_LED_USE_DMA == 1
- i2c_led_send_pwm_dma(drvid);
-# else
- i2c_led_send_pwm(drvid);
-# endif
- } else if (i2c_led_q[i2c_led_q_s] == I2C_Q_GCR) {
- i2c_led_q_s_advance();
- uint8_t drvid = i2c_led_q[i2c_led_q_s];
-# if I2C_LED_USE_DMA == 1
- i2c_led_send_GCR_dma(drvid);
-# else
- i2c_led_send_GCR(drvid);
-# endif
- } else if (i2c_led_q[i2c_led_q_s] == I2C_Q_ONOFF) {
- i2c_led_q_s_advance();
- uint8_t drvid = i2c_led_q[i2c_led_q_s];
-# if I2C_LED_USE_DMA == 1
- i2c_led_send_onoff_dma(drvid);
-# else
- i2c_led_send_onoff(drvid);
-# endif
- }
-
- i2c_led_q_s_advance(); // Advance last run command or if the command byte was not serviced
-
-# if I2C_LED_USE_DMA != 1
- }
-
- i2c_led_q_running = 0;
-# endif
-
- return 1;
-}
-
-__attribute__((weak)) void i2c_init(void) {
- static bool is_initialised = false;
- if (!is_initialised) {
- is_initialised = true;
-
- i2c0_init();
- }
-}
-
-i2c_status_t i2c_transmit(uint8_t address, const uint8_t *data, uint16_t length, uint16_t timeout) {
- uint8_t ret = i2c0_transmit(address, (uint8_t *)data, length, timeout);
- SERCOM0->I2CM.CTRLB.bit.CMD = 0x03;
- while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP) {
- DBGC(DC_USB_WRITE2422_BLOCK_SYNC_SYSOP);
- }
- return ret ? I2C_STATUS_SUCCESS : I2C_STATUS_ERROR;
-}
-
-#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE)
diff --git a/tmk_core/protocol/arm_atsam/i2c_master.h b/tmk_core/protocol/arm_atsam/i2c_master.h
deleted file mode 100644
index 5459923de43d..000000000000
--- a/tmk_core/protocol/arm_atsam/i2c_master.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _I2C_MASTER_H_
-#define _I2C_MASTER_H_
-
-#ifndef MD_BOOTLOADER
-
-# include "samd51j18a.h"
-# include "issi3733_driver.h"
-# include "config.h"
-
-extern __attribute__((__aligned__(16))) DmacDescriptor dmac_desc;
-extern __attribute__((__aligned__(16))) DmacDescriptor dmac_desc_wb;
-
-uint8_t I2C3733_Init_Control(void);
-uint8_t I2C3733_Init_Drivers(void);
-void I2C3733_Control_Set(uint8_t state);
-void I2C_DMAC_LED_Init(void);
-
-# define I2C_Q_SIZE 100
-
-# define I2C_Q_NA 100
-# define I2C_Q_CRWL 101
-# define I2C_Q_PAGE_SELECT 102
-# define I2C_Q_PWM 103
-# define I2C_Q_GCR 104
-# define I2C_Q_ONOFF 105
-
-# define I2C_DMA_MAX_SEND 255
-
-extern volatile uint8_t i2c_led_q_running;
-
-# define I2C_LED_Q_PWM(a) \
- { \
- if (i2c_led_q_request_room(7)) { \
- i2c_led_q_add(I2C_Q_CRWL); \
- i2c_led_q_add(a); \
- i2c_led_q_add(I2C_Q_PAGE_SELECT); \
- i2c_led_q_add(a); \
- i2c_led_q_add(ISSI3733_PG_PWM); \
- i2c_led_q_add(I2C_Q_PWM); \
- i2c_led_q_add(a); \
- } \
- }
-
-# define I2C_LED_Q_GCR(a) \
- { \
- if (i2c_led_q_request_room(7)) { \
- i2c_led_q_add(I2C_Q_CRWL); \
- i2c_led_q_add(a); \
- i2c_led_q_add(I2C_Q_PAGE_SELECT); \
- i2c_led_q_add(a); \
- i2c_led_q_add(ISSI3733_PG_FN); \
- i2c_led_q_add(I2C_Q_GCR); \
- i2c_led_q_add(a); \
- } \
- }
-
-# define I2C_LED_Q_ONOFF(a) \
- { \
- if (i2c_led_q_request_room(7)) { \
- i2c_led_q_add(I2C_Q_CRWL); \
- i2c_led_q_add(a); \
- i2c_led_q_add(I2C_Q_PAGE_SELECT); \
- i2c_led_q_add(a); \
- i2c_led_q_add(ISSI3733_PG_ONOFF); \
- i2c_led_q_add(I2C_Q_ONOFF); \
- i2c_led_q_add(a); \
- } \
- }
-
-void i2c_led_q_init(void);
-void i2c_led_q_add(uint8_t cmd);
-void i2c_led_q_s_advance(void);
-uint8_t i2c_led_q_size(void);
-uint8_t i2c_led_q_request_room(uint8_t request_size);
-uint8_t i2c_led_q_run(void);
-
-void i2c1_init(void);
-uint8_t i2c1_transmit(uint8_t address, uint8_t *data, uint16_t length, uint16_t timeout);
-void i2c1_stop(void);
-
-#endif // MD_BOOTLOADER
-
-void i2c0_init(void);
-uint8_t i2c0_transmit(uint8_t address, uint8_t *data, uint16_t length, uint16_t timeout);
-void i2c0_stop(void);
-
-// Terrible interface compatiblity...
-#define I2C_STATUS_SUCCESS (0)
-#define I2C_STATUS_ERROR (-1)
-
-typedef int16_t i2c_status_t;
-
-void i2c_init(void);
-i2c_status_t i2c_transmit(uint8_t address, const uint8_t *data, uint16_t length, uint16_t timeout);
-
-#endif // _I2C_MASTER_H_
diff --git a/tmk_core/protocol/arm_atsam/issi3733_driver.h b/tmk_core/protocol/arm_atsam/issi3733_driver.h
deleted file mode 100644
index c01f147e13dd..000000000000
--- a/tmk_core/protocol/arm_atsam/issi3733_driver.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _ISSI3733_DRIVER_H_
-#define _ISSI3733_DRIVER_H_
-
-// ISII3733 Registers
-
-#define ISSI3733_CMDR 0xFD // Command Register (Write Only)
-
-#define ISSI3733_CMDRWL 0xFE // Command Register Write Lock (Read/Write)
-#define ISSI3733_CMDRWL_WRITE_DISABLE 0x00 // Lock register
-#define ISSI3733_CMDRWL_WRITE_ENABLE_ONCE 0xC5 // Enable one write to register then reset to locked
-
-#define ISSI3733_IMR 0xF0 // Interrupt Mask Register (Write Only)
-#define ISSI3733_IMR_IAC_ON 0x08 // Auto Clear Interrupt Bit - Interrupt auto clear when INTB stay low exceeds 8ms
-#define ISSI3733_IMR_IAB_ON 0x04 // Auto Breath Interrupt Bit - Enable auto breath loop finish interrupt
-#define ISSI3733_IMR_IS_ON 0x02 // Dot Short Interrupt Bit - Enable dot short interrupt
-#define ISSI3733_IMR_IO_ON 0x01 // Dot Open Interrupt Bit - Enable dot open interrupt
-
-#define ISSI3733_ISR 0xF1 // Interrupt Status Register (Read Only)
-#define ISSI3733_ISR_ABM3_FINISH 0x10 // Auto Breath Mode 3 Finish Bit - ABM3 finished
-#define ISSI3733_ISR_ABM2_FINISH 0x08 // Auto Breath Mode 2 Finish Bit - ABM2 finished
-#define ISSI3733_ISR_ABM1_FINISH 0x04 // Auto Breath Mode 1 Finish Bit - ABM1 finished
-#define ISSI3733_ISR_SB 0x02 // Short Bit - Shorted
-#define ISSI3733_ISR_OB 0x01 // Open Bit - Opened
-
-#define ISSI3733_PG0 0x00 // LED Control Register
-#define ISSI3733_PG1 0x01 // PWM Register
-#define ISSI3733_PG2 0x02 // Auto Breath Mode Register
-#define ISSI3733_PG3 0x03 // Function Register
-
-#define ISSI3733_PG_ONOFF ISSI3733_PG0
-#define ISSI3733_PG_OR ISSI3733_PG0
-#define ISSI3733_PG_SR ISSI3733_PG0
-#define ISSI3733_PG_PWM ISSI3733_PG1
-#define ISSI3733_PG_ABM ISSI3733_PG2
-#define ISSI3733_PG_FN ISSI3733_PG3
-
-#define ISSI3733_CR 0x00 // Configuration Register
-
-// PG3: Configuration Register: Synchronize Configuration
-#define ISSI3733_CR_SYNC_MASTER 0x40 // Master
-#define ISSI3733_CR_SYNC_SLAVE 0x80 // Slave
-#define ISSI3733_CR_SYNC_HIGH_IMP 0xC0 // High Impedance
-
-// PG3: Configuration Register: Open/Short Detection Enable Bit
-//#define ISSI3733_CR_OSD_DISABLE 0x00 //Disable open/short detection
-#define ISSI3733_CR_OSD_ENABLE 0x04 // Enable open/short detection
-
-// PG3: Configuration Register: Auto Breath Enable
-//#define ISSI3733_CR_B_EN_PWM 0x00 //PWM Mode Enable
-#define ISSI3733_CR_B_EN_AUTO 0x02 // Auto Breath Mode Enable
-
-// PG3: Configuration Register: Software Shutdown Control
-//#define ISSI3733_CR_SSD_SHUTDOWN 0x00 //Software shutdown
-#define ISSI3733_CR_SSD_NORMAL 0x01 // Normal operation
-
-#define ISSI3733_GCCR 0x01 // Global Current Control Register
-
-// 1 Byte, Iout = (GCC / 256) * (840 / Rext)
-// TODO: Give user define for Rext
-
-// PG3: Auto Breath Control Register 1
-#define ISSI3733_ABCR1_ABM1 0x02 // Auto Breath Control Register 1 of ABM-1
-#define ISSI3733_ABCR1_ABM2 0x06 // Auto Breath Control Register 1 of ABM-2
-#define ISSI3733_ABCR1_ABM3 0x0A // Auto Breath Control Register 1 of ABM-3
-
-// Rise time
-#define ISSI3733_ABCR1_T1_0021 0x00 // 0.21s
-#define ISSI3733_ABCR1_T1_0042 0x20 // 0.42s
-#define ISSI3733_ABCR1_T1_0084 0x40 // 0.84s
-#define ISSI3733_ABCR1_T1_0168 0x60 // 1.68s
-#define ISSI3733_ABCR1_T1_0336 0x80 // 3.36s
-#define ISSI3733_ABCR1_T1_0672 0xA0 // 6.72s
-#define ISSI3733_ABCR1_T1_1344 0xC0 // 13.44s
-#define ISSI3733_ABCR1_T1_2688 0xE0 // 26.88s
-
-// Max value time
-#define ISSI3733_ABCR1_T2_0000 0x00 // 0s
-#define ISSI3733_ABCR1_T2_0021 0x02 // 0.21s
-#define ISSI3733_ABCR1_T2_0042 0x04 // 0.42s
-#define ISSI3733_ABCR1_T2_0084 0x06 // 0.84s
-#define ISSI3733_ABCR1_T2_0168 0x08 // 1.68s
-#define ISSI3733_ABCR1_T2_0336 0x0A // 3.36s
-#define ISSI3733_ABCR1_T2_0672 0x0C // 6.72s
-#define ISSI3733_ABCR1_T2_1344 0x0E // 13.44s
-#define ISSI3733_ABCR1_T2_2688 0x10 // 26.88s
-
-// PG3: Auto Breath Control Register 2
-#define ISSI3733_ABCR2_ABM1 0x03 // Auto Breath Control Register 2 of ABM-1
-#define ISSI3733_ABCR2_ABM2 0x07 // Auto Breath Control Register 2 of ABM-2
-#define ISSI3733_ABCR2_ABM3 0x0B // Auto Breath Control Register 2 of ABM-3
-
-// Fall time
-#define ISSI3733_ABCR2_T3_0021 0x00 // 0.21s
-#define ISSI3733_ABCR2_T3_0042 0x20 // 0.42s
-#define ISSI3733_ABCR2_T3_0084 0x40 // 0.84s
-#define ISSI3733_ABCR2_T3_0168 0x60 // 1.68s
-#define ISSI3733_ABCR2_T3_0336 0x80 // 3.36s
-#define ISSI3733_ABCR2_T3_0672 0xA0 // 6.72s
-#define ISSI3733_ABCR2_T3_1344 0xC0 // 13.44s
-#define ISSI3733_ABCR2_T3_2688 0xE0 // 26.88s
-
-// Min value time
-#define ISSI3733_ABCR2_T4_0000 0x00 // 0s
-#define ISSI3733_ABCR2_T4_0021 0x02 // 0.21s
-#define ISSI3733_ABCR2_T4_0042 0x04 // 0.42s
-#define ISSI3733_ABCR2_T4_0084 0x06 // 0.84s
-#define ISSI3733_ABCR2_T4_0168 0x08 // 1.68s
-#define ISSI3733_ABCR2_T4_0336 0x0A // 3.36s
-#define ISSI3733_ABCR2_T4_0672 0x0C // 6.72s
-#define ISSI3733_ABCR2_T4_1344 0x0E // 13.44s
-#define ISSI3733_ABCR2_T4_2688 0x10 // 26.88s
-#define ISSI3733_ABCR2_T4_5376 0x12 // 53.76s
-#define ISSI3733_ABCR2_T4_10752 0x14 // 107.52s
-
-// PG3: Auto Breath Control Register 3
-#define ISSI3733_ABCR3_ABM1 0x04 // Auto Breath Control Register 3 of ABM-1
-#define ISSI3733_ABCR3_ABM2 0x08 // Auto Breath Control Register 3 of ABM-2
-#define ISSI3733_ABCR3_ABM3 0x0C // Auto Breath Control Register 3 of ABM-3
-
-#define ISSI3733_ABCR3_LTA_LOOP_ENDLESS 0x00
-#define ISSI3733_ABCR3_LTA_LOOP_1 0x01
-#define ISSI3733_ABCR3_LTA_LOOP_2 0x02
-#define ISSI3733_ABCR3_LTA_LOOP_3 0x03
-#define ISSI3733_ABCR3_LTA_LOOP_4 0x04
-#define ISSI3733_ABCR3_LTA_LOOP_5 0x05
-#define ISSI3733_ABCR3_LTA_LOOP_6 0x06
-#define ISSI3733_ABCR3_LTA_LOOP_7 0x07
-#define ISSI3733_ABCR3_LTA_LOOP_8 0x08
-#define ISSI3733_ABCR3_LTA_LOOP_9 0x09
-#define ISSI3733_ABCR3_LTA_LOOP_10 0x0A
-#define ISSI3733_ABCR3_LTA_LOOP_11 0x0B
-#define ISSI3733_ABCR3_LTA_LOOP_12 0x0C
-#define ISSI3733_ABCR3_LTA_LOOP_13 0x0D
-#define ISSI3733_ABCR3_LTA_LOOP_14 0x0E
-#define ISSI3733_ABCR3_LTA_LOOP_15 0x0F
-
-// Loop Begin
-#define ISSI3733_ABCR3_LB_T1 0x00
-#define ISSI3733_ABCR3_LB_T2 0x10
-#define ISSI3733_ABCR3_LB_T3 0x20
-#define ISSI3733_ABCR3_LB_T4 0x30
-
-// Loop End
-#define ISSI3733_ABCR3_LE_T3 0x00 // End at Off state
-#define ISSI3733_ABCR3_LE_T1 0x40 // End at On State
-
-// PG3: Auto Breath Control Register 4
-#define ISSI3733_ABCR4_ABM1 0x05 // Auto Breath Control Register 4 of ABM-1
-#define ISSI3733_ABCR4_ABM2 0x09 // Auto Breath Control Register 4 of ABM-2
-#define ISSI3733_ABCR4_ABM3 0x0D // Auto Breath Control Register 4 of ABM-3
-
-#define ISSI3733_ABCR4_LTB_LOOP_ENDLESS 0x00
-// Or 8bit loop times
-
-// PG3: Time Update Register
-#define ISSI3733_TUR 0x0E
-#define ISSI3733_TUR_UPDATE 0x00 // Write to update 02h~0Dh time registers after configuring
-
-// PG3: SWy Pull-Up Resistor Selection Register
-#define ISSI3733_SWYR_PUR 0x0F
-#define ISSI3733_SWYR_PUR_NONE 0x00 // No pull-up resistor
-#define ISSI3733_SWYR_PUR_500 0x01 // 0.5k Ohm
-#define ISSI3733_SWYR_PUR_1000 0x02 // 1.0k Ohm
-#define ISSI3733_SWYR_PUR_2000 0x03 // 2.0k Ohm
-#define ISSI3733_SWYR_PUR_4000 0x04 // 4.0k Ohm
-#define ISSI3733_SWYR_PUR_8000 0x05 // 8.0k Ohm
-#define ISSI3733_SWYR_PUR_16000 0x06 // 16k Ohm
-#define ISSI3733_SWYR_PUR_32000 0x07 // 32k Ohm
-
-// PG3: CSx Pull-Down Resistor Selection Register
-#define ISSI3733_CSXR_PDR 0x10
-#define ISSI3733_CSXR_PDR_NONE 0x00 // No pull-down resistor
-#define ISSI3733_CSXR_PDR_500 0x01 // 0.5k Ohm
-#define ISSI3733_CSXR_PDR_1000 0x02 // 1.0k Ohm
-#define ISSI3733_CSXR_PDR_2000 0x03 // 2.0k Ohm
-#define ISSI3733_CSXR_PDR_4000 0x04 // 4.0k Ohm
-#define ISSI3733_CSXR_PDR_8000 0x05 // 8.0k Ohm
-#define ISSI3733_CSXR_PDR_16000 0x06 // 16k Ohm
-#define ISSI3733_CSXR_PDR_32000 0x07 // 32k Ohm
-
-// PG3: Reset Register
-#define ISSI3733_RR 0x11 // Read to reset all registers to default values
-
-#endif //_ISSI3733_DRIVER_H_
diff --git a/tmk_core/protocol/arm_atsam/main_arm_atsam.c b/tmk_core/protocol/arm_atsam/main_arm_atsam.c
deleted file mode 100644
index 15592bf9085e..000000000000
--- a/tmk_core/protocol/arm_atsam/main_arm_atsam.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "samd51j18a.h"
-#include "keyboard.h"
-
-#include "report.h"
-#include "host.h"
-#include "host_driver.h"
-#include "suspend.h"
-#include "keycode_config.h"
-#include
-
-// From protocol directory
-#include "arm_atsam_protocol.h"
-
-// From keyboard's directory
-#include "config_led.h"
-
-uint8_t g_usb_state = USB_FSMSTATUS_FSMSTATE_OFF_Val; // Saved USB state from hardware value to detect changes
-
-void main_subtasks(void);
-uint8_t keyboard_leds(void);
-void send_keyboard(report_keyboard_t *report);
-void send_nkro(report_nkro_t *report);
-void send_mouse(report_mouse_t *report);
-void send_extra(report_extra_t *report);
-
-#ifdef DEFERRED_EXEC_ENABLE
-void deferred_exec_task(void);
-#endif // DEFERRED_EXEC_ENABLE
-
-host_driver_t arm_atsam_driver = {keyboard_leds, send_keyboard, send_nkro, send_mouse, send_extra};
-
-uint8_t led_states;
-
-uint8_t keyboard_leds(void) {
-#ifdef NKRO_ENABLE
- if (keymap_config.nkro)
- return udi_hid_nkro_report_set;
- else
-#endif // NKRO_ENABLE
- return udi_hid_kbd_report_set;
-}
-
-void send_keyboard(report_keyboard_t *report) {
- uint32_t irqflags;
-
- while (udi_hid_kbd_b_report_trans_ongoing) {
- main_subtasks();
- } // Run other tasks while waiting for USB to be free
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
-
- memcpy(udi_hid_kbd_report, report, UDI_HID_KBD_REPORT_SIZE);
- udi_hid_kbd_b_report_valid = 1;
- udi_hid_kbd_send_report();
-
- __DMB();
- __set_PRIMASK(irqflags);
-}
-
-void send_nkro(report_nkro_t *report) {
-#ifdef NKRO_ENABLE
- uint32_t irqflags;
-
- while (udi_hid_nkro_b_report_trans_ongoing) {
- main_subtasks();
- } // Run other tasks while waiting for USB to be free
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
-
- /*
- Skipping ahead `sizeof(report->report_id)` bytes
- since `report_id` is not used by this driver
- */
- void *report_no_report_id = (void *)((char *)report + sizeof(report->report_id));
-
- memcpy(udi_hid_nkro_report, report_no_report_id, UDI_HID_NKRO_REPORT_SIZE);
- udi_hid_nkro_b_report_valid = 1;
- udi_hid_nkro_send_report();
-
- __DMB();
- __set_PRIMASK(irqflags);
-#endif
-}
-
-void send_mouse(report_mouse_t *report) {
-#ifdef MOUSEKEY_ENABLE
- uint32_t irqflags;
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
-
-# ifdef MOUSE_SHARED_EP
- /*
- Skipping ahead `sizeof(report->report_id)` bytes
- since `report_id` is not used by this driver
- */
- void *report_no_report_id = (void *)((char *)report + sizeof(report->report_id));
-
- memcpy(udi_hid_mou_report, report_no_report_id, UDI_HID_MOU_REPORT_SIZE);
-# else
- memcpy(udi_hid_mou_report, report, UDI_HID_MOU_REPORT_SIZE);
-# endif
- udi_hid_mou_b_report_valid = 1;
- udi_hid_mou_send_report();
-
- __DMB();
- __set_PRIMASK(irqflags);
-#endif // MOUSEKEY_ENABLE
-}
-
-void send_extra(report_extra_t *report) {
-#ifdef EXTRAKEY_ENABLE
- uint32_t irqflags;
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
-
- memcpy(udi_hid_exk_report, report, UDI_HID_EXK_REPORT_SIZE);
- udi_hid_exk_b_report_valid = 1;
- udi_hid_exk_send_report();
-
- __DMB();
- __set_PRIMASK(irqflags);
-#endif // EXTRAKEY_ENABLE
-}
-
-#ifdef CONSOLE_ENABLE
-# define CONSOLE_PRINTBUF_SIZE 512
-static char console_printbuf[CONSOLE_PRINTBUF_SIZE];
-static uint16_t console_printbuf_len = 0;
-
-int8_t sendchar(uint8_t c) {
- if (console_printbuf_len >= CONSOLE_PRINTBUF_SIZE) return -1;
-
- console_printbuf[console_printbuf_len++] = c;
- return 0;
-}
-
-void main_subtask_console_flush(void) {
- while (udi_hid_con_b_report_trans_ongoing) {
- } // Wait for any previous transfers to complete
-
- uint16_t result = console_printbuf_len;
- uint32_t irqflags;
- char * pconbuf = console_printbuf; // Pointer to start send from
- int send_out = CONSOLE_EPSIZE; // Bytes to send per transfer
-
- while (result > 0) { // While not error and bytes remain
- while (udi_hid_con_b_report_trans_ongoing) {
- } // Wait for any previous transfers to complete
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
-
- if (result < CONSOLE_EPSIZE) { // If remaining bytes are less than console epsize
- memset(udi_hid_con_report, 0, CONSOLE_EPSIZE); // Clear the buffer
- send_out = result; // Send remaining size
- }
-
- memcpy(udi_hid_con_report, pconbuf, send_out); // Copy data into the send buffer
-
- udi_hid_con_b_report_valid = 1; // Set report valid
- udi_hid_con_send_report(); // Send report
-
- __DMB();
- __set_PRIMASK(irqflags);
-
- result -= send_out; // Decrement result by bytes sent
- pconbuf += send_out; // Increment buffer point by bytes sent
- }
-
- console_printbuf_len = 0;
-}
-
-#endif // CONSOLE_ENABLE
-
-void main_subtask_usb_state(void) {
- static uint64_t fsmstate_on_delay = 0; // Delay timer to be sure USB is actually operating before bringing up hardware
- uint8_t fsmstate_now = USB->DEVICE.FSMSTATUS.reg; // Current state from hardware register
-
- if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) // If USB SUSPENDED
- {
- fsmstate_on_delay = 0; // Clear ON delay timer
-
- if (g_usb_state != USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) // If previously not SUSPENDED
- {
- suspend_power_down(); // Run suspend routine
- g_usb_state = fsmstate_now; // Save current USB state
- }
- } else if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SLEEP_Val) // Else if USB SLEEPING
- {
- fsmstate_on_delay = 0; // Clear ON delay timer
-
- if (g_usb_state != USB_FSMSTATUS_FSMSTATE_SLEEP_Val) // If previously not SLEEPING
- {
- suspend_power_down(); // Run suspend routine
- g_usb_state = fsmstate_now; // Save current USB state
- }
- } else if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_ON_Val) // Else if USB ON
- {
- if (g_usb_state != USB_FSMSTATUS_FSMSTATE_ON_Val) // If previously not ON
- {
- if (fsmstate_on_delay == 0) // If ON delay timer is cleared
- {
- fsmstate_on_delay = timer_read64() + 250; // Set ON delay timer
- } else if (timer_read64() > fsmstate_on_delay) // Else if ON delay timer is active and timed out
- {
- suspend_wakeup_init(); // Run wakeup routine
- g_usb_state = fsmstate_now; // Save current USB state
- }
- }
- } else // Else if USB is in a state not being tracked
- {
- fsmstate_on_delay = 0; // Clear ON delay timer
- }
-}
-
-void main_subtask_power_check(void) {
- static uint64_t next_5v_checkup = 0;
-
- if (timer_read64() > next_5v_checkup) {
- next_5v_checkup = timer_read64() + 5;
-
- v_5v = adc_get(ADC_5V);
- v_5v_avg = 0.9 * v_5v_avg + 0.1 * v_5v;
-
-#ifdef RGB_MATRIX_ENABLE
- gcr_compute();
-#endif
- }
-}
-
-void main_subtask_usb_extra_device(void) {
- static uint64_t next_usb_checkup = 0;
-
- if (timer_read64() > next_usb_checkup) {
- next_usb_checkup = timer_read64() + 10;
-
- USB_HandleExtraDevice();
- }
-}
-
-#ifdef RAW_ENABLE
-void main_subtask_raw(void) {
- udi_hid_raw_receive_report();
-}
-#endif
-
-void main_subtasks(void) {
- main_subtask_usb_state();
- main_subtask_power_check();
- main_subtask_usb_extra_device();
-#ifdef CONSOLE_ENABLE
- main_subtask_console_flush();
-#endif
-#ifdef RAW_ENABLE
- main_subtask_raw();
-#endif
-}
-
-int main(void) {
- DBG_LED_ENA;
- DBG_1_ENA;
- DBG_1_OFF;
- DBG_2_ENA;
- DBG_2_OFF;
- DBG_3_ENA;
- DBG_3_OFF;
-
- debug_code_init();
-
- CLK_init();
-
- ADC0_init();
-
- SR_EXP_Init();
-
-#ifdef RGB_MATRIX_ENABLE
- i2c1_init();
-#endif // RGB_MATRIX_ENABLE
-
- USB_Hub_init();
-
- DBGC(DC_MAIN_UDC_START_BEGIN);
- udc_start();
- DBGC(DC_MAIN_UDC_START_COMPLETE);
-
- DBGC(DC_MAIN_CDC_INIT_BEGIN);
- CDC_init();
- DBGC(DC_MAIN_CDC_INIT_COMPLETE);
-
- while (USB_Hub_Port_Detect_Init() == 0) {
- }
-
- DBG_LED_OFF;
-
-#ifdef RGB_MATRIX_ENABLE
- while (I2C3733_Init_Control() != 1) {
- }
- while (I2C3733_Init_Drivers() != 1) {
- }
-
- I2C_DMAC_LED_Init();
-
- i2c_led_q_init();
-
- for (uint8_t drvid = 0; drvid < ISSI3733_DRIVER_COUNT; drvid++)
- I2C_LED_Q_ONOFF(drvid); // Queue data
-#endif // RGB_MATRIX_ENABLE
-
- keyboard_setup();
-
- keyboard_init();
-
- host_set_driver(&arm_atsam_driver);
-
-#ifdef CONSOLE_ENABLE
- uint64_t next_print = 0;
-#endif // CONSOLE_ENABLE
-
- v_5v_avg = adc_get(ADC_5V);
-
- debug_code_disable();
-
- while (1) {
- main_subtasks(); // Note these tasks will also be run while waiting for USB keyboard polling intervals
-
- if (g_usb_state == USB_FSMSTATUS_FSMSTATE_SUSPEND_Val || g_usb_state == USB_FSMSTATUS_FSMSTATE_SLEEP_Val) {
- if (suspend_wakeup_condition()) {
- udc_remotewakeup(); // Send remote wakeup signal
- wait_ms(50);
- }
-
- continue;
- }
-
- keyboard_task();
-
-#ifdef CONSOLE_ENABLE
- if (timer_read64() > next_print) {
- next_print = timer_read64() + 250;
- // Add any debug information here that you want to see very often
- // dprintf("5v=%u 5vu=%u dlow=%u dhi=%u gca=%u gcd=%u\r\n", v_5v, v_5v_avg, v_5v_avg - V5_LOW, v_5v_avg - V5_HIGH, gcr_actual, gcr_desired);
- }
-#endif // CONSOLE_ENABLE
-
-#ifdef DEFERRED_EXEC_ENABLE
- // Run deferred executions
- deferred_exec_task();
-#endif // DEFERRED_EXEC_ENABLE
-
- // Run housekeeping
- housekeeping_task();
- }
-
- return 1;
-}
diff --git a/tmk_core/protocol/arm_atsam/main_arm_atsam.h b/tmk_core/protocol/arm_atsam/main_arm_atsam.h
deleted file mode 100644
index 78205e2e1be9..000000000000
--- a/tmk_core/protocol/arm_atsam/main_arm_atsam.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _MAIN_ARM_ATSAM_H_
-#define _MAIN_ARM_ATSAM_H_
-
-uint8_t keyboard_leds(void);
-
-#endif //_MAIN_ARM_ATSAM_H_
diff --git a/tmk_core/protocol/arm_atsam/md_rgb_matrix.c b/tmk_core/protocol/arm_atsam/md_rgb_matrix.c
deleted file mode 100644
index 0f316b256cfc..000000000000
--- a/tmk_core/protocol/arm_atsam/md_rgb_matrix.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#define FLUSH_TIMEOUT 5000
-#define EECONFIG_MD_LED ((uint8_t*)(EECONFIG_SIZE + 64))
-#define MD_LED_CONFIG_VERSION 1
-
-#ifdef RGB_MATRIX_ENABLE
-# include "arm_atsam_protocol.h"
-# include "led.h"
-# include "rgb_matrix.h"
-# include "eeprom.h"
-# include "host.h"
-# include
-# include
-
-# ifdef USE_MASSDROP_CONFIGURATOR
-// TODO?: wire these up to keymap.c
-md_led_config_t md_led_config = {0};
-
-EECONFIG_DEBOUNCE_HELPER(md_led, EECONFIG_MD_LED, md_led_config);
-
-void eeconfig_update_md_led_default(void) {
- md_led_config.ver = MD_LED_CONFIG_VERSION;
-
- gcr_desired = LED_GCR_MAX;
- led_animation_orientation = 0;
- led_animation_direction = 0;
- led_animation_breathing = 0;
- led_animation_id = 0;
- led_animation_speed = 4.0f;
- led_lighting_mode = LED_MODE_NORMAL;
- led_enabled = 1;
- led_animation_breathe_cur = BREATHE_MIN_STEP;
- breathe_dir = 1;
- led_animation_circular = 0;
- led_edge_brightness = 1.0f;
- led_ratio_brightness = 1.0f;
- led_edge_mode = LED_EDGE_MODE_ALL;
-
- eeconfig_flush_md_led(true);
-}
-
-void md_led_changed(void) {
- eeconfig_flag_md_led(true);
-}
-
-// todo: use real task rather than this bodge
-void housekeeping_task_kb(void) {
- eeconfig_flush_md_led_task(FLUSH_TIMEOUT);
-}
-
-__attribute__((weak)) led_instruction_t led_instructions[] = {{.end = 1}};
-static void md_rgb_matrix_config_override(int i);
-# else
-uint8_t gcr_desired;
-# endif // USE_MASSDROP_CONFIGURATOR
-
-void SERCOM1_0_Handler(void) {
- if (SERCOM1->I2CM.INTFLAG.bit.ERROR) {
- SERCOM1->I2CM.INTFLAG.reg = SERCOM_I2CM_INTENCLR_ERROR;
- }
-}
-
-void DMAC_0_Handler(void) {
- if (DMAC->Channel[0].CHINTFLAG.bit.TCMPL) {
- DMAC->Channel[0].CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
-
- i2c1_stop();
-
- i2c_led_q_running = 0;
-
- i2c_led_q_run();
-
- return;
- }
-
- if (DMAC->Channel[0].CHINTFLAG.bit.TERR) {
- DMAC->Channel[0].CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
- }
-}
-
-issi3733_driver_t issidrv[ISSI3733_DRIVER_COUNT];
-
-issi3733_led_t led_map[ISSI3733_LED_COUNT] = ISSI3733_LED_MAP;
-RGB led_buffer[ISSI3733_LED_COUNT];
-
-uint8_t gcr_actual;
-uint8_t gcr_actual_last;
-# ifdef USE_MASSDROP_CONFIGURATOR
-uint8_t gcr_breathe;
-float breathe_mult;
-float pomod;
-# endif
-
-# define ACT_GCR_NONE 0
-# define ACT_GCR_INC 1
-# define ACT_GCR_DEC 2
-
-# define LED_GCR_STEP_AUTO 2
-
-static uint8_t gcr_min_counter;
-static uint8_t v_5v_cat_hit;
-
-// WARNING: Automatic GCR is in place to prevent USB shutdown and LED driver overloading
-void gcr_compute(void) {
- uint8_t action = ACT_GCR_NONE;
- uint8_t gcr_use = gcr_desired;
-
-# ifdef USE_MASSDROP_CONFIGURATOR
- if (led_animation_breathing) {
- gcr_use = gcr_breathe;
- }
-# endif
-
- // If the 5v takes a catastrophic hit, disable the LED drivers briefly, assert auto gcr mode, min gcr and let the auto take over
- if (v_5v < V5_CAT) {
- I2C3733_Control_Set(0);
- // CDC_print("USB: WARNING: 5V catastrophic level reached! Disabling LED drivers!\r\n"); //Blocking print is bad here!
- v_5v_cat_hit = 20; //~100ms recover
- gcr_actual = 0; // Minimize GCR
- usb_gcr_auto = 1; // Force auto mode enabled
- return;
- } else if (v_5v_cat_hit > 1) {
- v_5v_cat_hit--;
- return;
- } else if (v_5v_cat_hit == 1) {
- I2C3733_Control_Set(1);
- CDC_print("USB: WARNING: Re-enabling LED drivers\r\n");
- v_5v_cat_hit = 0;
- return;
- }
-
- if (usb_gcr_auto) {
- if (v_5v_avg < V5_LOW)
- action = ACT_GCR_DEC;
- else if (v_5v_avg > V5_HIGH && gcr_actual < gcr_use)
- action = ACT_GCR_INC;
- else if (gcr_actual > gcr_use)
- action = ACT_GCR_DEC;
- } else {
- if (gcr_actual < gcr_use)
- action = ACT_GCR_INC;
- else if (gcr_actual > gcr_use)
- action = ACT_GCR_DEC;
- }
-
- if (action == ACT_GCR_NONE) {
- gcr_min_counter = 0;
- } else if (action == ACT_GCR_INC) {
- if (LED_GCR_STEP_AUTO > LED_GCR_MAX - gcr_actual)
- gcr_actual = LED_GCR_MAX; // Obey max and prevent wrapping
- else
- gcr_actual += LED_GCR_STEP_AUTO;
- gcr_min_counter = 0;
- } else if (action == ACT_GCR_DEC) {
- if (LED_GCR_STEP_AUTO > gcr_actual) // Prevent wrapping
- {
- gcr_actual = 0;
- // At this point, power can no longer be cut from the LED drivers, so focus on cutting out extra port if active
- if (usb_extra_state != USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG) // If not in a wait for replug state
- {
- if (usb_extra_state == USB_EXTRA_STATE_ENABLED) // If extra usb is enabled
- {
- gcr_min_counter++;
- if (gcr_min_counter > 200) // 5ms per check = 1s delay
- {
- USB_ExtraSetState(USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG);
- usb_extra_manual = 0; // Force disable manual mode of extra port
- if (usb_extra_manual)
- CDC_print("USB: Disabling extra port until replug and manual mode toggle!\r\n");
- else
- CDC_print("USB: Disabling extra port until replug!\r\n");
- }
- }
- }
- } else {
- // Power successfully cut back from LED drivers
- gcr_actual -= LED_GCR_STEP_AUTO;
- gcr_min_counter = 0;
-
-# ifdef USE_MASSDROP_CONFIGURATOR
- // If breathe mode is active, the top end can fluctuate if the host can not supply enough current
- // So set the breathe GCR to where it becomes stable
- if (led_animation_breathing == 1) {
- gcr_breathe = gcr_actual;
- // PS: At this point, setting breathing to exhale makes a noticebly shorter cycle
- // and the same would happen maybe one or two more times. Therefore I'm favoring
- // powering through one full breathe and letting gcr settle completely
- }
-# endif
- }
- }
-}
-
-void issi3733_prepare_arrays(void) {
- static bool s_init = false;
- if (s_init) {
- return;
- }
- s_init = true;
-
- memset(issidrv, 0, sizeof(issi3733_driver_t) * ISSI3733_DRIVER_COUNT);
-
- int i;
- uint8_t addrs[ISSI3733_DRIVER_COUNT] = ISSI3773_DRIVER_ADDRESSES;
-
- for (i = 0; i < ISSI3733_DRIVER_COUNT; i++) {
- issidrv[i].addr = addrs[i];
- }
-
- for (uint8_t i = 0; i < ISSI3733_LED_COUNT; i++) {
- // BYTE: 1 + (SW-1)*16 + (CS-1)
- led_map[i].rgb.g = issidrv[led_map[i].adr.drv - 1].pwm + 1 + ((led_map[i].adr.swg - 1) * 16 + (led_map[i].adr.cs - 1));
- led_map[i].rgb.r = issidrv[led_map[i].adr.drv - 1].pwm + 1 + ((led_map[i].adr.swr - 1) * 16 + (led_map[i].adr.cs - 1));
- led_map[i].rgb.b = issidrv[led_map[i].adr.drv - 1].pwm + 1 + ((led_map[i].adr.swb - 1) * 16 + (led_map[i].adr.cs - 1));
-
- // BYTE: 1 + (SW-1)*2 + (CS-1)/8
- // BIT: (CS-1)%8
- *(issidrv[led_map[i].adr.drv - 1].onoff + 1 + (led_map[i].adr.swg - 1) * 2 + (led_map[i].adr.cs - 1) / 8) |= (1 << ((led_map[i].adr.cs - 1) % 8));
- *(issidrv[led_map[i].adr.drv - 1].onoff + 1 + (led_map[i].adr.swr - 1) * 2 + (led_map[i].adr.cs - 1) / 8) |= (1 << ((led_map[i].adr.cs - 1) % 8));
- *(issidrv[led_map[i].adr.drv - 1].onoff + 1 + (led_map[i].adr.swb - 1) * 2 + (led_map[i].adr.cs - 1) / 8) |= (1 << ((led_map[i].adr.cs - 1) % 8));
- }
-}
-
-void md_rgb_matrix_prepare(void) {
- for (uint8_t i = 0; i < ISSI3733_LED_COUNT; i++) {
- *led_map[i].rgb.r = 0;
- *led_map[i].rgb.g = 0;
- *led_map[i].rgb.b = 0;
- }
-}
-
-static void led_set_one(int i, uint8_t r, uint8_t g, uint8_t b) {
- if (i < ISSI3733_LED_COUNT) {
-# ifdef USE_MASSDROP_CONFIGURATOR
- md_rgb_matrix_config_override(i);
-# else
- led_buffer[i].r = r;
- led_buffer[i].g = g;
- led_buffer[i].b = b;
-# endif
- }
-}
-
-static void led_set_all(uint8_t r, uint8_t g, uint8_t b) {
- for (uint8_t i = 0; i < ISSI3733_LED_COUNT; i++) {
- led_set_one(i, r, g, b);
- }
-}
-
-static void init(void) {
- DBGC(DC_LED_MATRIX_INIT_BEGIN);
-
-# ifdef USE_MASSDROP_CONFIGURATOR
- eeconfig_init_md_led();
- if (md_led_config.ver != MD_LED_CONFIG_VERSION) {
- eeconfig_update_md_led_default();
- }
-# endif
-
- issi3733_prepare_arrays();
-
- md_rgb_matrix_prepare();
-
- gcr_min_counter = 0;
- v_5v_cat_hit = 0;
-
- DBGC(DC_LED_MATRIX_INIT_COMPLETE);
-}
-
-static void flush(void) {
-# ifdef USE_MASSDROP_CONFIGURATOR
- if (!led_enabled) {
- return;
- } // Prevent calculations and I2C traffic if LED drivers are not enabled
-# else
- if (!sr_exp_data.bit.SDB_N) {
- return;
- } // Prevent calculations and I2C traffic if LED drivers are not enabled
-# endif
-
- // Wait for previous transfer to complete
- while (i2c_led_q_running) {
- }
-
- // Copy buffer to live DMA region
- for (uint8_t i = 0; i < ISSI3733_LED_COUNT; i++) {
- *led_map[i].rgb.r = led_buffer[i].r;
- *led_map[i].rgb.g = led_buffer[i].g;
- *led_map[i].rgb.b = led_buffer[i].b;
- }
-
-# ifdef USE_MASSDROP_CONFIGURATOR
- breathe_mult = 1;
-
- if (led_animation_breathing) {
- //+60us 119 LED
- led_animation_breathe_cur += BREATHE_STEP * breathe_dir;
-
- if (led_animation_breathe_cur >= BREATHE_MAX_STEP)
- breathe_dir = -1;
- else if (led_animation_breathe_cur <= BREATHE_MIN_STEP)
- breathe_dir = 1;
-
- // Brightness curve created for 256 steps, 0 - ~98%
- breathe_mult = 0.000015 * led_animation_breathe_cur * led_animation_breathe_cur;
- if (breathe_mult > 1)
- breathe_mult = 1;
- else if (breathe_mult < 0)
- breathe_mult = 0;
- }
-
- // This should only be performed once per frame
- pomod = (float)((g_rgb_timer / 10) % (uint32_t)(1000.0f / led_animation_speed)) / 10.0f * led_animation_speed;
- pomod *= 100.0f;
- pomod = (uint32_t)pomod % 10000;
- pomod /= 100.0f;
-
-# endif // USE_MASSDROP_CONFIGURATOR
-
- uint8_t drvid;
-
- // NOTE: GCR does not need to be timed with LED processing, but there is really no harm
- if (gcr_actual != gcr_actual_last) {
- for (drvid = 0; drvid < ISSI3733_DRIVER_COUNT; drvid++)
- I2C_LED_Q_GCR(drvid); // Queue data
- gcr_actual_last = gcr_actual;
- }
-
- for (drvid = 0; drvid < ISSI3733_DRIVER_COUNT; drvid++)
- I2C_LED_Q_PWM(drvid); // Queue data
-
- i2c_led_q_run();
-}
-
-void md_rgb_matrix_indicators_advanced(uint8_t led_min, uint8_t led_max) {
- led_t led_state = host_keyboard_led_state();
- if (led_state.raw && rgb_matrix_config.enable) {
- for (uint8_t i = led_min; i < led_max; i++) {
- if (
-# if USB_LED_NUM_LOCK_SCANCODE != 255
- (led_map[i].scan == USB_LED_NUM_LOCK_SCANCODE && led_state.num_lock) ||
-# endif // NUM LOCK
-# if USB_LED_CAPS_LOCK_SCANCODE != 255
- (led_map[i].scan == USB_LED_CAPS_LOCK_SCANCODE && led_state.caps_lock) ||
-# endif // CAPS LOCK
-# if USB_LED_SCROLL_LOCK_SCANCODE != 255
- (led_map[i].scan == USB_LED_SCROLL_LOCK_SCANCODE && led_state.scroll_lock) ||
-# endif // SCROLL LOCK
-# if USB_LED_COMPOSE_SCANCODE != 255
- (led_map[i].scan == USB_LED_COMPOSE_SCANCODE && led_state.compose) ||
-# endif // COMPOSE
-# if USB_LED_KANA_SCANCODE != 255
- (led_map[i].scan == USB_LED_KANA_SCANCODE && led_state.kana) ||
-# endif // KANA
- (0)) {
- if (rgb_matrix_get_flags() & LED_FLAG_INDICATOR) {
- led_buffer[i].r = 255 - led_buffer[i].r;
- led_buffer[i].g = 255 - led_buffer[i].g;
- led_buffer[i].b = 255 - led_buffer[i].b;
- }
- }
- }
- }
-}
-
-const rgb_matrix_driver_t rgb_matrix_driver = {.init = init, .flush = flush, .set_color = led_set_one, .set_color_all = led_set_all};
-
-/*==============================================================================
-= Legacy Lighting Support =
-==============================================================================*/
-
-# ifdef USE_MASSDROP_CONFIGURATOR
-// Ported from Massdrop QMK GitHub Repo
-
-static void led_run_pattern(led_setup_t* f, float* ro, float* go, float* bo, float pos) {
- float po;
-
- while (f->end != 1) {
- po = pos; // Reset po for new frame
-
- // Add in any moving effects
- if ((!led_animation_direction && f->ef & EF_SCR_R) || (led_animation_direction && (f->ef & EF_SCR_L))) {
- po -= pomod;
-
- if (po > 100)
- po -= 100;
- else if (po < 0)
- po += 100;
- } else if ((!led_animation_direction && f->ef & EF_SCR_L) || (led_animation_direction && (f->ef & EF_SCR_R))) {
- po += pomod;
-
- if (po > 100)
- po -= 100;
- else if (po < 0)
- po += 100;
- }
-
- // Check if LED's po is in current frame
- if (po < f->hs) {
- f++;
- continue;
- }
- if (po > f->he) {
- f++;
- continue;
- }
- // note: < 0 or > 100 continue
-
- // Calculate the po within the start-stop percentage for color blending
- po = (po - f->hs) / (f->he - f->hs);
-
- // Add in any color effects
- if (f->ef & EF_OVER) {
- *ro = (po * (f->re - f->rs)) + f->rs; // + 0.5;
- *go = (po * (f->ge - f->gs)) + f->gs; // + 0.5;
- *bo = (po * (f->be - f->bs)) + f->bs; // + 0.5;
- } else if (f->ef & EF_SUBTRACT) {
- *ro -= (po * (f->re - f->rs)) + f->rs; // + 0.5;
- *go -= (po * (f->ge - f->gs)) + f->gs; // + 0.5;
- *bo -= (po * (f->be - f->bs)) + f->bs; // + 0.5;
- } else {
- *ro += (po * (f->re - f->rs)) + f->rs; // + 0.5;
- *go += (po * (f->ge - f->gs)) + f->gs; // + 0.5;
- *bo += (po * (f->be - f->bs)) + f->bs; // + 0.5;
- }
-
- f++;
- }
-}
-
-# define RGB_MAX_DISTANCE 232.9635f
-
-static void md_rgb_matrix_config_override(int i) {
- float ro = 0;
- float go = 0;
- float bo = 0;
- float po;
-
- uint8_t highest_active_layer = get_highest_layer(layer_state);
-
- if (led_animation_circular) {
- // TODO: should use min/max values from LED configuration instead of
- // hard-coded 224, 64
- // po = sqrtf((powf(fabsf((disp.width / 2) - (led_cur->x - disp.left)), 2) + powf(fabsf((disp.height / 2) - (led_cur->y - disp.bottom)), 2))) / disp.max_distance * 100;
- po = sqrtf((powf(fabsf((224 / 2) - (float)g_led_config.point[i].x), 2) + powf(fabsf((64 / 2) - (float)g_led_config.point[i].y), 2))) / RGB_MAX_DISTANCE * 100;
- } else {
- if (led_animation_orientation) {
- po = (float)g_led_config.point[i].y / 64.f * 100;
- } else {
- po = (float)g_led_config.point[i].x / 224.f * 100;
- }
- }
-
- if (led_edge_mode == LED_EDGE_MODE_ALTERNATE && LED_IS_EDGE_ALT(led_map[i].scan)) {
- // Do not act on this LED (Edge alternate lighting mode)
- } else if (led_lighting_mode == LED_MODE_KEYS_ONLY && HAS_FLAGS(g_led_config.flags[i], LED_FLAG_UNDERGLOW)) {
- // Do not act on this LED
- } else if (led_lighting_mode == LED_MODE_NON_KEYS_ONLY && !HAS_FLAGS(g_led_config.flags[i], LED_FLAG_UNDERGLOW)) {
- // Do not act on this LED
- } else if (led_lighting_mode == LED_MODE_INDICATORS_ONLY) {
- // Do not act on this LED (Only show indicators)
- } else {
- led_instruction_t* led_cur_instruction = led_instructions;
- while (!led_cur_instruction->end) {
- // Check if this applies to current layer
- if ((led_cur_instruction->flags & LED_FLAG_MATCH_LAYER) && (led_cur_instruction->layer != highest_active_layer)) {
- goto next_iter;
- }
-
- // Check if this applies to current index
- if (led_cur_instruction->flags & LED_FLAG_MATCH_ID) {
- uint8_t modid = i / 32; // Calculate which id# contains the led bit
- uint32_t modidbit = 1 << (i % 32); // Calculate the bit within the id#
- uint32_t* bitfield = &led_cur_instruction->id0 + modid; // Add modid as offset to id0 address. *bitfield is now idX of the led id
- if (~(*bitfield) & modidbit) { // Check if led bit is not set in idX
- goto next_iter;
- }
- }
-
- if (led_cur_instruction->flags & LED_FLAG_USE_RGB) {
- ro = led_cur_instruction->r;
- go = led_cur_instruction->g;
- bo = led_cur_instruction->b;
- } else if (led_cur_instruction->flags & LED_FLAG_USE_PATTERN) {
- led_run_pattern(led_setups[led_cur_instruction->pattern_id], &ro, &go, &bo, po);
- } else if (led_cur_instruction->flags & LED_FLAG_USE_ROTATE_PATTERN) {
- led_run_pattern(led_setups[led_animation_id], &ro, &go, &bo, po);
- }
-
- next_iter:
- led_cur_instruction++;
- }
-
- if (ro > 255)
- ro = 255;
- else if (ro < 0)
- ro = 0;
- if (go > 255)
- go = 255;
- else if (go < 0)
- go = 0;
- if (bo > 255)
- bo = 255;
- else if (bo < 0)
- bo = 0;
-
- if (led_animation_breathing) {
- ro *= breathe_mult;
- go *= breathe_mult;
- bo *= breathe_mult;
- }
- }
-
- // Adjust edge LED brightness
- if (led_edge_brightness != 1 && LED_IS_EDGE(led_map[i].scan)) {
- ro *= led_edge_brightness;
- go *= led_edge_brightness;
- bo *= led_edge_brightness;
- }
-
- // Adjust ratio of key vs. underglow (edge) LED brightness
- if (LED_IS_EDGE(led_map[i].scan) && led_ratio_brightness > 1.0) {
- // Decrease edge (underglow) LEDs
- ro *= (2.0 - led_ratio_brightness);
- go *= (2.0 - led_ratio_brightness);
- bo *= (2.0 - led_ratio_brightness);
- } else if (LED_IS_KEY(led_map[i].scan) && led_ratio_brightness < 1.0) {
- // Decrease KEY LEDs
- ro *= led_ratio_brightness;
- go *= led_ratio_brightness;
- bo *= led_ratio_brightness;
- }
-
- led_buffer[i].r = (uint8_t)ro;
- led_buffer[i].g = (uint8_t)go;
- led_buffer[i].b = (uint8_t)bo;
-}
-
-# endif // USE_MASSDROP_CONFIGURATOR
-#endif // RGB_MATRIX_ENABLE
diff --git a/tmk_core/protocol/arm_atsam/md_rgb_matrix.h b/tmk_core/protocol/arm_atsam/md_rgb_matrix.h
deleted file mode 100644
index bb3312e8e749..000000000000
--- a/tmk_core/protocol/arm_atsam/md_rgb_matrix.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#pragma once
-
-#include
-
-// From keyboard
-#include "config_led.h"
-
-// CS1-CS16 Current Source "Col"
-#define ISSI3733_CS_COUNT 16
-
-// SW1-SW12 Switch "Row"
-#define ISSI3733_SW_COUNT 12
-
-#define ISSI3733_LED_RGB_COUNT ISSI3733_CS_COUNT *ISSI3733_SW_COUNT
-#define ISSI3733_PG0_BYTES ISSI3733_LED_RGB_COUNT / 8 + 1 //+1 for first byte being memory start offset for I2C transfer
-#define ISSI3733_PG1_BYTES ISSI3733_LED_RGB_COUNT + 1 //+1 for first byte being memory start offset for I2C transfer
-#define ISSI3733_PG2_BYTES ISSI3733_LED_RGB_COUNT + 1 //+1 for first byte being memory start offset for I2C transfer
-#define ISSI3733_PG3_BYTES 18 + 1 //+1 for first byte being memory start offset for I2C transfer
-
-#define ISSI3733_PG_ONOFF_BYTES ISSI3733_PG0_BYTES
-#define ISSI3733_PG_OR_BYTES ISSI3733_PG0_BYTES
-#define ISSI3733_PG_SR_BYTES ISSI3733_PG0_BYTES
-#define ISSI3733_PG_PWM_BYTES ISSI3733_PG1_BYTES
-#define ISSI3733_PG_ABM_BYTES ISSI3733_PG2_BYTES
-#define ISSI3733_PG_FN_BYTES ISSI3733_PG3_BYTES
-
-typedef struct issi3733_driver_s {
- uint8_t addr; // Address of the driver according to wiring "ISSI3733: Table 1 Slave Address"
- uint8_t onoff[ISSI3733_PG_ONOFF_BYTES]; // PG0 - LED Control Register - LED On/Off Register
- uint8_t open[ISSI3733_PG_OR_BYTES]; // PG0 - LED Control Register - LED Open Register
- uint8_t shrt[ISSI3733_PG_SR_BYTES]; // PG0 - LED Control Register - LED Short Register
- uint8_t pwm[ISSI3733_PG_PWM_BYTES]; // PG1 - PWM Register
- uint8_t abm[ISSI3733_PG_ABM_BYTES]; // PG2 - Auto Breath Mode Register
- uint8_t conf[ISSI3733_PG_FN_BYTES]; // PG3 - Function Register
-} issi3733_driver_t;
-
-typedef struct issi3733_rgb_s {
- uint8_t *r; // Direct access into PWM data
- uint8_t *g; // Direct access into PWM data
- uint8_t *b; // Direct access into PWM data
-} issi3733_rgb_t;
-
-typedef struct issi3733_rgb_adr_s {
- uint8_t drv; // Driver from given list
- uint8_t cs; // CS
- uint8_t swr; // SW Red
- uint8_t swg; // SW Green
- uint8_t swb; // SW Blue
-} issi3733_rgb_adr_t;
-
-typedef struct issi3733_led_s {
- uint8_t id; // According to PCB ref
- issi3733_rgb_t rgb; // PWM settings of R G B
- issi3733_rgb_adr_t adr; // Hardware addresses
- float x; // Physical position X
- float y; // Physical position Y
- float px; // Physical position X in percent
- float py; // Physical position Y in percent
- uint8_t scan; // Key scan code from wiring (set 0xFF if no key)
-} issi3733_led_t;
-
-extern issi3733_driver_t issidrv[ISSI3733_DRIVER_COUNT];
-
-extern uint8_t gcr_breathe;
-extern uint8_t gcr_actual;
-extern uint8_t gcr_actual_last;
-
-void gcr_compute(void);
-
-void md_rgb_matrix_indicators_advanced(uint8_t led_min, uint8_t led_max);
-
-/*------------------------- Legacy Lighting Support ------------------------*/
-
-#ifdef USE_MASSDROP_CONFIGURATOR
-
-# define EF_NONE 0x00000000 // No effect
-# define EF_OVER 0x00000001 // Overwrite any previous color information with new
-# define EF_SCR_L 0x00000002 // Scroll left
-# define EF_SCR_R 0x00000004 // Scroll right
-# define EF_SUBTRACT 0x00000008 // Subtract color values
-
-typedef struct led_setup_s {
- float hs; // Band begin at percent
- float he; // Band end at percent
- uint8_t rs; // Red start value
- uint8_t re; // Red end value
- uint8_t gs; // Green start value
- uint8_t ge; // Green end value
- uint8_t bs; // Blue start value
- uint8_t be; // Blue end value
- uint32_t ef; // Animation and color effects
- uint8_t end; // Set to signal end of the setup
-} led_setup_t;
-
-extern const uint8_t led_setups_count;
-extern void * led_setups[];
-
-// LED Extra Instructions
-# define LED_FLAG_NULL 0x00 // Matching and coloring not used (default)
-# define LED_FLAG_MATCH_ID 0x01 // Match on the ID of the LED (set id#'s to desired bit pattern, first LED is id 1)
-# define LED_FLAG_MATCH_LAYER 0x02 // Match on the current active layer (set layer to desired match layer)
-# define LED_FLAG_USE_RGB 0x10 // Use a specific RGB value (set r, g, b to desired output color values)
-# define LED_FLAG_USE_PATTERN 0x20 // Use a specific pattern ID (set pattern_id to desired output pattern)
-# define LED_FLAG_USE_ROTATE_PATTERN 0x40 // Use pattern the user has cycled to manually
-
-typedef struct led_instruction_s {
- uint16_t flags; // Bitfield for LED instructions
- uint32_t id0; // Bitwise id, IDs 0-31
- uint32_t id1; // Bitwise id, IDs 32-63
- uint32_t id2; // Bitwise id, IDs 64-95
- uint32_t id3; // Bitwise id, IDs 96-127
- uint32_t id4; // Bitwise id, IDs 128-159
- uint32_t id5; // Bitwise id, IDs 160-191
- uint8_t layer;
- uint8_t r;
- uint8_t g;
- uint8_t b;
- uint8_t pattern_id;
- uint8_t end;
-} led_instruction_t;
-
-extern led_instruction_t led_instructions[];
-
-typedef struct led_config_s {
- uint8_t ver; // assumed to be zero on eeprom reset
-
- uint8_t desired_gcr;
- uint8_t animation_breathing;
- uint8_t animation_id;
- float animation_speed;
- uint8_t lighting_mode;
- uint8_t enabled;
- uint8_t animation_breathe_cur;
- uint8_t animation_direction;
- uint8_t animation_breathe_dir;
- uint8_t animation_orientation;
- uint8_t animation_circular;
- float edge_brightness;
- float ratio_brightness;
- uint8_t edge_mode;
-} md_led_config_t;
-
-extern md_led_config_t md_led_config;
-
-void md_led_changed(void);
-
-# define gcr_desired md_led_config.desired_gcr
-# define led_animation_breathing md_led_config.animation_breathing
-# define led_animation_id md_led_config.animation_id
-# define led_animation_speed md_led_config.animation_speed
-# define led_lighting_mode md_led_config.lighting_mode
-# define led_enabled md_led_config.enabled
-# define led_animation_breathe_cur md_led_config.animation_breathe_cur
-# define led_animation_direction md_led_config.animation_direction
-# define breathe_dir md_led_config.animation_breathe_dir
-# define led_animation_orientation md_led_config.animation_orientation
-# define led_animation_circular md_led_config.animation_circular
-# define led_edge_brightness md_led_config.edge_brightness
-# define led_ratio_brightness md_led_config.ratio_brightness
-# define led_edge_mode md_led_config.edge_mode
-
-# define LED_MODE_NORMAL 0 // Must be 0
-# define LED_MODE_KEYS_ONLY 1
-# define LED_MODE_NON_KEYS_ONLY 2
-# define LED_MODE_INDICATORS_ONLY 3
-# define LED_MODE_MAX_INDEX LED_MODE_INDICATORS_ONLY // Must be highest value
-
-# define LED_EDGE_MODE_ALL 0 // All edge LEDs are active (Must be 0)
-# define LED_EDGE_MODE_ALTERNATE 1 // Alternate mode of edge LEDs are active (Intention is for 'only every other edge LED' to be active)
-# define LED_EDGE_MODE_MAX LED_EDGE_MODE_ALTERNATE // Must be the highest valued LED edge mode
-
-# define LED_EDGE_FULL_MODE 255 // LEDs configured with this scan code will always be on for edge lighting modes
-# define LED_EDGE_ALT_MODE 254 // LEDs configured with this scan code will turn off in edge alternating mode
-# define LED_EDGE_MIN_SCAN 254 // LEDs configured with scan code >= to this are assigned as edge LEDs
-# define LED_INDICATOR_SCAN 253 // LEDs configured as dedicated indicators
-
-# define LED_IS_KEY(scan) (scan < LED_INDICATOR_SCAN) // Return true if an LED's scan value indicates it is a key LED
-# define LED_IS_EDGE(scan) (scan >= LED_EDGE_MIN_SCAN) // Return true if an LED's scan value indicates an edge LED
-# define LED_IS_EDGE_ALT(scan) (scan == LED_EDGE_ALT_MODE) // Return true if an LED's scan value indicates an alternate edge mode LED
-# define LED_IS_INDICATOR(scan) (scan == LED_INDICATOR_SCAN) // Return true if an LED's scan value indicates it is a dedicated Indicator
-#else
-extern uint8_t gcr_desired;
-#endif // USE_MASSDROP_CONFIGURATOR
diff --git a/tmk_core/protocol/arm_atsam/md_rgb_matrix_programs.c b/tmk_core/protocol/arm_atsam/md_rgb_matrix_programs.c
deleted file mode 100644
index 476b60529716..000000000000
--- a/tmk_core/protocol/arm_atsam/md_rgb_matrix_programs.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifdef RGB_MATRIX_ENABLE
-# ifdef USE_MASSDROP_CONFIGURATOR
-
-# include "md_rgb_matrix.h"
-# include "util.h"
-
-// Teal <-> Salmon
-led_setup_t leds_teal_salmon[] = {
- {.hs = 0, .he = 33, .rs = 24, .re = 24, .gs = 215, .ge = 215, .bs = 204, .be = 204, .ef = EF_NONE},
- {.hs = 33, .he = 66, .rs = 24, .re = 255, .gs = 215, .ge = 114, .bs = 204, .be = 118, .ef = EF_NONE},
- {.hs = 66, .he = 100, .rs = 255, .re = 255, .gs = 114, .ge = 114, .bs = 118, .be = 118, .ef = EF_NONE},
- {.end = 1},
-};
-
-// Yellow
-led_setup_t leds_yellow[] = {
- {.hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_NONE},
- {.end = 1},
-};
-
-// Off
-led_setup_t leds_off[] = {
- {.hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_NONE},
- {.end = 1},
-};
-
-// Red
-led_setup_t leds_red[] = {
- {.hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_NONE},
- {.end = 1},
-};
-
-// Green
-led_setup_t leds_green[] = {
- {.hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_NONE},
- {.end = 1},
-};
-
-// Blue
-led_setup_t leds_blue[] = {
- {.hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_NONE},
- {.end = 1},
-};
-
-// White
-led_setup_t leds_white[] = {
- {.hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 255, .be = 255, .ef = EF_NONE},
- {.end = 1},
-};
-
-// White with moving red stripe
-led_setup_t leds_white_with_red_stripe[] = {
- {.hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 255, .be = 255, .ef = EF_NONE},
- {.hs = 0, .he = 15, .rs = 0, .re = 0, .gs = 0, .ge = 255, .bs = 0, .be = 255, .ef = EF_SCR_R | EF_SUBTRACT},
- {.hs = 15, .he = 30, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 0, .ef = EF_SCR_R | EF_SUBTRACT},
- {.end = 1},
-};
-
-// Black with moving red stripe
-led_setup_t leds_black_with_red_stripe[] = {
- {.hs = 0, .he = 15, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_SCR_R},
- {.hs = 15, .he = 30, .rs = 255, .re = 0, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_SCR_R},
- {.end = 1},
-};
-
-// Rainbow no scrolling
-led_setup_t leds_rainbow_ns[] = {
- {.hs = 0, .he = 16.67, .rs = 255, .re = 255, .gs = 0, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER}, {.hs = 16.67, .he = 33.33, .rs = 255, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER}, {.hs = 33.33, .he = 50, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 255, .ef = EF_OVER}, {.hs = 50, .he = 66.67, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER}, {.hs = 66.67, .he = 83.33, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER}, {.hs = 83.33, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 0, .ef = EF_OVER}, {.end = 1},
-};
-
-// Rainbow scrolling
-led_setup_t leds_rainbow_s[] = {
- {.hs = 0, .he = 16.67, .rs = 255, .re = 255, .gs = 0, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER | EF_SCR_R}, {.hs = 16.67, .he = 33.33, .rs = 255, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER | EF_SCR_R}, {.hs = 33.33, .he = 50, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 255, .ef = EF_OVER | EF_SCR_R}, {.hs = 50, .he = 66.67, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER | EF_SCR_R}, {.hs = 66.67, .he = 83.33, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER | EF_SCR_R}, {.hs = 83.33, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 0, .ef = EF_OVER | EF_SCR_R}, {.end = 1},
-};
-
-// Add new LED animations here using one from above as example
-// The last entry must be { .end = 1 }
-// Add the new animation name to the list below following its format
-
-void *led_setups[] = {leds_rainbow_s, leds_rainbow_ns, leds_teal_salmon, leds_yellow, leds_red, leds_green, leds_blue, leds_white, leds_white_with_red_stripe, leds_black_with_red_stripe, leds_off};
-
-const uint8_t led_setups_count = ARRAY_SIZE(led_setups);
-
-# endif // USE_MASSDROP_CONFIGURATOR
-#endif // RGB_MATRIX_ENABLE
\ No newline at end of file
diff --git a/tmk_core/protocol/arm_atsam/shift_register.c b/tmk_core/protocol/arm_atsam/shift_register.c
deleted file mode 100644
index e81db4a19d7b..000000000000
--- a/tmk_core/protocol/arm_atsam/shift_register.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "arm_atsam_protocol.h"
-
-#include "spi_master.h"
-#include "wait.h"
-#include "gpio.h"
-
-// #define SR_USE_BITBANG
-
-// Bodge for when spi_master is not available
-#ifdef SR_USE_BITBANG
-# define CLOCK_DELAY 10
-
-void shift_init_impl(void) {
- gpio_set_pin_output(SR_EXP_RCLK_PIN);
- gpio_set_pin_output(SPI_DATAOUT_PIN);
- gpio_set_pin_output(SPI_SCLK_PIN);
-}
-
-void shift_out_impl(const uint8_t *data, uint16_t length) {
- gpio_write_pin_low(SR_EXP_RCLK_PIN);
- for (uint16_t i = 0; i < length; i++) {
- uint8_t val = data[i];
-
- // shift out lsb first
- for (uint8_t bit = 0; bit < 8; bit++) {
- gpio_write_pin(SPI_DATAOUT_PIN, !!(val & (1 << bit)));
- gpio_write_pin(SPI_SCLK_PIN, true);
- wait_us(CLOCK_DELAY);
-
- gpio_write_pin(SPI_SCLK_PIN, false);
- wait_us(CLOCK_DELAY);
- }
- }
- gpio_write_pin_high(SR_EXP_RCLK_PIN);
- return SPI_STATUS_SUCCESS;
-}
-
-#else
-
-void shift_init_impl(void) {
- spi_init();
-}
-
-void shift_out_impl(const uint8_t *data, uint16_t length) {
- spi_start(SR_EXP_RCLK_PIN, true, 0, 0);
-
- spi_transmit(data, length);
-
- spi_stop();
-}
-#endif
-
-// ***************************************************************
-
-void shift_out(const uint8_t *data, uint16_t length) {
- shift_out_impl(data, length);
-}
-
-void shift_enable(void) {
- gpio_set_pin_output(SR_EXP_OE_PIN);
- gpio_write_pin_low(SR_EXP_OE_PIN);
-}
-
-void shift_disable(void) {
- gpio_set_pin_output(SR_EXP_OE_PIN);
- gpio_write_pin_high(SR_EXP_OE_PIN);
-}
-
-void shift_init(void) {
- shift_disable();
- shift_init_impl();
-}
-
-// ***************************************************************
-
-sr_exp_t sr_exp_data;
-
-void SR_EXP_WriteData(void) {
- uint8_t data[2] = {
- sr_exp_data.reg & 0xFF, // Shift in bits 7-0
- (sr_exp_data.reg >> 8) & 0xFF, // Shift in bits 15-8
- };
- shift_out(data, 2);
-}
-
-void SR_EXP_Init(void) {
- shift_init();
-
- sr_exp_data.reg = 0;
- sr_exp_data.bit.HUB_CONNECT = 0;
- sr_exp_data.bit.HUB_RESET_N = 0;
- sr_exp_data.bit.S_UP = 0;
- sr_exp_data.bit.E_UP_N = 1;
- sr_exp_data.bit.S_DN1 = 1;
- sr_exp_data.bit.E_DN1_N = 1;
- sr_exp_data.bit.E_VBUS_1 = 0;
- sr_exp_data.bit.E_VBUS_2 = 0;
- sr_exp_data.bit.SRC_1 = 1;
- sr_exp_data.bit.SRC_2 = 1;
- sr_exp_data.bit.IRST = 1;
- sr_exp_data.bit.SDB_N = 0;
- SR_EXP_WriteData();
-
- shift_enable();
-}
diff --git a/tmk_core/protocol/arm_atsam/shift_register.h b/tmk_core/protocol/arm_atsam/shift_register.h
deleted file mode 100644
index 56a8c7f7177f..000000000000
--- a/tmk_core/protocol/arm_atsam/shift_register.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#pragma once
-
-#include
-
-/* Data structure to define Shift Register output expander hardware */
-/* This structure gets shifted into registers LSB first */
-typedef union {
- struct {
- uint16_t RSVD4 : 1; /*!< bit: 0 */
- uint16_t RSVD3 : 1; /*!< bit: 1 */
- uint16_t RSVD2 : 1; /*!< bit: 2 */
- uint16_t RSVD1 : 1; /*!< bit: 3 */
- uint16_t SDB_N : 1; /*!< bit: 4 SHUTDOWN THE CHIP WHEN 0, RUN WHEN 1 */
- uint16_t IRST : 1; /*!< bit: 5 RESET THE IS3733 I2C WHEN 1, RUN WHEN 0 */
- uint16_t SRC_2 : 1; /*!< bit: 6 ADVERTISE A SOURCE TO USBC-2 CC */
- uint16_t SRC_1 : 1; /*!< bit: 7 ADVERTISE A SOURCE TO USBC-1 CC */
- uint16_t E_VBUS_2 : 1; /*!< bit: 8 ENABLE 5V OUT TO USBC-2 WHEN 1 */
- uint16_t E_VBUS_1 : 1; /*!< bit: 9 ENABLE 5V OUT TO USBC-1 WHEN 1 */
- uint16_t E_DN1_N : 1; /*!< bit: 10 ENABLE DN1 1:2 MUX WHEN 0 */
- uint16_t S_DN1 : 1; /*!< bit: 11 SELECT DN1 PATH 0:USBC-1, 1:USBC-2 */
- uint16_t E_UP_N : 1; /*!< bit: 12 ENABLE SUP 1:2 MUX WHEN 0 */
- uint16_t S_UP : 1; /*!< bit: 13 SELECT UP PATH 0:USBC-1, 1:USBC-2 */
- uint16_t HUB_RESET_N : 1; /*!< bit: 14 RESET USB HUB WHEN 0, RUN WHEN 1 */
- uint16_t HUB_CONNECT : 1; /*!< bit: 15 SIGNAL VBUS CONNECT TO USB HUB WHEN 1 */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
-} sr_exp_t;
-
-extern sr_exp_t sr_exp_data;
-
-void SR_EXP_WriteData(void);
-void SR_EXP_Init(void);
diff --git a/tmk_core/protocol/arm_atsam/spi_master.c b/tmk_core/protocol/arm_atsam/spi_master.c
deleted file mode 100644
index fedb9654fde0..000000000000
--- a/tmk_core/protocol/arm_atsam/spi_master.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "arm_atsam_protocol.h"
-#include "spi_master.h"
-#include "gpio.h"
-
-/* Determine bits to set for mux selection */
-#if SPI_DATAOUT_PIN % 2 == 0
-# define SPI_DATAOUT_MUX_SEL PMUXE
-#else
-# define SPI_DATAOUT_MUX_SEL PMUXO
-#endif
-
-/* Determine bits to set for mux selection */
-#if SPI_SCLK_PIN % 2 == 0
-# define SPI_SCLK_MUX_SEL PMUXE
-#else
-# define SPI_SCLK_MUX_SEL PMUXO
-#endif
-
-static pin_t currentSelectPin = NO_PIN;
-
-__attribute__((weak)) void spi_init(void) {
- static bool is_initialised = false;
- if (!is_initialised) {
- is_initialised = true;
-
- DBGC(DC_SPI_INIT_BEGIN);
-
- CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
-
- // Set up MCU SPI pins
- PORT->Group[SAMD_PORT(SPI_DATAOUT_PIN)].PMUX[SAMD_PIN(SPI_DATAOUT_PIN) / 2].bit.SPI_DATAOUT_MUX_SEL = SPI_DATAOUT_MUX; // MUX select for sercom
- PORT->Group[SAMD_PORT(SPI_SCLK_PIN)].PMUX[SAMD_PIN(SPI_SCLK_PIN) / 2].bit.SPI_SCLK_MUX_SEL = SPI_SCLK_MUX; // MUX select for sercom
- PORT->Group[SAMD_PORT(SPI_DATAOUT_PIN)].PINCFG[SAMD_PIN(SPI_DATAOUT_PIN)].bit.PMUXEN = 1; // MUX Enable
- PORT->Group[SAMD_PORT(SPI_SCLK_PIN)].PINCFG[SAMD_PIN(SPI_SCLK_PIN)].bit.PMUXEN = 1; // MUX Enable
-
- DBGC(DC_SPI_INIT_COMPLETE);
- }
-}
-
-bool spi_start(pin_t csPin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
- if (currentSelectPin != NO_PIN || csPin == NO_PIN) {
- return false;
- }
-
- currentSelectPin = csPin;
- gpio_set_pin_output(currentSelectPin);
- gpio_write_pin_low(currentSelectPin);
-
- SPI_SERCOM->SPI.CTRLA.bit.DORD = lsbFirst; // Data Order - LSB is transferred first
- SPI_SERCOM->SPI.CTRLA.bit.CPOL = 1; // Clock Polarity - SCK high when idle. Leading edge of cycle is falling. Trailing rising.
- SPI_SERCOM->SPI.CTRLA.bit.CPHA = 1; // Clock Phase - Leading Edge Falling, change, Trailing Edge - Rising, sample
- SPI_SERCOM->SPI.CTRLA.bit.DIPO = 3; // Data In Pinout - SERCOM PAD[3] is used as data input (Configure away from DOPO. Not using input.)
- SPI_SERCOM->SPI.CTRLA.bit.DOPO = 0; // Data Output PAD[0], Serial Clock PAD[1]
- SPI_SERCOM->SPI.CTRLA.bit.MODE = 3; // Operating Mode - Master operation
-
- SPI_SERCOM->SPI.CTRLA.bit.ENABLE = 1; // Enable - Peripheral is enabled or being enabled
- while (SPI_SERCOM->SPI.SYNCBUSY.bit.ENABLE) {
- DBGC(DC_SPI_SYNC_ENABLING);
- }
- return true;
-}
-
-spi_status_t spi_transmit(const uint8_t *data, uint16_t length) {
- while (!(SPI_SERCOM->SPI.INTFLAG.bit.DRE)) {
- DBGC(DC_SPI_WRITE_DRE);
- }
-
- for (uint16_t i = 0; i < length; i++) {
- SPI_SERCOM->SPI.DATA.bit.DATA = data[i];
- while (!(SPI_SERCOM->SPI.INTFLAG.bit.TXC)) {
- DBGC(DC_SPI_WRITE_TXC_1);
- }
- }
-
- return SPI_STATUS_SUCCESS;
-}
-
-void spi_stop(void) {
- if (currentSelectPin != NO_PIN) {
- gpio_set_pin_output(currentSelectPin);
- gpio_write_pin_high(currentSelectPin);
- currentSelectPin = NO_PIN;
- }
-}
-
-// Not implemented yet....
-
-spi_status_t spi_write(uint8_t data);
-
-spi_status_t spi_read(void);
-
-spi_status_t spi_receive(uint8_t *data, uint16_t length);
diff --git a/tmk_core/protocol/arm_atsam/spi_master.h b/tmk_core/protocol/arm_atsam/spi_master.h
deleted file mode 100644
index 80678a57077e..000000000000
--- a/tmk_core/protocol/arm_atsam/spi_master.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2021 QMK
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
- */
-
-#pragma once
-
-#include
-#include
-#include "gpio.h"
-
-typedef int16_t spi_status_t;
-
-#define SPI_STATUS_SUCCESS (0)
-#define SPI_STATUS_ERROR (-1)
-#define SPI_STATUS_TIMEOUT (-2)
-
-#define SPI_TIMEOUT_IMMEDIATE (0)
-#define SPI_TIMEOUT_INFINITE (0xFFFF)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-void spi_init(void);
-
-bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor);
-
-spi_status_t spi_write(uint8_t data);
-
-spi_status_t spi_read(void);
-
-spi_status_t spi_transmit(const uint8_t *data, uint16_t length);
-
-spi_status_t spi_receive(uint8_t *data, uint16_t length);
-
-void spi_stop(void);
-#ifdef __cplusplus
-}
-#endif
diff --git a/tmk_core/protocol/arm_atsam/startup.c b/tmk_core/protocol/arm_atsam/startup.c
deleted file mode 100644
index ce043bad516a..000000000000
--- a/tmk_core/protocol/arm_atsam/startup.c
+++ /dev/null
@@ -1,563 +0,0 @@
-/**
- * \file
- *
- * \brief gcc starttup file for SAMD51
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#include "samd51.h"
-
-/* Initialize segments */
-extern uint32_t _sfixed;
-extern uint32_t _efixed;
-extern uint32_t _etext;
-extern uint32_t _srelocate;
-extern uint32_t _erelocate;
-extern uint32_t _szero;
-extern uint32_t _ezero;
-extern uint32_t _sstack;
-extern uint32_t _estack;
-
-/** \cond DOXYGEN_SHOULD_SKIP_THIS */
-int main(void);
-/** \endcond */
-
-void __libc_init_array(void);
-
-/* Default empty handler */
-void Dummy_Handler(void);
-
-/* Cortex-M4 core handlers */
-void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void MemManage_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void DebugMon_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-
-/* Peripherals handlers */
-void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void MCLK_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void OSCCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
-void OSCCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
-void OSCCTRL_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
-void OSCCTRL_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
-void OSCCTRL_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
-void OSC32KCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void SUPC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
-void SUPC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
-void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void EIC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
-void EIC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
-void EIC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
-void EIC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
-void EIC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
-void EIC_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
-void EIC_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
-void EIC_7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
-void EIC_8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
-void EIC_9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
-void EIC_10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
-void EIC_11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
-void EIC_12_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
-void EIC_13_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
-void EIC_14_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
-void EIC_15_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
-void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void NVMCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
-void NVMCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
-void DMAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
-void DMAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
-void DMAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
-void DMAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
-void DMAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17,
- DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
-void EVSYS_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
-void EVSYS_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
-void EVSYS_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
-void EVSYS_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
-void EVSYS_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
-void PAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void TAL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TAL_BRK */
-void TAL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TAL_IPS_0, TAL_IPS_1 */
-void RAMECC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void SERCOM0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
-void SERCOM0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
-void SERCOM0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
-void SERCOM0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
-void SERCOM1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
-void SERCOM1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
-void SERCOM1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
-void SERCOM1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
-void SERCOM2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
-void SERCOM2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
-void SERCOM2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
-void SERCOM2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
-void SERCOM3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
-void SERCOM3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
-void SERCOM3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
-void SERCOM3_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
-#ifdef ID_SERCOM4
-void SERCOM4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
-void SERCOM4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
-void SERCOM4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
-void SERCOM4_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
-#endif
-#ifdef ID_SERCOM5
-void SERCOM5_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
-void SERCOM5_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
-void SERCOM5_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
-void SERCOM5_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
-#endif
-#ifdef ID_SERCOM6
-void SERCOM6_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
-void SERCOM6_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
-void SERCOM6_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
-void SERCOM6_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
-#endif
-#ifdef ID_SERCOM7
-void SERCOM7_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
-void SERCOM7_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
-void SERCOM7_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
-void SERCOM7_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
-#endif
-#ifdef ID_CAN0
-void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_CAN1
-void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_USB
-void USB_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
-void USB_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
-void USB_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
-void USB_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
-#endif
-#ifdef ID_GMAC
-void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-void TCC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
-void TCC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
-void TCC0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
-void TCC0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
-void TCC0_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
-void TCC0_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
-void TCC0_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
-void TCC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
-void TCC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
-void TCC1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
-void TCC1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
-void TCC1_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
-void TCC2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
-void TCC2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
-void TCC2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
-void TCC2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
-#ifdef ID_TCC3
-void TCC3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
-void TCC3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
-void TCC3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
-#endif
-#ifdef ID_TCC4
-void TCC4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
-void TCC4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
-void TCC4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
-#endif
-void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#ifdef ID_TC4
-void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_TC5
-void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_TC6
-void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_TC7
-void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-void PDEC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
-void PDEC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
-void PDEC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
-void ADC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
-void ADC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
-void ADC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
-void ADC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
-void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void DAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
-void DAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
-void DAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
-void DAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
-void DAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
-#ifdef ID_I2S
-void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-void PCC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#ifdef ID_ICM
-void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_PUKCC
-void PUKCC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#ifdef ID_SDHC0
-void SDHC0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_SDHC1
-void SDHC1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
-#endif
-
-/* Exception Table */
-__attribute__((section(".vectors"))) const DeviceVectors exception_table = {
-
- /* Configure Initial Stack Pointer, using linker-generated symbols */
- .pvStack = (void *)(&_estack),
-
- .pfnReset_Handler = (void *)Reset_Handler,
- .pfnNMI_Handler = (void *)NMI_Handler,
- .pfnHardFault_Handler = (void *)HardFault_Handler,
- .pfnMemManage_Handler = (void *)MemManage_Handler,
- .pfnBusFault_Handler = (void *)BusFault_Handler,
- .pfnUsageFault_Handler = (void *)UsageFault_Handler,
- .pvReservedM9 = (void *)(0UL), /* Reserved */
- .pvReservedM8 = (void *)(0UL), /* Reserved */
- .pvReservedM7 = (void *)(0UL), /* Reserved */
- .pvReservedM6 = (void *)(0UL), /* Reserved */
- .pfnSVC_Handler = (void *)SVC_Handler,
- .pfnDebugMon_Handler = (void *)DebugMon_Handler,
- .pvReservedM3 = (void *)(0UL), /* Reserved */
- .pfnPendSV_Handler = (void *)PendSV_Handler,
- .pfnSysTick_Handler = (void *)SysTick_Handler,
-
- /* Configurable interrupts */
- .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */
- .pfnMCLK_Handler = (void *)MCLK_Handler, /* 1 Main Clock */
- .pfnOSCCTRL_0_Handler = (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
- .pfnOSCCTRL_1_Handler = (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
- .pfnOSCCTRL_2_Handler = (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
- .pfnOSCCTRL_3_Handler = (void *)OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
- .pfnOSCCTRL_4_Handler = (void *)OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
- .pfnOSC32KCTRL_Handler = (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
- .pfnSUPC_0_Handler = (void *)SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
- .pfnSUPC_1_Handler = (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
- .pfnWDT_Handler = (void *)WDT_Handler, /* 10 Watchdog Timer */
- .pfnRTC_Handler = (void *)RTC_Handler, /* 11 Real-Time Counter */
- .pfnEIC_0_Handler = (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */
- .pfnEIC_1_Handler = (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */
- .pfnEIC_2_Handler = (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */
- .pfnEIC_3_Handler = (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */
- .pfnEIC_4_Handler = (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */
- .pfnEIC_5_Handler = (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */
- .pfnEIC_6_Handler = (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */
- .pfnEIC_7_Handler = (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */
- .pfnEIC_8_Handler = (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */
- .pfnEIC_9_Handler = (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */
- .pfnEIC_10_Handler = (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */
- .pfnEIC_11_Handler = (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */
- .pfnEIC_12_Handler = (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */
- .pfnEIC_13_Handler = (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */
- .pfnEIC_14_Handler = (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */
- .pfnEIC_15_Handler = (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */
- .pfnFREQM_Handler = (void *)FREQM_Handler, /* 28 Frequency Meter */
- .pfnNVMCTRL_0_Handler = (void *)NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
- .pfnNVMCTRL_1_Handler = (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
- .pfnDMAC_0_Handler = (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
- .pfnDMAC_1_Handler = (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
- .pfnDMAC_2_Handler = (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
- .pfnDMAC_3_Handler = (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
- .pfnDMAC_4_Handler = (void *)DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19,
- DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
- .pfnEVSYS_0_Handler = (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
- .pfnEVSYS_1_Handler = (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
- .pfnEVSYS_2_Handler = (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
- .pfnEVSYS_3_Handler = (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
- .pfnEVSYS_4_Handler = (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
- .pfnPAC_Handler = (void *)PAC_Handler, /* 41 Peripheral Access Controller */
- .pfnTAL_0_Handler = (void *)TAL_0_Handler, /* 42 TAL_BRK */
- .pfnTAL_1_Handler = (void *)TAL_1_Handler, /* 43 TAL_IPS_0, TAL_IPS_1 */
- .pvReserved44 = (void *)(0UL), /* 44 Reserved */
- .pfnRAMECC_Handler = (void *)RAMECC_Handler, /* 45 RAM ECC */
- .pfnSERCOM0_0_Handler = (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */
- .pfnSERCOM0_1_Handler = (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */
- .pfnSERCOM0_2_Handler = (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */
- .pfnSERCOM0_3_Handler = (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
- .pfnSERCOM1_0_Handler = (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */
- .pfnSERCOM1_1_Handler = (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */
- .pfnSERCOM1_2_Handler = (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */
- .pfnSERCOM1_3_Handler = (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
- .pfnSERCOM2_0_Handler = (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */
- .pfnSERCOM2_1_Handler = (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */
- .pfnSERCOM2_2_Handler = (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */
- .pfnSERCOM2_3_Handler = (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
- .pfnSERCOM3_0_Handler = (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */
- .pfnSERCOM3_1_Handler = (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */
- .pfnSERCOM3_2_Handler = (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */
- .pfnSERCOM3_3_Handler = (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
-#ifdef ID_SERCOM4
- .pfnSERCOM4_0_Handler = (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */
- .pfnSERCOM4_1_Handler = (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */
- .pfnSERCOM4_2_Handler = (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */
- .pfnSERCOM4_3_Handler = (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
-#else
- .pvReserved62 = (void *)(0UL), /* 62 Reserved */
- .pvReserved63 = (void *)(0UL), /* 63 Reserved */
- .pvReserved64 = (void *)(0UL), /* 64 Reserved */
- .pvReserved65 = (void *)(0UL), /* 65 Reserved */
-#endif
-#ifdef ID_SERCOM5
- .pfnSERCOM5_0_Handler = (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */
- .pfnSERCOM5_1_Handler = (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */
- .pfnSERCOM5_2_Handler = (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */
- .pfnSERCOM5_3_Handler = (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
-#else
- .pvReserved66 = (void *)(0UL), /* 66 Reserved */
- .pvReserved67 = (void *)(0UL), /* 67 Reserved */
- .pvReserved68 = (void *)(0UL), /* 68 Reserved */
- .pvReserved69 = (void *)(0UL), /* 69 Reserved */
-#endif
-#ifdef ID_SERCOM6
- .pfnSERCOM6_0_Handler = (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */
- .pfnSERCOM6_1_Handler = (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */
- .pfnSERCOM6_2_Handler = (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */
- .pfnSERCOM6_3_Handler = (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
-#else
- .pvReserved70 = (void *)(0UL), /* 70 Reserved */
- .pvReserved71 = (void *)(0UL), /* 71 Reserved */
- .pvReserved72 = (void *)(0UL), /* 72 Reserved */
- .pvReserved73 = (void *)(0UL), /* 73 Reserved */
-#endif
-#ifdef ID_SERCOM7
- .pfnSERCOM7_0_Handler = (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */
- .pfnSERCOM7_1_Handler = (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */
- .pfnSERCOM7_2_Handler = (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */
- .pfnSERCOM7_3_Handler = (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
-#else
- .pvReserved74 = (void *)(0UL), /* 74 Reserved */
- .pvReserved75 = (void *)(0UL), /* 75 Reserved */
- .pvReserved76 = (void *)(0UL), /* 76 Reserved */
- .pvReserved77 = (void *)(0UL), /* 77 Reserved */
-#endif
-#ifdef ID_CAN0
- .pfnCAN0_Handler = (void *)CAN0_Handler, /* 78 Control Area Network 0 */
-#else
- .pvReserved78 = (void *)(0UL), /* 78 Reserved */
-#endif
-#ifdef ID_CAN1
- .pfnCAN1_Handler = (void *)CAN1_Handler, /* 79 Control Area Network 1 */
-#else
- .pvReserved79 = (void *)(0UL), /* 79 Reserved */
-#endif
-#ifdef ID_USB
- .pfnUSB_0_Handler = (void *)USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
- .pfnUSB_1_Handler = (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */
- .pfnUSB_2_Handler = (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
- .pfnUSB_3_Handler = (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
-#else
- .pvReserved80 = (void *)(0UL), /* 80 Reserved */
- .pvReserved81 = (void *)(0UL), /* 81 Reserved */
- .pvReserved82 = (void *)(0UL), /* 82 Reserved */
- .pvReserved83 = (void *)(0UL), /* 83 Reserved */
-#endif
-#ifdef ID_GMAC
- .pfnGMAC_Handler = (void *)GMAC_Handler, /* 84 Ethernet MAC */
-#else
- .pvReserved84 = (void *)(0UL), /* 84 Reserved */
-#endif
- .pfnTCC0_0_Handler = (void *)TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
- .pfnTCC0_1_Handler = (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */
- .pfnTCC0_2_Handler = (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */
- .pfnTCC0_3_Handler = (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */
- .pfnTCC0_4_Handler = (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */
- .pfnTCC0_5_Handler = (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */
- .pfnTCC0_6_Handler = (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */
- .pfnTCC1_0_Handler = (void *)TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
- .pfnTCC1_1_Handler = (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */
- .pfnTCC1_2_Handler = (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */
- .pfnTCC1_3_Handler = (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */
- .pfnTCC1_4_Handler = (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */
- .pfnTCC2_0_Handler = (void *)TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
- .pfnTCC2_1_Handler = (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */
- .pfnTCC2_2_Handler = (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */
- .pfnTCC2_3_Handler = (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */
-#ifdef ID_TCC3
- .pfnTCC3_0_Handler = (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
- .pfnTCC3_1_Handler = (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */
- .pfnTCC3_2_Handler = (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */
-#else
- .pvReserved101 = (void *)(0UL), /* 101 Reserved */
- .pvReserved102 = (void *)(0UL), /* 102 Reserved */
- .pvReserved103 = (void *)(0UL), /* 103 Reserved */
-#endif
-#ifdef ID_TCC4
- .pfnTCC4_0_Handler = (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
- .pfnTCC4_1_Handler = (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */
- .pfnTCC4_2_Handler = (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */
-#else
- .pvReserved104 = (void *)(0UL), /* 104 Reserved */
- .pvReserved105 = (void *)(0UL), /* 105 Reserved */
- .pvReserved106 = (void *)(0UL), /* 106 Reserved */
-#endif
- .pfnTC0_Handler = (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */
- .pfnTC1_Handler = (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */
- .pfnTC2_Handler = (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */
- .pfnTC3_Handler = (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */
-#ifdef ID_TC4
- .pfnTC4_Handler = (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */
-#else
- .pvReserved111 = (void *)(0UL), /* 111 Reserved */
-#endif
-#ifdef ID_TC5
- .pfnTC5_Handler = (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */
-#else
- .pvReserved112 = (void *)(0UL), /* 112 Reserved */
-#endif
-#ifdef ID_TC6
- .pfnTC6_Handler = (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */
-#else
- .pvReserved113 = (void *)(0UL), /* 113 Reserved */
-#endif
-#ifdef ID_TC7
- .pfnTC7_Handler = (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */
-#else
- .pvReserved114 = (void *)(0UL), /* 114 Reserved */
-#endif
- .pfnPDEC_0_Handler = (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
- .pfnPDEC_1_Handler = (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */
- .pfnPDEC_2_Handler = (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */
- .pfnADC0_0_Handler = (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
- .pfnADC0_1_Handler = (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */
- .pfnADC1_0_Handler = (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
- .pfnADC1_1_Handler = (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */
- .pfnAC_Handler = (void *)AC_Handler, /* 122 Analog Comparators */
- .pfnDAC_0_Handler = (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
- .pfnDAC_1_Handler = (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */
- .pfnDAC_2_Handler = (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */
- .pfnDAC_3_Handler = (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */
- .pfnDAC_4_Handler = (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */
-#ifdef ID_I2S
- .pfnI2S_Handler = (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */
-#else
- .pvReserved128 = (void *)(0UL), /* 128 Reserved */
-#endif
- .pfnPCC_Handler = (void *)PCC_Handler, /* 129 Parallel Capture Controller */
- .pfnAES_Handler = (void *)AES_Handler, /* 130 Advanced Encryption Standard */
- .pfnTRNG_Handler = (void *)TRNG_Handler, /* 131 True Random Generator */
-#ifdef ID_ICM
- .pfnICM_Handler = (void *)ICM_Handler, /* 132 Integrity Check Monitor */
-#else
- .pvReserved132 = (void *)(0UL), /* 132 Reserved */
-#endif
-#ifdef ID_PUKCC
- .pfnPUKCC_Handler = (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
-#else
- .pvReserved133 = (void *)(0UL), /* 133 Reserved */
-#endif
- .pfnQSPI_Handler = (void *)QSPI_Handler, /* 134 Quad SPI interface */
-#ifdef ID_SDHC0
- .pfnSDHC0_Handler = (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
-#else
- .pvReserved135 = (void *)(0UL), /* 135 Reserved */
-#endif
-#ifdef ID_SDHC1
- .pfnSDHC1_Handler = (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
-#else
- .pvReserved136 = (void *)(0UL) /* 136 Reserved */
-#endif
-};
-
-// WARNING: These are only for CTRL bootloader release "v2.18Jun 22 2018 17:28:08" for bootloader_jump support
-extern uint32_t _eram;
-#define BOOTLOADER_MAGIC 0x3B9ACA00
-#define MAGIC_ADDR (uint32_t *)((intptr_t)(&_eram) - 4)
-
-/**
- * \brief This is the code that gets called on processor reset.
- * To initialize the device, and call the main() routine.
- */
-void Reset_Handler(void) {
-#ifdef KEYBOARD_massdrop_ctrl
- /* WARNING: This is only for CTRL bootloader release "v2.18Jun 22 2018 17:28:08" for bootloader_jump support */
- if (*MAGIC_ADDR == BOOTLOADER_MAGIC) {
- /* At this point, the bootloader's memory is initialized properly, so undo the jump to here, then jump back */
- *MAGIC_ADDR = 0x00000000; /* Change value to prevent potential bootloader entrance loop */
- __set_MSP(0x20008818); /* MSP according to bootloader */
- SCB->VTOR = 0x00000000; /* Vector table back to bootloader's */
- asm("bx %0" ::"r"(0x00001267)); /* Jump past bootloader RCAUSE check using THUMB */
- }
-#endif
- uint32_t *pSrc, *pDest;
-
- /* Initialize the relocate segment */
- pSrc = &_etext;
- pDest = &_srelocate;
-
- if (pSrc != pDest) {
- for (; pDest < &_erelocate;) {
- *pDest++ = *pSrc++;
- }
- }
-
- /* Clear the zero segment */
- for (pDest = &_szero; pDest < &_ezero;) {
- *pDest++ = 0;
- }
-
- /* Set the vector table base address */
- pSrc = (uint32_t *)&_sfixed;
- SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
-
-#if __FPU_USED
- /* Enable FPU */
- SCB->CPACR |= (0xFu << 20);
- __DSB();
- __ISB();
-#endif
-
- /* Initialize the C library */
- __libc_init_array();
-
- /* Branch to main function */
- main();
-
- /* Infinite loop */
- while (1)
- ;
-}
-
-/**
- * \brief Default interrupt handler for unused IRQs.
- */
-void Dummy_Handler(void) {
- while (1) {
- }
-}
diff --git a/tmk_core/protocol/arm_atsam/usb/compiler.h b/tmk_core/protocol/arm_atsam/usb/compiler.h
deleted file mode 100644
index 9fb04ff6280c..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/compiler.h
+++ /dev/null
@@ -1,1079 +0,0 @@
-/**
- * \file
- *
- * \brief Commonly used includes, types and macros.
- *
- * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef UTILS_COMPILER_H_INCLUDED
-#define UTILS_COMPILER_H_INCLUDED
-
-/**
- * \defgroup group_sam0_utils Compiler abstraction layer and code utilities
- *
- * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices.
- * This module provides various abstraction layers and utilities to make code compatible between different compilers.
- *
- * @{
- */
-
-#if (defined __ICCARM__)
-# include
-#endif
-
-#include
-//#include
-//#include
-//#include
-//#include
-
-#ifndef __ASSEMBLY__
-
-# include
-# include
-# include
-# include
-
-/**
- * \def UNUSED
- * \brief Marking \a v as a unused parameter or value.
- */
-# define UNUSED(v) (void)(v)
-
-/**
- * \def barrier
- * \brief Memory barrier
- */
-# ifdef __GNUC__
-# define barrier() asm volatile("" ::: "memory")
-# else
-# define barrier() asm("")
-# endif
-
-/**
- * \brief Emit the compiler pragma \a arg.
- *
- * \param[in] arg The pragma directive as it would appear after \e \#pragma
- * (i.e. not stringified).
- */
-# define COMPILER_PRAGMA(arg) _Pragma(# arg)
-
-/**
- * \def COMPILER_PACK_SET(alignment)
- * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
- */
-# define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
-
-/**
- * \def COMPILER_PACK_RESET()
- * \brief Set default alignment for subsequent struct and union definitions.
- */
-# define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
-
-/**
- * \brief Set aligned boundary.
- */
-# if (defined __GNUC__) || (defined __CC_ARM)
-# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
-# elif (defined __ICCARM__)
-# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
-# endif
-
-/**
- * \brief Set word-aligned boundary.
- */
-# if (defined __GNUC__) || defined(__CC_ARM)
-# define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
-# elif (defined __ICCARM__)
-# define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
-# endif
-
-/**
- * \def __always_inline
- * \brief The function should always be inlined.
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and inline the function no matter how big it thinks it
- * becomes.
- */
-# if !defined(__always_inline)
-# if defined(__CC_ARM)
-# define __always_inline __forceinline
-# elif (defined __GNUC__)
-# define __always_inline __attribute__((__always_inline__))
-# elif (defined __ICCARM__)
-# define __always_inline _Pragma("inline=forced")
-# endif
-# endif
-
-/**
- * \def __no_inline
- * \brief The function should never be inlined
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and not inline the function no matter how small it thinks it
- * becomes.
- */
-# if defined(__CC_ARM)
-# define __no_inline __attribute__((noinline))
-# elif (defined __GNUC__)
-# define __no_inline __attribute__((noinline))
-# elif (defined __ICCARM__)
-# define __no_inline _Pragma("inline=never")
-# endif
-
-/** \brief This macro is used to test fatal errors.
- *
- * The macro tests if the expression is false. If it is, a fatal error is
- * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO
- * is defined, a unit test version of the macro is used, to allow execution
- * of further tests after a false expression.
- *
- * \param[in] expr Expression to evaluate and supposed to be nonzero.
- */
-# if defined(_ASSERT_ENABLE_)
-# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
-# include "unit_test/suite.h"
-# else
-# undef TEST_SUITE_DEFINE_ASSERT_MACRO
-# define Assert(expr) \
- { \
- if (!(expr)) asm("BKPT #0"); \
- }
-# endif
-# else
-# define Assert(expr) ((void)0)
-# endif
-
-/* Define WEAK attribute */
-# if defined(__CC_ARM)
-# define WEAK __attribute__((weak))
-# elif defined(__ICCARM__)
-# define WEAK __weak
-# elif defined(__GNUC__)
-# define WEAK __attribute__((weak))
-# endif
-
-/* Define NO_INIT attribute */
-# if defined(__CC_ARM)
-# define NO_INIT __attribute__((zero_init))
-# elif defined(__ICCARM__)
-# define NO_INIT __no_init
-# elif defined(__GNUC__)
-# define NO_INIT __attribute__((section(".no_init")))
-# endif
-
-//#include "interrupt.h"
-
-/** \name Usual Types
- * @{ */
-# ifndef __cplusplus
-# if !defined(__bool_true_false_are_defined)
-typedef unsigned char bool;
-# endif
-# endif
-typedef uint16_t le16_t;
-typedef uint16_t be16_t;
-typedef uint32_t le32_t;
-typedef uint32_t be32_t;
-typedef uint32_t iram_size_t;
-/** @} */
-
-/** \name Aliasing Aggregate Types
- * @{ */
-
-/** 16-bit union. */
-typedef union {
- int16_t s16;
- uint16_t u16;
- int8_t s8[2];
- uint8_t u8[2];
-} Union16;
-
-/** 32-bit union. */
-typedef union {
- int32_t s32;
- uint32_t u32;
- int16_t s16[2];
- uint16_t u16[2];
- int8_t s8[4];
- uint8_t u8[4];
-} Union32;
-
-/** 64-bit union. */
-typedef union {
- int64_t s64;
- uint64_t u64;
- int32_t s32[2];
- uint32_t u32[2];
- int16_t s16[4];
- uint16_t u16[4];
- int8_t s8[8];
- uint8_t u8[8];
-} Union64;
-
-/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union {
- int64_t * s64ptr;
- uint64_t *u64ptr;
- int32_t * s32ptr;
- uint32_t *u32ptr;
- int16_t * s16ptr;
- uint16_t *u16ptr;
- int8_t * s8ptr;
- uint8_t * u8ptr;
-} UnionPtr;
-
-/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union {
- volatile int64_t * s64ptr;
- volatile uint64_t *u64ptr;
- volatile int32_t * s32ptr;
- volatile uint32_t *u32ptr;
- volatile int16_t * s16ptr;
- volatile uint16_t *u16ptr;
- volatile int8_t * s8ptr;
- volatile uint8_t * u8ptr;
-} UnionVPtr;
-
-/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union {
- const int64_t * s64ptr;
- const uint64_t *u64ptr;
- const int32_t * s32ptr;
- const uint32_t *u32ptr;
- const int16_t * s16ptr;
- const uint16_t *u16ptr;
- const int8_t * s8ptr;
- const uint8_t * u8ptr;
-} UnionCPtr;
-
-/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union {
- const volatile int64_t * s64ptr;
- const volatile uint64_t *u64ptr;
- const volatile int32_t * s32ptr;
- const volatile uint32_t *u32ptr;
- const volatile int16_t * s16ptr;
- const volatile uint16_t *u16ptr;
- const volatile int8_t * s8ptr;
- const volatile uint8_t * u8ptr;
-} UnionCVPtr;
-
-/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct {
- int64_t * s64ptr;
- uint64_t *u64ptr;
- int32_t * s32ptr;
- uint32_t *u32ptr;
- int16_t * s16ptr;
- uint16_t *u16ptr;
- int8_t * s8ptr;
- uint8_t * u8ptr;
-} StructPtr;
-
-/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct {
- volatile int64_t * s64ptr;
- volatile uint64_t *u64ptr;
- volatile int32_t * s32ptr;
- volatile uint32_t *u32ptr;
- volatile int16_t * s16ptr;
- volatile uint16_t *u16ptr;
- volatile int8_t * s8ptr;
- volatile uint8_t * u8ptr;
-} StructVPtr;
-
-/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct {
- const int64_t * s64ptr;
- const uint64_t *u64ptr;
- const int32_t * s32ptr;
- const uint32_t *u32ptr;
- const int16_t * s16ptr;
- const uint16_t *u16ptr;
- const int8_t * s8ptr;
- const uint8_t * u8ptr;
-} StructCPtr;
-
-/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct {
- const volatile int64_t * s64ptr;
- const volatile uint64_t *u64ptr;
- const volatile int32_t * s32ptr;
- const volatile uint32_t *u32ptr;
- const volatile int16_t * s16ptr;
- const volatile uint16_t *u16ptr;
- const volatile int8_t * s8ptr;
- const volatile uint8_t * u8ptr;
-} StructCVPtr;
-
-/** @} */
-
-#endif /* #ifndef __ASSEMBLY__ */
-
-/** \name Usual Constants
- * @{ */
-// kmod #define DISABLE 0
-// kmod #define ENABLE 1
-
-#ifndef __cplusplus
-# if !defined(__bool_true_false_are_defined)
-# define false 0
-# define true 1
-# endif
-#endif
-/** @} */
-
-#ifndef __ASSEMBLY__
-
-/** \name Optimization Control
- * @{ */
-
-/**
- * \def likely(exp)
- * \brief The expression \a exp is likely to be true
- */
-# if !defined(likely) || defined(__DOXYGEN__)
-# define likely(exp) (exp)
-# endif
-
-/**
- * \def unlikely(exp)
- * \brief The expression \a exp is unlikely to be true
- */
-# if !defined(unlikely) || defined(__DOXYGEN__)
-# define unlikely(exp) (exp)
-# endif
-
-/**
- * \def is_constant(exp)
- * \brief Determine if an expression evaluates to a constant value.
- *
- * \param[in] exp Any expression
- *
- * \return true if \a exp is constant, false otherwise.
- */
-# if (defined __GNUC__) || (defined __CC_ARM)
-# define is_constant(exp) __builtin_constant_p(exp)
-# else
-# define is_constant(exp) (0)
-# endif
-
-/** @} */
-
-/** \name Bit-Field Handling
- * @{ */
-
-/** \brief Reads the bits of a value specified by a given bit-mask.
- *
- * \param[in] value Value to read bits from.
- * \param[in] mask Bit-mask indicating bits to read.
- *
- * \return Read bits.
- */
-# define Rd_bits(value, mask) ((value) & (mask))
-
-/** \brief Writes the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue C lvalue to write bits to.
- * \param[in] mask Bit-mask indicating bits to write.
- * \param[in] bits Bits to write.
- *
- * \return Resulting value with written bits.
- */
-# define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) | ((bits) & (mask)))
-
-/** \brief Tests the bits of a value specified by a given bit-mask.
- *
- * \param[in] value Value of which to test bits.
- * \param[in] mask Bit-mask indicating bits to test.
- *
- * \return \c 1 if at least one of the tested bits is set, else \c 0.
- */
-# define Tst_bits(value, mask) (Rd_bits(value, mask) != 0)
-
-/** \brief Clears the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue C lvalue of which to clear bits.
- * \param[in] mask Bit-mask indicating bits to clear.
- *
- * \return Resulting value with cleared bits.
- */
-# define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
-
-/** \brief Sets the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue C lvalue of which to set bits.
- * \param[in] mask Bit-mask indicating bits to set.
- *
- * \return Resulting value with set bits.
- */
-# define Set_bits(lvalue, mask) ((lvalue) |= (mask))
-
-/** \brief Toggles the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue C lvalue of which to toggle bits.
- * \param[in] mask Bit-mask indicating bits to toggle.
- *
- * \return Resulting value with toggled bits.
- */
-# define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
-
-/** \brief Reads the bit-field of a value specified by a given bit-mask.
- *
- * \param[in] value Value to read a bit-field from.
- * \param[in] mask Bit-mask indicating the bit-field to read.
- *
- * \return Read bit-field.
- */
-# define Rd_bitfield(value, mask) (Rd_bits(value, mask) >> ctz(mask))
-
-/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue C lvalue to write a bit-field to.
- * \param[in] mask Bit-mask indicating the bit-field to write.
- * \param[in] bitfield Bit-field to write.
- *
- * \return Resulting value with written bit-field.
- */
-# define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask)))
-
-/** @} */
-
-/** \name Zero-Bit Counting
- *
- * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
- * applied to constant expressions (values known at compile time), so they are
- * more optimized than the use of the corresponding assembly instructions and
- * they can be used as constant expressions e.g. to initialize objects having
- * static storage duration, and like the corresponding assembly instructions
- * when applied to non-constant expressions (values unknown at compile time), so
- * they are more optimized than an assembly periphrasis. Hence, clz and ctz
- * ensure a possible and optimized behavior for both constant and non-constant
- * expressions.
- *
- * @{ */
-
-/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
- *
- * \param[in] u Value of which to count the leading zero bits.
- *
- * \return The count of leading zero bits in \a u.
- */
-# if (defined __GNUC__) || (defined __CC_ARM)
-# define clz(u) ((u) ? __builtin_clz(u) : 32)
-# else
-# define clz(u) (((u) == 0) ? 32 : ((u) & (1ul << 31)) ? 0 : ((u) & (1ul << 30)) ? 1 : ((u) & (1ul << 29)) ? 2 : ((u) & (1ul << 28)) ? 3 : ((u) & (1ul << 27)) ? 4 : ((u) & (1ul << 26)) ? 5 : ((u) & (1ul << 25)) ? 6 : ((u) & (1ul << 24)) ? 7 : ((u) & (1ul << 23)) ? 8 : ((u) & (1ul << 22)) ? 9 : ((u) & (1ul << 21)) ? 10 : ((u) & (1ul << 20)) ? 11 : ((u) & (1ul << 19)) ? 12 : ((u) & (1ul << 18)) ? 13 : ((u) & (1ul << 17)) ? 14 : ((u) & (1ul << 16)) ? 15 : ((u) & (1ul << 15)) ? 16 : ((u) & (1ul << 14)) ? 17 : ((u) & (1ul << 13)) ? 18 : ((u) & (1ul << 12)) ? 19 : ((u) & (1ul << 11)) ? 20 : ((u) & (1ul << 10)) ? 21 : ((u) & (1ul << 9)) ? 22 : ((u) & (1ul << 8)) ? 23 : ((u) & (1ul << 7)) ? 24 : ((u) & (1ul << 6)) ? 25 : ((u) & (1ul << 5)) ? 26 : ((u) & (1ul << 4)) ? 27 : ((u) & (1ul << 3)) ? 28 : ((u) & (1ul << 2)) ? 29 : ((u) & (1ul << 1)) ? 30 : 31)
-# endif
-
-/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
- *
- * \param[in] u Value of which to count the trailing zero bits.
- *
- * \return The count of trailing zero bits in \a u.
- */
-# if (defined __GNUC__) || (defined __CC_ARM)
-# define ctz(u) ((u) ? __builtin_ctz(u) : 32)
-# else
-# define ctz(u) ((u) & (1ul << 0) ? 0 : (u) & (1ul << 1) ? 1 : (u) & (1ul << 2) ? 2 : (u) & (1ul << 3) ? 3 : (u) & (1ul << 4) ? 4 : (u) & (1ul << 5) ? 5 : (u) & (1ul << 6) ? 6 : (u) & (1ul << 7) ? 7 : (u) & (1ul << 8) ? 8 : (u) & (1ul << 9) ? 9 : (u) & (1ul << 10) ? 10 : (u) & (1ul << 11) ? 11 : (u) & (1ul << 12) ? 12 : (u) & (1ul << 13) ? 13 : (u) & (1ul << 14) ? 14 : (u) & (1ul << 15) ? 15 : (u) & (1ul << 16) ? 16 : (u) & (1ul << 17) ? 17 : (u) & (1ul << 18) ? 18 : (u) & (1ul << 19) ? 19 : (u) & (1ul << 20) ? 20 : (u) & (1ul << 21) ? 21 : (u) & (1ul << 22) ? 22 : (u) & (1ul << 23) ? 23 : (u) & (1ul << 24) ? 24 : (u) & (1ul << 25) ? 25 : (u) & (1ul << 26) ? 26 : (u) & (1ul << 27) ? 27 : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32)
-# endif
-
-/** @} */
-
-/** \name Bit Reversing
- * @{ */
-
-/** \brief Reverses the bits of \a u8.
- *
- * \param[in] u8 U8 of which to reverse the bits.
- *
- * \return Value resulting from \a u8 with reversed bits.
- */
-# define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
-
-/** \brief Reverses the bits of \a u16.
- *
- * \param[in] u16 U16 of which to reverse the bits.
- *
- * \return Value resulting from \a u16 with reversed bits.
- */
-# define bit_reverse16(u16) ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16))
-
-/** \brief Reverses the bits of \a u32.
- *
- * \param[in] u32 U32 of which to reverse the bits.
- *
- * \return Value resulting from \a u32 with reversed bits.
- */
-# define bit_reverse32(u32) __RBIT(u32)
-
-/** \brief Reverses the bits of \a u64.
- *
- * \param[in] u64 U64 of which to reverse the bits.
- *
- * \return Value resulting from \a u64 with reversed bits.
- */
-# define bit_reverse64(u64) ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) | ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32)))
-
-/** @} */
-
-/** \name Alignment
- * @{ */
-
-/** \brief Tests alignment of the number \a val with the \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n Boundary.
- *
- * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
- */
-# define Test_align(val, n) (!Tst_bits(val, (n)-1))
-
-/** \brief Gets alignment of the number \a val with respect to the \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n Boundary.
- *
- * \return Alignment of the number \a val with respect to the \a n boundary.
- */
-# define Get_align(val, n) (Rd_bits(val, (n)-1))
-
-/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
- *
- * \param[in] lval Input/output lvalue.
- * \param[in] n Boundary.
- * \param[in] alg Alignment.
- *
- * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
- */
-# define Set_align(lval, n, alg) (Wr_bits(lval, (n)-1, alg))
-
-/** \brief Aligns the number \a val with the upper \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n Boundary.
- *
- * \return Value resulting from the number \a val aligned with the upper \a n boundary.
- */
-# define Align_up(val, n) (((val) + ((n)-1)) & ~((n)-1))
-
-/** \brief Aligns the number \a val with the lower \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n Boundary.
- *
- * \return Value resulting from the number \a val aligned with the lower \a n boundary.
- */
-# define Align_down(val, n) ((val) & ~((n)-1))
-
-/** @} */
-
-/** \name Mathematics
- *
- * The same considerations as for clz and ctz apply here but GCC does not
- * provide built-in functions to access the assembly instructions abs, min and
- * max and it does not produce them by itself in most cases, so two sets of
- * macros are defined here:
- * - Abs, Min and Max to apply to constant expressions (values known at
- * compile time);
- * - abs, min and max to apply to non-constant expressions (values unknown at
- * compile time), abs is found in stdlib.h.
- *
- * @{ */
-
-/** \brief Takes the absolute value of \a a.
- *
- * \param[in] a Input value.
- *
- * \return Absolute value of \a a.
- *
- * \note More optimized if only used with values known at compile time.
- */
-# define Abs(a) (((a) < 0) ? -(a) : (a))
-
-# ifndef __cplusplus
-/** \brief Takes the minimal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-# define Min(a, b) (((a) < (b)) ? (a) : (b))
-
-/** \brief Takes the maximal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-# define Max(a, b) (((a) > (b)) ? (a) : (b))
-
-/** \brief Takes the minimal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-# define min(a, b) Min(a, b)
-
-/** \brief Takes the maximal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-# define max(a, b) Max(a, b)
-# endif
-
-/** @} */
-
-/** \brief Calls the routine at address \a addr.
- *
- * It generates a long call opcode.
- *
- * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
- * it is invoked from the CPU supervisor mode.
- *
- * \param[in] addr Address of the routine to call.
- *
- * \note It may be used as a long jump opcode in some special cases.
- */
-# define Long_call(addr) ((*(void (*)(void))(addr))())
-
-/** \name MCU Endianism Handling
- * ARM is MCU little endian.
- *
- * @{ */
-# define BE16(x) swap16(x)
-# define LE16(x) (x)
-
-# define le16_to_cpu(x) (x)
-# define cpu_to_le16(x) (x)
-# define LE16_TO_CPU(x) (x)
-# define CPU_TO_LE16(x) (x)
-
-# define be16_to_cpu(x) swap16(x)
-# define cpu_to_be16(x) swap16(x)
-# define BE16_TO_CPU(x) swap16(x)
-# define CPU_TO_BE16(x) swap16(x)
-
-# define le32_to_cpu(x) (x)
-# define cpu_to_le32(x) (x)
-# define LE32_TO_CPU(x) (x)
-# define CPU_TO_LE32(x) (x)
-
-# define be32_to_cpu(x) swap32(x)
-# define cpu_to_be32(x) swap32(x)
-# define BE32_TO_CPU(x) swap32(x)
-# define CPU_TO_BE32(x) swap32(x)
-/** @} */
-
-/** \name Endianism Conversion
- *
- * The same considerations as for clz and ctz apply here but GCC's
- * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
- * applied to constant expressions, so two sets of macros are defined here:
- * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
- * at compile time);
- * - swap16, swap32 and swap64 to apply to non-constant expressions (values
- * unknown at compile time).
- *
- * @{ */
-
-/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param[in] u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-# define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8)))
-
-/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param[in] u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-# define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) | ((uint32_t)Swap16((uint32_t)(u32)) << 16)))
-
-/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param[in] u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-# define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) | ((uint64_t)Swap32((uint64_t)(u64)) << 32)))
-
-/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param[in] u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-# define swap16(u16) Swap16(u16)
-
-/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param[in] u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-# if (defined __GNUC__)
-# define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32)))
-# else
-# define swap32(u32) Swap32(u32)
-# endif
-
-/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param[in] u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-# if (defined __GNUC__)
-# define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64)))
-# else
-# define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) | ((uint64_t)swap32((uint64_t)(u64)) << 32)))
-# endif
-
-/** @} */
-
-/** \name Target Abstraction
- *
- * @{ */
-
-# define _GLOBEXT_ extern /**< extern storage-class specifier. */
-# define _CONST_TYPE_ const /**< const type qualifier. */
-# define _MEM_TYPE_SLOW_ /**< Slow memory type. */
-# define _MEM_TYPE_MEDFAST_ /**< Fairly fast memory type. */
-# define _MEM_TYPE_FAST_ /**< Fast memory type. */
-
-# define memcmp_ram2ram memcmp /**< Target-specific memcmp of RAM to RAM. */
-# define memcmp_code2ram memcmp /**< Target-specific memcmp of RAM to NVRAM. */
-# define memcpy_ram2ram memcpy /**< Target-specific memcpy from RAM to RAM. */
-# define memcpy_code2ram memcpy /**< Target-specific memcpy from NVRAM to RAM. */
-
-/** @} */
-
-/**
- * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
- * integer arithmetic.
- *
- * \param[in] a An integer
- * \param[in] b Another integer
- *
- * \return (\a a / \a b) rounded up to the nearest integer.
- */
-# define div_ceil(a, b) (((a) + (b)-1) / (b))
-
-#endif /* #ifndef __ASSEMBLY__ */
-#ifdef __ICCARM__
-/** \name Compiler Keywords
- *
- * Port of some keywords from GCC to IAR Embedded Workbench.
- *
- * @{ */
-
-# define __asm__ asm
-# define __inline__ inline
-# define __volatile__
-
-/** @} */
-
-#endif
-
-#define FUNC_PTR void *
-/**
- * \def unused
- * \brief Marking \a v as a unused parameter or value.
- */
-#define unused(v) \
- do { \
- (void)(v); \
- } while (0)
-
-/* Define RAMFUNC attribute */
-#if defined(__CC_ARM) /* Keil uVision 4 */
-# define RAMFUNC __attribute__((section(".ramfunc")))
-#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
-# define RAMFUNC __ramfunc
-#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
-# define RAMFUNC __attribute__((section(".ramfunc")))
-#endif
-
-/* Define OPTIMIZE_HIGH attribute */
-#if defined(__CC_ARM) /* Keil uVision 4 */
-# define OPTIMIZE_HIGH _Pragma("O3")
-#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
-# define OPTIMIZE_HIGH _Pragma("optimize=high")
-#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
-# define OPTIMIZE_HIGH __attribute__((optimize("s")))
-#endif
-// kmod #define PASS 0
-// kmod #define FAIL 1
-// kmod #define LOW 0
-// kmod #define HIGH 1
-
-typedef int8_t S8; //!< 8-bit signed integer.
-typedef uint8_t U8; //!< 8-bit unsigned integer.
-typedef int16_t S16; //!< 16-bit signed integer.
-typedef uint16_t U16; //!< 16-bit unsigned integer.
-typedef int32_t S32; //!< 32-bit signed integer.
-typedef uint32_t U32; //!< 32-bit unsigned integer.
-typedef int64_t S64; //!< 64-bit signed integer.
-typedef uint64_t U64; //!< 64-bit unsigned integer.
-typedef float F32; //!< 32-bit floating-point number.
-typedef double F64; //!< 64-bit floating-point number.
-
-#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
-#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
-
-#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
-#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
-#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
-#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
-#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
-#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
-#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
-#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
-#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
-#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
-
-#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
-#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
-#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
-#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
-#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
-#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
-#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
-#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
-#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
-#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
-#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
-#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
-#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
-#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
-#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
-#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
-#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
-#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
-#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
-#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
-#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
-#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
-#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
-#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
-#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
-#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
-
-#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
-#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
-#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
-#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
-#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
-#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
-#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
-#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
-
-#if defined(__ICCARM__)
-# define SHORTENUM __packed
-#elif defined(__GNUC__)
-# define SHORTENUM __attribute__((packed))
-#endif
-
-/* No operation */
-#if defined(__ICCARM__)
-# define nop() __no_operation()
-#elif defined(__GNUC__)
-# define nop() (__NOP())
-#endif
-
-#define FLASH_DECLARE(x) const x
-#define FLASH_EXTERN(x) extern const x
-#define PGM_READ_BYTE(x) *(x)
-#define PGM_READ_WORD(x) *(x)
-#define MEMCPY_ENDIAN memcpy
-#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
-
-/*Defines the Flash Storage for the request and response of MAC*/
-#define CMD_ID_OCTET (0)
-
-/* Converting of values from CPU endian to little endian. */
-#define CPU_ENDIAN_TO_LE16(x) (x)
-#define CPU_ENDIAN_TO_LE32(x) (x)
-#define CPU_ENDIAN_TO_LE64(x) (x)
-
-/* Converting of values from little endian to CPU endian. */
-#define LE16_TO_CPU_ENDIAN(x) (x)
-#define LE32_TO_CPU_ENDIAN(x) (x)
-#define LE64_TO_CPU_ENDIAN(x) (x)
-
-/* Converting of constants from little endian to CPU endian. */
-#define CLE16_TO_CPU_ENDIAN(x) (x)
-#define CLE32_TO_CPU_ENDIAN(x) (x)
-#define CLE64_TO_CPU_ENDIAN(x) (x)
-
-/* Converting of constants from CPU endian to little endian. */
-#define CCPU_ENDIAN_TO_LE16(x) (x)
-#define CCPU_ENDIAN_TO_LE32(x) (x)
-#define CCPU_ENDIAN_TO_LE64(x) (x)
-
-#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))
-#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))
-
-/**
- * @brief Converts a 64-Bit value into a 8 Byte array
- *
- * @param[in] value 64-Bit value
- * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) {
- uint8_t index = 0;
-
- while (index < 8) {
- data[index++] = value & 0xFF;
- value = value >> 8;
- }
-}
-
-/**
- * @brief Converts a 16-Bit value into a 2 Byte array
- *
- * @param[in] value 16-Bit value
- * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) {
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) {
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) {
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/*
- * @brief Converts a 2 Byte array into a 16-Bit value
- *
- * @param data Specifies the pointer to the 2 Byte array
- *
- * @return 16-Bit value
- * @ingroup apiPalApi
- */
-static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) {
- return (data[0] | ((uint16_t)data[1] << 8));
-}
-
-/* Converts a 4 Byte array into a 32-Bit value */
-static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) {
- union {
- uint32_t u32;
- uint8_t u8[4];
- } long_addr;
-
- uint8_t index;
-
- for (index = 0; index < 4; index++) {
- long_addr.u8[index] = *data++;
- }
-
- return long_addr.u32;
-}
-
-/**
- * @brief Converts a 8 Byte array into a 64-Bit value
- *
- * @param data Specifies the pointer to the 8 Byte array
- *
- * @return 64-Bit value
- * @ingroup apiPalApi
- */
-static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) {
- union {
- uint64_t u64;
- uint8_t u8[8];
- } long_addr;
-
- uint8_t index;
-
- for (index = 0; index < 8; index++) {
- long_addr.u8[index] = *data++;
- }
-
- return long_addr.u64;
-}
-
-/** @} */
-
-#endif /* UTILS_COMPILER_H_INCLUDED */
diff --git a/tmk_core/protocol/arm_atsam/usb/conf_usb.h b/tmk_core/protocol/arm_atsam/usb/conf_usb.h
deleted file mode 100644
index 50d189a2025f..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/conf_usb.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/**
- * \file
- *
- * \brief USB configuration file
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _CONF_USB_H_
-#define _CONF_USB_H_
-
-#include "compiler.h"
-#include "udi_device_conf.h"
-
-#define UDI_CDC_DEFAULT_RATE 115200
-#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1
-#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE
-#define UDI_CDC_DEFAULT_DATABITS 8
-
-//! Device definition (mandatory)
-#define USB_DEVICE_VENDOR_ID VENDOR_ID
-#define USB_DEVICE_PRODUCT_ID PRODUCT_ID
-#define USB_DEVICE_VERSION DEVICE_VER
-#define USB_DEVICE_POWER 500 // Consumption on Vbus line (mA)
-#define USB_DEVICE_ATTR (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_BUS_POWERED)
-// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED)
-// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED)
-// (USB_CONFIG_ATTR_SELF_POWERED)
-// (USB_CONFIG_ATTR_BUS_POWERED)
-
-//! USB Device string definitions (Optional)
-#define USB_DEVICE_MANUFACTURE_NAME MANUFACTURER
-#define USB_DEVICE_PRODUCT_NAME PRODUCT
-#define USB_DEVICE_SERIAL_NAME SERIAL_NUM
-
-// Comment out USB_DEVICE_SERIAL_USE_BOOTLOADER_SERIAL to prevent ROM lookup of factory programmed serial number
-#define USB_DEVICE_SERIAL_USE_BOOTLOADER_SERIAL
-
-/**
- * Device speeds support
- * @{
- */
-//! To define a Low speed device
-//#define USB_DEVICE_LOW_SPEED
-
-//! To authorize the High speed
-#if (UC3A3 || UC3A4)
-//#define USB_DEVICE_HS_SUPPORT
-#elif (SAM3XA || SAM3U)
-//#define USB_DEVICE_HS_SUPPORT
-#endif
-//@}
-
-/**
- * USB Device Callbacks definitions (Optional)
- * @{
- */
-#define UDC_VBUS_EVENT(b_vbus_high)
-#define UDC_SOF_EVENT() main_sof_action()
-#define UDC_SUSPEND_EVENT() main_suspend_action()
-#define UDC_RESUME_EVENT() main_resume_action()
-//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature
-#define UDC_REMOTEWAKEUP_ENABLE() main_remotewakeup_enable()
-#define UDC_REMOTEWAKEUP_DISABLE() main_remotewakeup_disable()
-//! When a extra string descriptor must be supported
-//! other than manufacturer, product and serial string
-// #define UDC_GET_EXTRA_STRING()
-//@}
-
-//@}
-
-/**
- * USB Interface Configuration
- * @{
- */
-/**
- * Configuration of HID Keyboard interface
- * @{
- */
-//! Interface callback definition
-#define UDI_HID_KBD_ENABLE_EXT() main_kbd_enable()
-#define UDI_HID_KBD_DISABLE_EXT() main_kbd_disable()
-//#define UDI_HID_KBD_CHANGE_LED(value) ui_kbd_led(value)
-
-#ifdef NKRO_ENABLE
-# define UDI_HID_NKRO_ENABLE_EXT() main_nkro_enable()
-# define UDI_HID_NKRO_DISABLE_EXT() main_nkro_disable()
-//#define UDI_HID_NKRO_CHANGE_LED(value) ui_kbd_led(value)
-#endif
-
-#ifdef EXTRAKEY_ENABLE
-# define UDI_HID_EXK_ENABLE_EXT() main_exk_enable()
-# define UDI_HID_EXK_DISABLE_EXT() main_exk_disable()
-#endif
-
-#ifdef CONSOLE_ENABLE
-# define UDI_HID_CON_ENABLE_EXT() main_con_enable()
-# define UDI_HID_CON_DISABLE_EXT() main_con_disable()
-#endif
-
-#ifdef MOUSE_ENABLE
-# define UDI_HID_MOU_ENABLE_EXT() main_mou_enable()
-# define UDI_HID_MOU_DISABLE_EXT() main_mou_disable()
-#endif
-
-#ifdef RAW_ENABLE
-# define UDI_HID_RAW_ENABLE_EXT() main_raw_enable()
-# define UDI_HID_RAW_DISABLE_EXT() main_raw_disable()
-# define UDI_HID_RAW_RECEIVE(buffer, len) main_raw_receive(buffer, len)
-#endif
-
-//@}
-//@}
-
-/**
- * USB Device Driver Configuration
- * @{
- */
-//@}
-
-//! The includes of classes and other headers must be done at the end of this file to avoid compile error
-#include "udi_hid_kbd_conf.h"
-#include "usb_main.h"
-#include "ui.h"
-
-#endif // _CONF_USB_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/main_usb.c b/tmk_core/protocol/arm_atsam/usb/main_usb.c
deleted file mode 100644
index ee6ed25b8573..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/main_usb.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "samd51j18a.h"
-#include "conf_usb.h"
-#include "udd.h"
-
-#ifdef RAW_ENABLE
-# include "raw_hid.h"
-#endif
-
-uint8_t keyboard_protocol = 1;
-
-void main_suspend_action(void) {
- ui_powerdown();
-}
-
-void main_resume_action(void) {
- ui_wakeup();
-}
-
-void main_sof_action(void) {
- ui_process(udd_get_frame_number());
-}
-
-void main_remotewakeup_enable(void) {
- ui_wakeup_enable();
-}
-
-void main_remotewakeup_disable(void) {
- ui_wakeup_disable();
-}
-
-volatile bool main_b_kbd_enable = false;
-bool main_kbd_enable(void) {
- main_b_kbd_enable = true;
- return true;
-}
-
-void main_kbd_disable(void) {
- main_b_kbd_enable = false;
-}
-
-#ifdef NKRO_ENABLE
-volatile bool main_b_nkro_enable = false;
-bool main_nkro_enable(void) {
- main_b_nkro_enable = true;
- return true;
-}
-
-void main_nkro_disable(void) {
- main_b_nkro_enable = false;
-}
-#endif
-
-#ifdef EXTRAKEY_ENABLE
-volatile bool main_b_exk_enable = false;
-bool main_exk_enable(void) {
- main_b_exk_enable = true;
- return true;
-}
-
-void main_exk_disable(void) {
- main_b_exk_enable = false;
-}
-#endif
-
-#ifdef CONSOLE_ENABLE
-volatile bool main_b_con_enable = false;
-bool main_con_enable(void) {
- main_b_con_enable = true;
- return true;
-}
-
-void main_con_disable(void) {
- main_b_con_enable = false;
-}
-#endif
-
-#ifdef MOUSE_ENABLE
-volatile bool main_b_mou_enable = false;
-bool main_mou_enable(void) {
- main_b_mou_enable = true;
- return true;
-}
-
-void main_mou_disable(void) {
- main_b_mou_enable = false;
-}
-#endif
-
-#ifdef RAW_ENABLE
-volatile bool main_b_raw_enable = false;
-bool main_raw_enable(void) {
- main_b_raw_enable = true;
- return true;
-}
-
-void main_raw_disable(void) {
- main_b_raw_enable = false;
-}
-
-void main_raw_receive(uint8_t *buffer, uint8_t len) {
- raw_hid_receive(buffer, len);
-}
-#endif
diff --git a/tmk_core/protocol/arm_atsam/usb/status_codes.h b/tmk_core/protocol/arm_atsam/usb/status_codes.h
deleted file mode 100644
index 72819a0d7d2f..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/status_codes.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
- * \file
- *
- * \brief Status code definitions.
- *
- * This file defines various status codes returned by functions,
- * indicating success or failure as well as what kind of failure.
- *
- * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef STATUS_CODES_H_INCLUDED
-#define STATUS_CODES_H_INCLUDED
-
-#include
-
-/**
- * \defgroup group_sam0_utils_status_codes Status Codes
- *
- * \ingroup group_sam0_utils
- *
- * @{
- */
-
-/** Mask to retrieve the error category of a status code. */
-#define STATUS_CATEGORY_MASK 0xF0
-
-/** Mask to retrieve the error code within the category of a status code. */
-#define STATUS_ERROR_MASK 0x0F
-
-/** Status code error categories. */
-enum status_categories {
- STATUS_CATEGORY_OK = 0x00,
- STATUS_CATEGORY_COMMON = 0x10,
- STATUS_CATEGORY_ANALOG = 0x30,
- STATUS_CATEGORY_COM = 0x40,
- STATUS_CATEGORY_IO = 0x50,
-};
-
-/**
- * Status code that may be returned by shell commands and protocol
- * implementations.
- *
- * \note Any change to these status codes and the corresponding
- * message strings is strictly forbidden. New codes can be added,
- * however, but make sure that any message string tables are updated
- * at the same time.
- */
-enum status_code {
- STATUS_OK = STATUS_CATEGORY_OK | 0x00,
- STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01,
- STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02,
- STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04,
- STATUS_BUSY = STATUS_CATEGORY_OK | 0x05,
- STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06,
-
- STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00,
- STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01,
- STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02,
- STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03,
- STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04,
- STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05,
- STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06,
- STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07,
- STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08,
- STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A,
- STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B,
- STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c,
- STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d,
- STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e,
- STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f,
-
- STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
- STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
-
- STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00,
- STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01,
- STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02,
-
- STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00,
-};
-typedef enum status_code status_code_genare_t;
-
-/**
- Status codes used by MAC stack.
- */
-enum status_code_wireless {
- // STATUS_OK = 0, //!< Success
- ERR_IO_ERROR = -1, //!< I/O error
- ERR_FLUSHED = -2, //!< Request flushed from queue
- ERR_TIMEOUT = -3, //!< Operation timed out
- ERR_BAD_DATA = -4, //!< Data integrity check failed
- ERR_PROTOCOL = -5, //!< Protocol error
- ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
- ERR_NO_MEMORY = -7, //!< Insufficient memory
- ERR_INVALID_ARG = -8, //!< Invalid argument
- ERR_BAD_ADDRESS = -9, //!< Bad address
- ERR_BUSY = -10, //!< Resource is busy
- ERR_BAD_FORMAT = -11, //!< Data format not recognized
- ERR_NO_TIMER = -12, //!< No timer available
- ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
- ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
-
- /**
- * \brief Operation in progress
- *
- * This status code is for driver-internal use when an operation
- * is currently being performed.
- *
- * \note Drivers should never return this status code to any
- * callers. It is strictly for internal use.
- */
- OPERATION_IN_PROGRESS = -128,
-};
-
-typedef enum status_code_wireless status_code_t;
-
-/** @} */
-
-#endif /* STATUS_CODES_H_INCLUDED */
diff --git a/tmk_core/protocol/arm_atsam/usb/udc.c b/tmk_core/protocol/arm_atsam/usb/udc.c
deleted file mode 100644
index 2a371c200af1..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udc.c
+++ /dev/null
@@ -1,1072 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device Controller (UDC)
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "udd.h"
-#include "udc_desc.h"
-#include "udi_device_conf.h"
-#include "udi.h"
-#include "udc.h"
-
-#define BOOTLOADER_SERIAL_MAX_SIZE 20 // DO NOT MODIFY!
-
-/**
- * \ingroup udc_group
- * \defgroup udc_group_interne Implementation of UDC
- *
- * Internal implementation
- * @{
- */
-
-//! \name Internal variables to manage the USB device
-//! @{
-
-//! Device status state (see enum usb_device_status in usb_protocol.h)
-static le16_t udc_device_status;
-
-COMPILER_WORD_ALIGNED
-//! Device interface setting value
-static uint8_t udc_iface_setting = 0;
-
-//! Device Configuration number selected by the USB host
-COMPILER_WORD_ALIGNED
-static uint8_t udc_num_configuration = 0;
-
-//! Pointer on the selected speed device configuration
-static udc_config_speed_t UDC_DESC_STORAGE *udc_ptr_conf;
-
-//! Pointer on interface descriptor used by SETUP request.
-static usb_iface_desc_t UDC_DESC_STORAGE *udc_ptr_iface;
-
-//! @}
-
-//! \name Internal structure to store the USB device main strings
-//! @{
-
-/**
- * \brief Language ID of USB device (US ID by default)
- */
-COMPILER_WORD_ALIGNED
-static UDC_DESC_STORAGE usb_str_lgid_desc_t udc_string_desc_languageid = {.desc.bLength = sizeof(usb_str_lgid_desc_t), .desc.bDescriptorType = USB_DT_STRING, .string = {LE16(USB_LANGID_EN_US)}};
-
-/**
- * \brief USB device manufacture name storage
- * String is allocated only if USB_DEVICE_MANUFACTURE_NAME is declared
- * by usb application configuration
- */
-#ifdef USB_DEVICE_MANUFACTURE_NAME
-static uint8_t udc_string_manufacturer_name[] = USB_DEVICE_MANUFACTURE_NAME;
-# define USB_DEVICE_MANUFACTURE_NAME_SIZE (sizeof(udc_string_manufacturer_name) - 1)
-#else
-# define USB_DEVICE_MANUFACTURE_NAME_SIZE 0
-#endif
-
-/**
- * \brief USB device product name storage
- * String is allocated only if USB_DEVICE_PRODUCT_NAME is declared
- * by usb application configuration
- */
-#ifdef USB_DEVICE_PRODUCT_NAME
-static uint8_t udc_string_product_name[] = USB_DEVICE_PRODUCT_NAME;
-# define USB_DEVICE_PRODUCT_NAME_SIZE (sizeof(udc_string_product_name) - 1)
-#else
-# define USB_DEVICE_PRODUCT_NAME_SIZE 0
-#endif
-
-#if defined USB_DEVICE_SERIAL_NAME
-# define USB_DEVICE_SERIAL_NAME_SIZE (sizeof(USB_DEVICE_SERIAL_NAME) - 1)
-#else
-# define USB_DEVICE_SERIAL_NAME_SIZE 0
-#endif
-
-extern uint32_t _srom;
-
-uint8_t usb_device_serial_name_size = 0;
-#if defined USB_DEVICE_SERIAL_USE_BOOTLOADER_SERIAL
-uint8_t bootloader_serial_number[BOOTLOADER_SERIAL_MAX_SIZE + 1] = "";
-#endif
-static const uint8_t *udc_get_string_serial_name(void) {
-#if defined USB_DEVICE_SERIAL_USE_BOOTLOADER_SERIAL
- uint32_t serial_ptrloc = (uint32_t)&_srom - 4;
- uint32_t serial_address = *(uint32_t *)serial_ptrloc; // Address of bootloader's serial number if available
-
- if (serial_address != 0xFFFFFFFF && serial_address < serial_ptrloc) // Check for factory programmed serial address
- {
- if ((serial_address & 0xFF) % 4 == 0) // Check alignment
- {
- uint16_t *serial_use = (uint16_t *)(serial_address); // Point to address of string in rom
- uint8_t serial_length = 0;
-
- while ((*(serial_use + serial_length) > 32 && *(serial_use + serial_length) < 127) && serial_length < BOOTLOADER_SERIAL_MAX_SIZE) {
- bootloader_serial_number[serial_length] = *(serial_use + serial_length) & 0xFF;
- serial_length++;
- }
- bootloader_serial_number[serial_length] = 0;
-
- usb_device_serial_name_size = serial_length;
-
- return bootloader_serial_number; // Use serial programmed into bootloader rom
- }
- }
-#endif
-
- usb_device_serial_name_size = USB_DEVICE_SERIAL_NAME_SIZE;
-
-#if defined USB_DEVICE_SERIAL_NAME
- return (const uint8_t *)USB_DEVICE_SERIAL_NAME; // Use serial supplied by keyboard's config.h
-#else
- return 0; // No serial supplied
-#endif
-}
-
-/**
- * \brief USB device string descriptor
- * Structure used to transfer ASCII strings to USB String descriptor structure.
- */
-#ifndef BOOTLOADER_SERIAL_MAX_SIZE
-# define BOOTLOADER_SERIAL_MAX_SIZE 0
-#endif // BOOTLOADER_SERIAL_MAX_SIZE
-struct udc_string_desc_t {
- usb_str_desc_t header;
- le16_t string[Max(Max(Max(USB_DEVICE_MANUFACTURE_NAME_SIZE, USB_DEVICE_PRODUCT_NAME_SIZE), USB_DEVICE_SERIAL_NAME_SIZE), BOOTLOADER_SERIAL_MAX_SIZE)];
-};
-COMPILER_WORD_ALIGNED
-static UDC_DESC_STORAGE struct udc_string_desc_t udc_string_desc = {.header.bDescriptorType = USB_DT_STRING};
-//! @}
-
-usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void) {
- return udc_ptr_iface;
-}
-
-/**
- * \brief Returns a value to check the end of USB Configuration descriptor
- *
- * \return address after the last byte of USB Configuration descriptor
- */
-static usb_conf_desc_t UDC_DESC_STORAGE *udc_get_eof_conf(void) {
- return (UDC_DESC_STORAGE usb_conf_desc_t *)((uint8_t *)udc_ptr_conf->desc + le16_to_cpu(udc_ptr_conf->desc->wTotalLength));
-}
-
-#if (0 != USB_DEVICE_MAX_EP)
-/**
- * \brief Search specific descriptor in global interface descriptor
- *
- * \param desc Address of interface descriptor
- * or previous specific descriptor found
- * \param desc_id Descriptor ID to search
- *
- * \return address of specific descriptor found
- * \return NULL if it is the end of global interface descriptor
- */
-static usb_conf_desc_t UDC_DESC_STORAGE *udc_next_desc_in_iface(usb_conf_desc_t UDC_DESC_STORAGE *desc, uint8_t desc_id) {
- usb_conf_desc_t UDC_DESC_STORAGE *ptr_eof_desc;
-
- ptr_eof_desc = udc_get_eof_conf();
- // Go to next descriptor
- desc = (UDC_DESC_STORAGE usb_conf_desc_t *)((uint8_t *)desc + desc->bLength);
- // Check the end of configuration descriptor
- while (ptr_eof_desc > desc) {
- // If new interface descriptor is found,
- // then it is the end of the current global interface descriptor
- if (USB_DT_INTERFACE == desc->bDescriptorType) {
- break; // End of global interface descriptor
- }
- if (desc_id == desc->bDescriptorType) {
- return desc; // Specific descriptor found
- }
- // Go to next descriptor
- desc = (UDC_DESC_STORAGE usb_conf_desc_t *)((uint8_t *)desc + desc->bLength);
- }
- return NULL; // No specific descriptor found
-}
-#endif
-
-/**
- * \brief Search an interface descriptor
- * This routine updates the internal pointer udc_ptr_iface.
- *
- * \param iface_num Interface number to find in Configuration Descriptor
- * \param setting_num Setting number of interface to find
- *
- * \return 1 if found or 0 if not found
- */
-static bool udc_update_iface_desc(uint8_t iface_num, uint8_t setting_num) {
- usb_conf_desc_t UDC_DESC_STORAGE *ptr_end_desc;
-
- if (0 == udc_num_configuration) {
- return false;
- }
-
- if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) {
- return false;
- }
-
- // Start at the beginning of configuration descriptor
- udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *)udc_ptr_conf->desc;
-
- // Check the end of configuration descriptor
- ptr_end_desc = udc_get_eof_conf();
- while (ptr_end_desc > (UDC_DESC_STORAGE usb_conf_desc_t *)udc_ptr_iface) {
- if (USB_DT_INTERFACE == udc_ptr_iface->bDescriptorType) {
- // A interface descriptor is found
- // Check interface and alternate setting number
- if ((iface_num == udc_ptr_iface->bInterfaceNumber) && (setting_num == udc_ptr_iface->bAlternateSetting)) {
- return true; // Interface found
- }
- }
- // Go to next descriptor
- udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *)((uint8_t *)udc_ptr_iface + udc_ptr_iface->bLength);
- }
- return false; // Interface not found
-}
-
-/**
- * \brief Disables an usb device interface (UDI)
- * This routine call the UDI corresponding to interface number
- *
- * \param iface_num Interface number to disable
- *
- * \return 1 if it is done or 0 if interface is not found
- */
-static bool udc_iface_disable(uint8_t iface_num) {
- udi_api_t UDC_DESC_STORAGE *udi_api;
-
- // Select first alternate setting of the interface
- // to update udc_ptr_iface before call iface->getsetting()
- if (!udc_update_iface_desc(iface_num, 0)) {
- return false;
- }
-
- // Select the interface with the current alternate setting
- udi_api = udc_ptr_conf->udi_apis[iface_num];
-
-#if (0 != USB_DEVICE_MAX_EP)
- if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) {
- return false;
- }
-
- // Start at the beginning of interface descriptor
- {
- usb_ep_desc_t UDC_DESC_STORAGE *ep_desc;
- ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *)udc_ptr_iface;
- while (1) {
- // Search Endpoint descriptor included in global interface descriptor
- ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *)udc_next_desc_in_iface((UDC_DESC_STORAGE usb_conf_desc_t *)ep_desc, USB_DT_ENDPOINT);
- if (NULL == ep_desc) {
- break;
- }
- // Free the endpoint used by the interface
- udd_ep_free(ep_desc->bEndpointAddress);
- }
- }
-#endif
-
- // Disable interface
- udi_api->disable();
- return true;
-}
-
-/**
- * \brief Enables an usb device interface (UDI)
- * This routine calls the UDI corresponding
- * to the interface and setting number.
- *
- * \param iface_num Interface number to enable
- * \param setting_num Setting number to enable
- *
- * \return 1 if it is done or 0 if interface is not found
- */
-static bool udc_iface_enable(uint8_t iface_num, uint8_t setting_num) {
- // Select the interface descriptor
- if (!udc_update_iface_desc(iface_num, setting_num)) {
- return false;
- }
-
-#if (0 != USB_DEVICE_MAX_EP)
- usb_ep_desc_t UDC_DESC_STORAGE *ep_desc;
-
- // Start at the beginning of the global interface descriptor
- ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *)udc_ptr_iface;
- while (1) {
- // Search Endpoint descriptor included in the global interface descriptor
- ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *)udc_next_desc_in_iface((UDC_DESC_STORAGE usb_conf_desc_t *)ep_desc, USB_DT_ENDPOINT);
- if (NULL == ep_desc) break;
- // Alloc the endpoint used by the interface
- if (!udd_ep_alloc(ep_desc->bEndpointAddress, ep_desc->bmAttributes, le16_to_cpu(ep_desc->wMaxPacketSize))) {
- return false;
- }
- }
-#endif
- // Enable the interface
- return udc_ptr_conf->udi_apis[iface_num]->enable();
-}
-
-/*! \brief Start the USB Device stack
- */
-void udc_start(void) {
- udd_enable();
-}
-
-/*! \brief Stop the USB Device stack
- */
-void udc_stop(void) {
- udd_disable();
- udc_reset();
-}
-
-/**
- * \brief Reset the current configuration of the USB device,
- * This routines can be called by UDD when a RESET on the USB line occurs.
- */
-void udc_reset(void) {
- uint8_t iface_num;
-
- if (udc_num_configuration) {
- for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; iface_num++) {
- udc_iface_disable(iface_num);
- }
- }
- udc_num_configuration = 0;
-#if (USB_CONFIG_ATTR_REMOTE_WAKEUP == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP))
- if (CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP) & udc_device_status) {
- // Remote wakeup is enabled then disable it
- UDC_REMOTEWAKEUP_DISABLE();
- }
-#endif
- udc_device_status =
-#if (USB_DEVICE_ATTR & USB_CONFIG_ATTR_SELF_POWERED)
- CPU_TO_LE16(USB_DEV_STATUS_SELF_POWERED);
-#else
- CPU_TO_LE16(USB_DEV_STATUS_BUS_POWERED);
-#endif
-}
-
-void udc_sof_notify(void) {
- uint8_t iface_num;
-
- if (udc_num_configuration) {
- for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; iface_num++) {
- if (udc_ptr_conf->udi_apis[iface_num]->sof_notify != NULL) {
- udc_ptr_conf->udi_apis[iface_num]->sof_notify();
- }
- }
- }
-}
-
-/**
- * \brief Standard device request to get device status
- *
- * \return true if success
- */
-static bool udc_req_std_dev_get_status(void) {
- if (udd_g_ctrlreq.req.wLength != sizeof(udc_device_status)) {
- return false;
- }
-
- udd_set_setup_payload((uint8_t *)&udc_device_status, sizeof(udc_device_status));
- return true;
-}
-
-#if (0 != USB_DEVICE_MAX_EP)
-/**
- * \brief Standard endpoint request to get endpoint status
- *
- * \return true if success
- */
-static bool udc_req_std_ep_get_status(void) {
- static le16_t udc_ep_status;
-
- if (udd_g_ctrlreq.req.wLength != sizeof(udc_ep_status)) {
- return false;
- }
-
- udc_ep_status = udd_ep_is_halted(udd_g_ctrlreq.req.wIndex & 0xFF) ? CPU_TO_LE16(USB_EP_STATUS_HALTED) : 0;
-
- udd_set_setup_payload((uint8_t *)&udc_ep_status, sizeof(udc_ep_status));
- return true;
-}
-#endif
-
-/**
- * \brief Standard device request to change device status
- *
- * \return true if success
- */
-static bool udc_req_std_dev_clear_feature(void) {
- if (udd_g_ctrlreq.req.wLength) {
- return false;
- }
-
- if (udd_g_ctrlreq.req.wValue == USB_DEV_FEATURE_REMOTE_WAKEUP) {
- udc_device_status &= CPU_TO_LE16(~(uint32_t)USB_DEV_STATUS_REMOTEWAKEUP);
-#if (USB_CONFIG_ATTR_REMOTE_WAKEUP == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP))
- UDC_REMOTEWAKEUP_DISABLE();
-#endif
- return true;
- }
- return false;
-}
-
-#if (0 != USB_DEVICE_MAX_EP)
-/**
- * \brief Standard endpoint request to clear endpoint feature
- *
- * \return true if success
- */
-static bool udc_req_std_ep_clear_feature(void) {
- if (udd_g_ctrlreq.req.wLength) {
- return false;
- }
-
- if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) {
- return udd_ep_clear_halt(udd_g_ctrlreq.req.wIndex & 0xFF);
- }
- return false;
-}
-#endif
-
-/**
- * \brief Standard device request to set a feature
- *
- * \return true if success
- */
-static bool udc_req_std_dev_set_feature(void) {
- if (udd_g_ctrlreq.req.wLength) {
- return false;
- }
-
- switch (udd_g_ctrlreq.req.wValue) {
- case USB_DEV_FEATURE_REMOTE_WAKEUP:
-#if (USB_CONFIG_ATTR_REMOTE_WAKEUP == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP))
- udc_device_status |= CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP);
- UDC_REMOTEWAKEUP_ENABLE();
- return true;
-#else
- return false;
-#endif
-
-#ifdef USB_DEVICE_HS_SUPPORT
- case USB_DEV_FEATURE_TEST_MODE:
- if (!udd_is_high_speed()) {
- break;
- }
- if (udd_g_ctrlreq.req.wIndex & 0xff) {
- break;
- }
- // Unconfigure the device, terminating all ongoing requests
- udc_reset();
- switch ((udd_g_ctrlreq.req.wIndex >> 8) & 0xFF) {
- case USB_DEV_TEST_MODE_J:
- udd_g_ctrlreq.callback = udd_test_mode_j;
- return true;
-
- case USB_DEV_TEST_MODE_K:
- udd_g_ctrlreq.callback = udd_test_mode_k;
- return true;
-
- case USB_DEV_TEST_MODE_SE0_NAK:
- udd_g_ctrlreq.callback = udd_test_mode_se0_nak;
- return true;
-
- case USB_DEV_TEST_MODE_PACKET:
- udd_g_ctrlreq.callback = udd_test_mode_packet;
- return true;
-
- case USB_DEV_TEST_MODE_FORCE_ENABLE: // Only for downstream facing hub ports
- default:
- break;
- }
- break;
-#endif
- default:
- break;
- }
- return false;
-}
-
-/**
- * \brief Standard endpoint request to halt an endpoint
- *
- * \return true if success
- */
-#if (0 != USB_DEVICE_MAX_EP)
-static bool udc_req_std_ep_set_feature(void) {
- if (udd_g_ctrlreq.req.wLength) {
- return false;
- }
- if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) {
- udd_ep_abort(udd_g_ctrlreq.req.wIndex & 0xFF);
- return udd_ep_set_halt(udd_g_ctrlreq.req.wIndex & 0xFF);
- }
- return false;
-}
-#endif
-
-/**
- * \brief Change the address of device
- * Callback called at the end of request set address
- */
-static void udc_valid_address(void) {
- udd_set_address(udd_g_ctrlreq.req.wValue & 0x7F);
-}
-
-/**
- * \brief Standard device request to set device address
- *
- * \return true if success
- */
-static bool udc_req_std_dev_set_address(void) {
- if (udd_g_ctrlreq.req.wLength) {
- return false;
- }
-
- // The address must be changed at the end of setup request after the handshake
- // then we use a callback to change address
- udd_g_ctrlreq.callback = udc_valid_address;
- return true;
-}
-
-/**
- * \brief Standard device request to get device string descriptor
- *
- * \return true if success
- */
-static bool udc_req_std_dev_get_str_desc(void) {
- uint8_t i;
- const uint8_t *str;
- uint8_t str_length = 0;
-
- // Link payload pointer to the string corresponding at request
- switch (udd_g_ctrlreq.req.wValue & 0xff) {
- case 0:
- udd_set_setup_payload((uint8_t *)&udc_string_desc_languageid, sizeof(udc_string_desc_languageid));
- break;
-
-#ifdef USB_DEVICE_MANUFACTURE_NAME
- case 1:
- str_length = USB_DEVICE_MANUFACTURE_NAME_SIZE;
- str = udc_string_manufacturer_name;
- break;
-#endif
-#ifdef USB_DEVICE_PRODUCT_NAME
- case 2:
- str_length = USB_DEVICE_PRODUCT_NAME_SIZE;
- str = udc_string_product_name;
- break;
-#endif
- case 3:
- str = udc_get_string_serial_name();
- str_length = usb_device_serial_name_size;
- break;
- default:
-#ifdef UDC_GET_EXTRA_STRING
- if (UDC_GET_EXTRA_STRING()) {
- break;
- }
-#endif
- return false;
- }
-
- if (str_length) {
- for (i = 0; i < str_length; i++) {
- udc_string_desc.string[i] = cpu_to_le16((le16_t)str[i]);
- }
-
- udc_string_desc.header.bLength = 2 + (str_length)*2;
- udd_set_setup_payload((uint8_t *)&udc_string_desc, udc_string_desc.header.bLength);
- }
-
- return true;
-}
-
-/**
- * \brief Standard device request to get descriptors about USB device
- *
- * \return true if success
- */
-static bool udc_req_std_dev_get_descriptor(void) {
- uint8_t conf_num;
-
- conf_num = udd_g_ctrlreq.req.wValue & 0xff;
-
- // Check descriptor ID
- switch ((uint8_t)(udd_g_ctrlreq.req.wValue >> 8)) {
- case USB_DT_DEVICE:
- // Device descriptor requested
-#ifdef USB_DEVICE_HS_SUPPORT
- if (!udd_is_high_speed()) {
- udd_set_setup_payload((uint8_t *)udc_config.confdev_hs, udc_config.confdev_hs->bLength);
- } else
-#endif
- {
- udd_set_setup_payload((uint8_t *)udc_config.confdev_lsfs, udc_config.confdev_lsfs->bLength);
- }
- break;
-
- case USB_DT_CONFIGURATION:
- // Configuration descriptor requested
-#ifdef USB_DEVICE_HS_SUPPORT
- if (udd_is_high_speed()) {
- // HS descriptor
- if (conf_num >= udc_config.confdev_hs->bNumConfigurations) {
- return false;
- }
- udd_set_setup_payload((uint8_t *)udc_config.conf_hs[conf_num].desc, le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength));
- } else
-#endif
- {
- // FS descriptor
- if (conf_num >= udc_config.confdev_lsfs->bNumConfigurations) {
- return false;
- }
- udd_set_setup_payload((uint8_t *)udc_config.conf_lsfs[conf_num].desc, le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength));
- }
- ((usb_conf_desc_t *)udd_g_ctrlreq.payload)->bDescriptorType = USB_DT_CONFIGURATION;
- break;
-
-#ifdef USB_DEVICE_HS_SUPPORT
- case USB_DT_DEVICE_QUALIFIER:
- // Device qualifier descriptor requested
- udd_set_setup_payload((uint8_t *)udc_config.qualifier, udc_config.qualifier->bLength);
- break;
-
- case USB_DT_OTHER_SPEED_CONFIGURATION:
- // Other configuration descriptor requested
- if (!udd_is_high_speed()) {
- // HS descriptor
- if (conf_num >= udc_config.confdev_hs->bNumConfigurations) {
- return false;
- }
- udd_set_setup_payload((uint8_t *)udc_config.conf_hs[conf_num].desc, le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength));
- } else {
- // FS descriptor
- if (conf_num >= udc_config.confdev_lsfs->bNumConfigurations) {
- return false;
- }
- udd_set_setup_payload((uint8_t *)udc_config.conf_lsfs[conf_num].desc, le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength));
- }
- ((usb_conf_desc_t *)udd_g_ctrlreq.payload)->bDescriptorType = USB_DT_OTHER_SPEED_CONFIGURATION;
- break;
-#endif
-
- case USB_DT_BOS:
- // Device BOS descriptor requested
- if (udc_config.conf_bos == NULL) {
- return false;
- }
- udd_set_setup_payload((uint8_t *)udc_config.conf_bos, udc_config.conf_bos->wTotalLength);
- break;
-
- case USB_DT_STRING:
- // String descriptor requested
- if (!udc_req_std_dev_get_str_desc()) {
- return false;
- }
- break;
-
- default:
- // Unknown descriptor requested
- return false;
- }
- // if the descriptor is larger than length requested, then reduce it
- if (udd_g_ctrlreq.req.wLength < udd_g_ctrlreq.payload_size) {
- udd_g_ctrlreq.payload_size = udd_g_ctrlreq.req.wLength;
- }
- return true;
-}
-
-/**
- * \brief Standard device request to get configuration number
- *
- * \return true if success
- */
-static bool udc_req_std_dev_get_configuration(void) {
- if (udd_g_ctrlreq.req.wLength != 1) {
- return false;
- }
-
- udd_set_setup_payload(&udc_num_configuration, 1);
- return true;
-}
-
-/**
- * \brief Standard device request to enable a configuration
- *
- * \return true if success
- */
-static bool udc_req_std_dev_set_configuration(void) {
- uint8_t iface_num;
-
- // Check request length
- if (udd_g_ctrlreq.req.wLength) {
- return false;
- }
- // Authorize configuration only if the address is valid
- if (!udd_getaddress()) {
- return false;
- }
- // Check the configuration number requested
-#ifdef USB_DEVICE_HS_SUPPORT
- if (udd_is_high_speed()) {
- // HS descriptor
- if ((udd_g_ctrlreq.req.wValue & 0xFF) > udc_config.confdev_hs->bNumConfigurations) {
- return false;
- }
- } else
-#endif
- {
- // FS descriptor
- if ((udd_g_ctrlreq.req.wValue & 0xFF) > udc_config.confdev_lsfs->bNumConfigurations) {
- return false;
- }
- }
-
- // Reset current configuration
- udc_reset();
-
- // Enable new configuration
- udc_num_configuration = udd_g_ctrlreq.req.wValue & 0xFF;
- if (udc_num_configuration == 0) {
- return true; // Default empty configuration requested
- }
- // Update pointer of the configuration descriptor
-#ifdef USB_DEVICE_HS_SUPPORT
- if (udd_is_high_speed()) {
- // HS descriptor
- udc_ptr_conf = &udc_config.conf_hs[udc_num_configuration - 1];
- } else
-#endif
- {
- // FS descriptor
- udc_ptr_conf = &udc_config.conf_lsfs[udc_num_configuration - 1];
- }
- // Enable all interfaces of the selected configuration
- for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; iface_num++) {
- if (!udc_iface_enable(iface_num, 0)) {
- return false;
- }
- }
- return true;
-}
-
-/**
- * \brief Standard interface request
- * to get the alternate setting number of an interface
- *
- * \return true if success
- */
-static bool udc_req_std_iface_get_setting(void) {
- uint8_t iface_num;
- udi_api_t UDC_DESC_STORAGE *udi_api;
-
- if (udd_g_ctrlreq.req.wLength != 1) {
- return false; // Error in request
- }
- if (!udc_num_configuration) {
- return false; // The device is not is configured state yet
- }
-
- // Check the interface number included in the request
- iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
- if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) {
- return false;
- }
-
- // Select first alternate setting of the interface to update udc_ptr_iface
- // before call iface->getsetting()
- if (!udc_update_iface_desc(iface_num, 0)) {
- return false;
- }
- // Get alternate setting from UDI
- udi_api = udc_ptr_conf->udi_apis[iface_num];
- udc_iface_setting = udi_api->getsetting();
-
- // Link value to payload pointer of request
- udd_set_setup_payload(&udc_iface_setting, 1);
- return true;
-}
-
-/**
- * \brief Standard interface request
- * to set an alternate setting of an interface
- *
- * \return true if success
- */
-static bool udc_req_std_iface_set_setting(void) {
- uint8_t iface_num, setting_num;
-
- if (udd_g_ctrlreq.req.wLength) {
- return false; // Error in request
- }
- if (!udc_num_configuration) {
- return false; // The device is not is configured state yet
- }
-
- iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
- setting_num = udd_g_ctrlreq.req.wValue & 0xFF;
-
- // Disable current setting
- if (!udc_iface_disable(iface_num)) {
- return false;
- }
-
- // Enable new setting
- return udc_iface_enable(iface_num, setting_num);
-}
-
-/**
- * \brief Main routine to manage the standard USB SETUP request
- *
- * \return true if the request is supported
- */
-static bool udc_reqstd(void) {
- if (Udd_setup_is_in()) {
- // GET Standard Requests
- if (udd_g_ctrlreq.req.wLength == 0) {
- return false; // Error for USB host
- }
-
- if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) {
- // Standard Get Device request
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_GET_STATUS:
- return udc_req_std_dev_get_status();
- case USB_REQ_GET_DESCRIPTOR:
- return udc_req_std_dev_get_descriptor();
- case USB_REQ_GET_CONFIGURATION:
- return udc_req_std_dev_get_configuration();
- default:
- break;
- }
- }
-
- if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) {
- // Standard Get Interface request
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_GET_INTERFACE:
- return udc_req_std_iface_get_setting();
- default:
- break;
- }
- }
-#if (0 != USB_DEVICE_MAX_EP)
- if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) {
- // Standard Get Endpoint request
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_GET_STATUS:
- return udc_req_std_ep_get_status();
- default:
- break;
- }
- }
-#endif
- } else {
- // SET Standard Requests
- if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) {
- // Standard Set Device request
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_SET_ADDRESS:
- return udc_req_std_dev_set_address();
- case USB_REQ_CLEAR_FEATURE:
- return udc_req_std_dev_clear_feature();
- case USB_REQ_SET_FEATURE:
- return udc_req_std_dev_set_feature();
- case USB_REQ_SET_CONFIGURATION:
- return udc_req_std_dev_set_configuration();
- case USB_REQ_SET_DESCRIPTOR:
- /* Not supported (defined as optional by the USB 2.0 spec) */
- break;
- default:
- break;
- }
- }
-
- if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) {
- // Standard Set Interface request
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_SET_INTERFACE:
- return udc_req_std_iface_set_setting();
- default:
- break;
- }
- }
-#if (0 != USB_DEVICE_MAX_EP)
- if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) {
- // Standard Set Endpoint request
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_CLEAR_FEATURE:
- return udc_req_std_ep_clear_feature();
- case USB_REQ_SET_FEATURE:
- return udc_req_std_ep_set_feature();
- default:
- break;
- }
- }
-#endif
- }
- return false;
-}
-
-/**
- * \brief Send the SETUP interface request to UDI
- *
- * \return true if the request is supported
- */
-static bool udc_req_iface(void) {
- uint8_t iface_num;
- udi_api_t UDC_DESC_STORAGE *udi_api;
-
- if (0 == udc_num_configuration) {
- return false; // The device is not is configured state yet
- }
- // Check interface number
- iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
- if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) {
- return false;
- }
-
- //* To update udc_ptr_iface with the selected interface in request
- // Select first alternate setting of interface to update udc_ptr_iface
- // before calling udi_api->getsetting()
- if (!udc_update_iface_desc(iface_num, 0)) {
- return false;
- }
- // Select the interface with the current alternate setting
- udi_api = udc_ptr_conf->udi_apis[iface_num];
- if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) {
- return false;
- }
-
- // Send the SETUP request to the UDI corresponding to the interface number
- return udi_api->setup();
-}
-
-/**
- * \brief Send the SETUP interface request to UDI
- *
- * \return true if the request is supported
- */
-static bool udc_req_ep(void) {
- uint8_t iface_num;
- udi_api_t UDC_DESC_STORAGE *udi_api;
-
- if (0 == udc_num_configuration) {
- return false; // The device is not is configured state yet
- }
- // Send this request on all enabled interfaces
- iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
- for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; iface_num++) {
- // Select the interface with the current alternate setting
- udi_api = udc_ptr_conf->udi_apis[iface_num];
- if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) {
- return false;
- }
-
- // Send the SETUP request to the UDI
- if (udi_api->setup()) {
- return true;
- }
- }
- return false;
-}
-
-/**
- * \brief Main routine to manage the USB SETUP request.
- *
- * This function parses a USB SETUP request and submits an appropriate
- * response back to the host or, in the case of SETUP OUT requests
- * with data, sets up a buffer for receiving the data payload.
- *
- * The main standard requests defined by the USB 2.0 standard are handled
- * internally. The interface requests are sent to UDI, and the specific request
- * sent to a specific application callback.
- *
- * \return true if the request is supported, else the request is stalled by UDD
- */
-bool udc_process_setup(void) {
- // By default no data (receive/send) and no callbacks registered
- udd_g_ctrlreq.payload_size = 0;
- udd_g_ctrlreq.callback = NULL;
- udd_g_ctrlreq.over_under_run = NULL;
-
- if (Udd_setup_is_in()) {
- if (udd_g_ctrlreq.req.wLength == 0) {
- return false; // Error from USB host
- }
- }
-
- // If standard request then try to decode it in UDC
- if (Udd_setup_type() == USB_REQ_TYPE_STANDARD) {
- if (udc_reqstd()) {
- return true;
- }
- }
-
- // If interface request then try to decode it in UDI
- if (Udd_setup_recipient() == USB_REQ_RECIP_INTERFACE) {
- if (udc_req_iface()) {
- return true;
- }
- }
-
- // If endpoint request then try to decode it in UDI
- if (Udd_setup_recipient() == USB_REQ_RECIP_ENDPOINT) {
- if (udc_req_ep()) {
- return true;
- }
- }
-
- // Here SETUP request unknown by UDC and UDIs
-#ifdef USB_DEVICE_SPECIFIC_REQUEST
- // Try to decode it in specific callback
- return USB_DEVICE_SPECIFIC_REQUEST(); // Ex: Vendor request,...
-#else
- return false;
-#endif
-}
-
-//! @}
diff --git a/tmk_core/protocol/arm_atsam/usb/udc.h b/tmk_core/protocol/arm_atsam/usb/udc.h
deleted file mode 100644
index f2144059eb5a..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udc.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/**
- * \file
- *
- * \brief Interface of the USB Device Controller (UDC)
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDC_H_
-#define _UDC_H_
-
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "udc_desc.h"
-#include "udd.h"
-
-#if USB_DEVICE_VENDOR_ID == 0
-# error USB_DEVICE_VENDOR_ID cannot be equal to 0
-#endif
-
-#if USB_DEVICE_PRODUCT_ID == 0
-# error USB_DEVICE_PRODUCT_ID cannot be equal to 0
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \ingroup usb_device_group
- * \defgroup udc_group USB Device Controller (UDC)
- *
- * The UDC provides a high-level abstraction of the usb device.
- * You can use these functions to control the main device state
- * (start/attach/wakeup).
- *
- * \section USB_DEVICE_CONF USB Device Custom configuration
- * The following USB Device configuration must be included in the conf_usb.h
- * file of the application.
- *
- * USB_DEVICE_VENDOR_ID (Word)
- * Vendor ID provided by USB org (ATMEL 0x03EB).
- *
- * USB_DEVICE_PRODUCT_ID (Word)
- * Product ID (Referenced in usb_atmel.h).
- *
- * USB_DEVICE_MAJOR_VERSION (Byte)
- * Major version of the device
- *
- * USB_DEVICE_MINOR_VERSION (Byte)
- * Minor version of the device
- *
- * USB_DEVICE_MANUFACTURE_NAME (string)
- * ASCII name for the manufacture
- *
- * USB_DEVICE_PRODUCT_NAME (string)
- * ASCII name for the product
- *
- * USB_DEVICE_SERIAL_NAME (string)
- * ASCII name to enable and set a serial number
- *
- * USB_DEVICE_POWER (Numeric)
- * (unit mA) Maximum device power
- *
- * USB_DEVICE_ATTR (Byte)
- * USB attributes available:
- * - USB_CONFIG_ATTR_SELF_POWERED
- * - USB_CONFIG_ATTR_REMOTE_WAKEUP
- * Note: if remote wake enabled then defines remotewakeup callbacks,
- * see Table 5-2. External API from UDC - Callback
- *
- * USB_DEVICE_LOW_SPEED (Only defined)
- * Force the USB Device to run in low speed
- *
- * USB_DEVICE_HS_SUPPORT (Only defined)
- * Authorize the USB Device to run in high speed
- *
- * USB_DEVICE_MAX_EP (Byte)
- * Define the maximum endpoint number used by the USB Device.
- * This one is already defined in UDI default configuration.
- * Ex:
- * - When endpoint control 0x00, endpoint 0x01 and
- * endpoint 0x82 is used then USB_DEVICE_MAX_EP=2
- * - When only endpoint control 0x00 is used then USB_DEVICE_MAX_EP=0
- * - When endpoint 0x01 and endpoint 0x81 is used then USB_DEVICE_MAX_EP=1
- * (configuration not possible on USBB interface)
- * @{
- */
-
-/**
- * \brief Authorizes the VBUS event
- *
- * \return true, if the VBUS monitoring is possible.
- *
- * \section udc_vbus_monitoring VBus monitoring used cases
- *
- * The VBus monitoring is used only for USB SELF Power application.
- *
- * - By default the USB device is automatically attached when Vbus is high
- * or when USB is start for devices without internal Vbus monitoring.
- * conf_usb.h file does not contains define USB_DEVICE_ATTACH_AUTO_DISABLE.
- * \code //#define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
- *
- * - Add custom VBUS monitoring. conf_usb.h file contains define
- * USB_DEVICE_ATTACH_AUTO_DISABLE:
- * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
- * User C file contains:
- * \code
- // Authorize VBUS monitoring
- if (!udc_include_vbus_monitoring()) {
- // Implement custom VBUS monitoring via GPIO or other
- }
- Event_VBUS_present() // VBUS interrupt or GPIO interrupt or other
- {
- // Attach USB Device
- udc_attach();
- }
-\endcode
- *
- * - Case of battery charging. conf_usb.h file contains define
- * USB_DEVICE_ATTACH_AUTO_DISABLE:
- * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
- * User C file contains:
- * \code
- Event VBUS present() // VBUS interrupt or GPIO interrupt or ..
- {
- // Authorize battery charging, but wait key press to start USB.
- }
- Event Key press()
- {
- // Stop batteries charging
- // Start USB
- udc_attach();
- }
-\endcode
- */
-static inline bool udc_include_vbus_monitoring(void) {
- return udd_include_vbus_monitoring();
-}
-
-/*! \brief Start the USB Device stack
- */
-void udc_start(void);
-
-/*! \brief Stop the USB Device stack
- */
-void udc_stop(void);
-
-/**
- * \brief Attach device to the bus when possible
- *
- * \warning If a VBus control is included in driver,
- * then it will attach device when an acceptable Vbus
- * level from the host is detected.
- */
-static inline void udc_attach(void) {
- udd_attach();
-}
-
-/**
- * \brief Detaches the device from the bus
- *
- * The driver must remove pull-up on USB line D- or D+.
- */
-static inline void udc_detach(void) {
- udd_detach();
-}
-
-/*! \brief The USB driver sends a resume signal called \e "Upstream Resume"
- * This is authorized only when the remote wakeup feature is enabled by host.
- */
-inline void udc_remotewakeup(void) {
- udd_send_remotewakeup();
-}
-
-/**
- * \brief Returns a pointer on the current interface descriptor
- *
- * \return pointer on the current interface descriptor.
- */
-usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void);
-
-//@}
-
-/**
- * \ingroup usb_group
- * \defgroup usb_device_group USB Stack Device
- *
- * This module includes USB Stack Device implementation.
- * The stack is divided in three parts:
- * - USB Device Controller (UDC) provides USB chapter 9 compliance
- * - USB Device Interface (UDI) provides USB Class compliance
- * - USB Device Driver (UDD) provides USB Driver for each Atmel MCU
-
- * Many USB Device applications can be implemented on Atmel MCU.
- * Atmel provides many application notes for different applications:
- * - AVR4900, provides general information about Device Stack
- * - AVR4901, explains how to create a new class
- * - AVR4902, explains how to create a composite device
- * - AVR49xx, all device classes provided in ASF have an application note
- *
- * A basic USB knowledge is required to understand the USB Device
- * Class application notes (HID,MS,CDC,PHDC,...).
- * Then, to create an USB device with
- * only one class provided by ASF, refer directly to the application note
- * corresponding to this USB class. The USB Device application note for
- * New Class and Composite is dedicated to advanced USB users.
- *
- * @{
- */
-
-//! @}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _UDC_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udc_desc.h b/tmk_core/protocol/arm_atsam/usb/udc_desc.h
deleted file mode 100644
index 50861da96436..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udc_desc.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/**
- * \file
- *
- * \brief Common API for USB Device Interface
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDC_DESC_H_
-#define _UDC_DESC_H_
-
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "udi.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \ingroup udc_group
- * \defgroup udc_desc_group USB Device Descriptor
- *
- * @{
- */
-
-/**
- * \brief Defines the memory's location of USB descriptors
- *
- * By default the Descriptor is stored in RAM
- * (UDC_DESC_STORAGE is defined empty).
- *
- * If you have need to free RAM space,
- * it is possible to put descriptor in flash in following case:
- * - USB driver authorize flash transfer (USBB on UC3 and USB on Mega)
- * - USB Device is not high speed (UDC no need to change USB descriptors)
- *
- * For UC3 application used "const".
- *
- * For Mega application used "code".
- */
-#define UDC_DESC_STORAGE
-// Descriptor storage in internal RAM
-#if (defined UDC_DATA_USE_HRAM_SUPPORT)
-# if defined(__GNUC__)
-# define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0")))
-# define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0")))
-# elif defined(__ICCAVR32__)
-# define UDC_DATA(x) COMPILER_ALIGNED(x) __data32
-# define UDC_BSS(x) COMPILER_ALIGNED(x) __data32
-# endif
-#else
-# define UDC_DATA(x) COMPILER_ALIGNED(x)
-# define UDC_BSS(x) COMPILER_ALIGNED(x)
-#endif
-
-/**
- * \brief Configuration descriptor and UDI link for one USB speed
- */
-typedef struct {
- //! USB configuration descriptor
- usb_conf_desc_t UDC_DESC_STORAGE *desc;
- //! Array of UDI API pointer
- udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE *udi_apis;
-} udc_config_speed_t;
-
-/**
- * \brief All information about the USB Device
- */
-typedef struct {
- //! USB device descriptor for low or full speed
- usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs;
- //! USB configuration descriptor and UDI API pointers for low or full speed
- udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs;
-#ifdef USB_DEVICE_HS_SUPPORT
- //! USB device descriptor for high speed
- usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs;
- //! USB device qualifier, only use in high speed mode
- usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier;
- //! USB configuration descriptor and UDI API pointers for high speed
- udc_config_speed_t UDC_DESC_STORAGE *conf_hs;
-#endif
- usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos;
-} udc_config_t;
-
-//! Global variables of USB Device Descriptor and UDI links
-extern UDC_DESC_STORAGE udc_config_t udc_config;
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-#endif // _UDC_DESC_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udd.h b/tmk_core/protocol/arm_atsam/usb/udd.h
deleted file mode 100644
index d9f58baf0b27..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udd.h
+++ /dev/null
@@ -1,384 +0,0 @@
-/**
- * \file
- *
- * \brief Common API for USB Device Drivers (UDD)
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDD_H_
-#define _UDD_H_
-
-#include "usb_protocol.h"
-#include "udc_desc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \ingroup usb_device_group
- * \defgroup udd_group USB Device Driver (UDD)
- *
- * The UDD driver provides a low-level abstraction of the device
- * controller hardware. Most events coming from the hardware such as
- * interrupts, which may cause the UDD to call into the UDC and UDI.
- *
- * @{
- */
-
-//! \brief Endpoint identifier
-typedef uint8_t udd_ep_id_t;
-
-//! \brief Endpoint transfer status
-//! Returned in parameters of callback register via udd_ep_run routine.
-typedef enum {
- UDD_EP_TRANSFER_OK = 0,
- UDD_EP_TRANSFER_ABORT = 1,
-} udd_ep_status_t;
-
-/**
- * \brief Global variable to give and record information of the setup request management
- *
- * This global variable allows to decode and response a setup request.
- * It can be updated by udc_process_setup() from UDC or *setup() from UDIs.
- */
-typedef struct {
- //! Data received in USB SETUP packet
- //! Note: The swap of "req.wValues" from uin16_t to le16_t is done by UDD.
- usb_setup_req_t req;
-
- //! Point to buffer to send or fill with data following SETUP packet
- //! This buffer must be word align for DATA IN phase (use prefix COMPILER_WORD_ALIGNED for buffer)
- uint8_t *payload;
-
- //! Size of buffer to send or fill, and content the number of byte transfered
- uint16_t payload_size;
-
- //! Callback called after reception of ZLP from setup request
- void (*callback)(void);
-
- //! Callback called when the buffer given (.payload) is full or empty.
- //! This one return false to abort data transfer, or true with a new buffer in .payload.
- bool (*over_under_run)(void);
-} udd_ctrl_request_t;
-extern udd_ctrl_request_t udd_g_ctrlreq;
-
-//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer
-#define Udd_setup_is_in() (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
-
-//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer
-#define Udd_setup_is_out() (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
-
-//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype.
-#define Udd_setup_type() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
-
-//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient
-#define Udd_setup_recipient() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
-
-/**
- * \brief End of halt callback function type.
- * Registered by routine udd_ep_wait_stall_clear()
- * Callback called when endpoint stall is cleared.
- */
-typedef void (*udd_callback_halt_cleared_t)(void);
-
-/**
- * \brief End of transfer callback function type.
- * Registered by routine udd_ep_run()
- * Callback called by USB interrupt after data transfer or abort (reset,...).
- *
- * \param status UDD_EP_TRANSFER_OK, if transfer is complete
- * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted
- * \param n number of data transfered
- */
-typedef void (*udd_callback_trans_t)(udd_ep_status_t status, iram_size_t nb_transfered, udd_ep_id_t ep);
-
-/**
- * \brief Authorizes the VBUS event
- *
- * \return true, if the VBUS monitoring is possible.
- */
-bool udd_include_vbus_monitoring(void);
-
-/**
- * \brief Enables the USB Device mode
- */
-void udd_enable(void);
-
-/**
- * \brief Disables the USB Device mode
- */
-void udd_disable(void);
-
-/**
- * \brief Attach device to the bus when possible
- *
- * \warning If a VBus control is included in driver,
- * then it will attach device when an acceptable Vbus
- * level from the host is detected.
- */
-void udd_attach(void);
-
-/**
- * \brief Detaches the device from the bus
- *
- * The driver must remove pull-up on USB line D- or D+.
- */
-void udd_detach(void);
-
-/**
- * \brief Test whether the USB Device Controller is running at high
- * speed or not.
- *
- * \return \c true if the Device is running at high speed mode, otherwise \c false.
- */
-bool udd_is_high_speed(void);
-
-/**
- * \brief Changes the USB address of device
- *
- * \param address New USB address
- */
-void udd_set_address(uint8_t address);
-
-/**
- * \brief Returns the USB address of device
- *
- * \return USB address
- */
-uint8_t udd_getaddress(void);
-
-/**
- * \brief Returns the current start of frame number
- *
- * \return current start of frame number.
- */
-uint16_t udd_get_frame_number(void);
-
-/**
- * \brief Returns the current micro start of frame number
- *
- * \return current micro start of frame number required in high speed mode.
- */
-uint16_t udd_get_micro_frame_number(void);
-
-/*! \brief The USB driver sends a resume signal called Upstream Resume
- */
-void udd_send_remotewakeup(void);
-
-/**
- * \brief Load setup payload
- *
- * \param payload Pointer on payload
- * \param payload_size Size of payload
- */
-void udd_set_setup_payload(uint8_t *payload, uint16_t payload_size);
-
-/**
- * \name Endpoint Management
- *
- * The following functions allow drivers to create and remove
- * endpoints, as well as set, clear and query their "halted" and
- * "wedged" states.
- */
-//@{
-
-#if (USB_DEVICE_MAX_EP != 0)
-
-/**
- * \brief Configures and enables an endpoint
- *
- * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
- * \param bmAttributes Attributes of endpoint declared in the descriptor.
- * \param MaxEndpointSize Endpoint maximum size
- *
- * \return \c 1 if the endpoint is enabled, otherwise \c 0.
- */
-bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize);
-
-/**
- * \brief Disables an endpoint
- *
- * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
- */
-void udd_ep_free(udd_ep_id_t ep);
-
-/**
- * \brief Check if the endpoint \a ep is halted.
- *
- * \param ep The ID of the endpoint to check.
- *
- * \return \c 1 if \a ep is halted, otherwise \c 0.
- */
-bool udd_ep_is_halted(udd_ep_id_t ep);
-
-/**
- * \brief Set the halted state of the endpoint \a ep
- *
- * After calling this function, any transaction on \a ep will result
- * in a STALL handshake being sent. Any pending transactions will be
- * performed first, however.
- *
- * \param ep The ID of the endpoint to be halted
- *
- * \return \c 1 if \a ep is halted, otherwise \c 0.
- */
-bool udd_ep_set_halt(udd_ep_id_t ep);
-
-/**
- * \brief Clear the halted state of the endpoint \a ep
- *
- * After calling this function, any transaction on \a ep will
- * be handled normally, i.e. a STALL handshake will not be sent, and
- * the data toggle sequence will start at DATA0.
- *
- * \param ep The ID of the endpoint to be un-halted
- *
- * \return \c 1 if function was successfully done, otherwise \c 0.
- */
-bool udd_ep_clear_halt(udd_ep_id_t ep);
-
-/**
- * \brief Registers a callback to call when endpoint halt is cleared
- *
- * \param ep The ID of the endpoint to use
- * \param callback NULL or function to call when endpoint halt is cleared
- *
- * \warning if the endpoint is not halted then the \a callback is called immediately.
- *
- * \return \c 1 if the register is accepted, otherwise \c 0.
- */
-bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback);
-
-/**
- * \brief Allows to receive or send data on an endpoint
- *
- * The driver uses a specific DMA USB to transfer data
- * from internal RAM to endpoint, if this one is available.
- * When the transfer is finished or aborted (stall, reset, ...), the \a callback is called.
- * The \a callback returns the transfer status and eventually the number of byte transfered.
- * Note: The control endpoint is not authorized.
- *
- * \param ep The ID of the endpoint to use
- * \param b_shortpacket Enabled automatic short packet
- * \param buf Buffer on Internal RAM to send or fill.
- * It must be align, then use COMPILER_WORD_ALIGNED.
- * \param buf_size Buffer size to send or fill
- * \param callback NULL or function to call at the end of transfer
- *
- * \warning About \a b_shortpacket, for IN endpoint it means that a short packet
- * (or a Zero Length Packet) will be sent to the USB line to properly close the usb
- * transfer at the end of the data transfer.
- * For Bulk and Interrupt OUT endpoint, it will automatically stop the transfer
- * at the end of the data transfer (received short packet).
- *
- * \return \c 1 if function was successfully done, otherwise \c 0.
- */
-bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t *buf, iram_size_t buf_size, udd_callback_trans_t callback);
-/**
- * \brief Aborts transfer on going on endpoint
- *
- * If a transfer is on going, then it is stopped and
- * the callback registered is called to signal the end of transfer.
- * Note: The control endpoint is not authorized.
- *
- * \param ep Endpoint to abort
- */
-void udd_ep_abort(udd_ep_id_t ep);
-
-#endif
-
-//@}
-
-/**
- * \name High speed test mode management
- *
- * The following functions allow the device to jump to a specific test mode required in high speed mode.
- */
-//@{
-void udd_test_mode_j(void);
-void udd_test_mode_k(void);
-void udd_test_mode_se0_nak(void);
-void udd_test_mode_packet(void);
-//@}
-
-/**
- * \name UDC callbacks to provide for UDD
- *
- * The following callbacks are used by UDD.
- */
-//@{
-
-/**
- * \brief Decodes and manages a setup request
- *
- * The driver call it when a SETUP packet is received.
- * The \c udd_g_ctrlreq contains the data of SETUP packet.
- * If this callback accepts the setup request then it must
- * return \c 1 and eventually update \c udd_g_ctrlreq to send or receive data.
- *
- * \return \c 1 if the request is accepted, otherwise \c 0.
- */
-extern bool udc_process_setup(void);
-
-/**
- * \brief Reset the UDC
- *
- * The UDC must reset all configuration.
- */
-extern void udc_reset(void);
-
-/**
- * \brief To signal that a SOF is occurred
- *
- * The UDC must send the signal to all UDIs enabled
- */
-extern void udc_sof_notify(void);
-
-//@}
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-#endif // _UDD_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi.h b/tmk_core/protocol/arm_atsam/usb/udi.h
deleted file mode 100644
index 60b117f3ca3a..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
- * \file
- *
- * \brief Common API for USB Device Interface
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDI_H_
-#define _UDI_H_
-
-#include "conf_usb.h"
-#include "usb_protocol.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \ingroup usb_device_group
- * \defgroup udi_group USB Device Interface (UDI)
- * The UDI provides a common API for all classes,
- * and this is used by UDC for the main control of USB Device interface.
- * @{
- */
-
-/**
- * \brief UDI API.
- *
- * The callbacks within this structure are called only by
- * USB Device Controller (UDC)
- *
- * The udc_get_interface_desc() can be use by UDI to know the interface descriptor
- * selected by UDC.
- */
-typedef struct {
- /**
- * \brief Enable the interface.
- *
- * This function is called when the host selects a configuration
- * to which this interface belongs through a Set Configuration
- * request, and when the host selects an alternate setting of
- * this interface through a Set Interface request.
- *
- * \return \c 1 if function was successfully done, otherwise \c 0.
- */
- bool (*enable)(void);
-
- /**
- * \brief Disable the interface.
- *
- * This function is called when this interface is currently
- * active, and
- * - the host selects any configuration through a Set
- * Configuration request, or
- * - the host issues a USB reset, or
- * - the device is detached from the host (i.e. Vbus is no
- * longer present)
- */
- void (*disable)(void);
-
- /**
- * \brief Handle a control request directed at an interface.
- *
- * This function is called when this interface is currently
- * active and the host sends a SETUP request
- * with this interface as the recipient.
- *
- * Use udd_g_ctrlreq to decode and response to SETUP request.
- *
- * \return \c 1 if this interface supports the SETUP request, otherwise \c 0.
- */
- bool (*setup)(void);
-
- /**
- * \brief Returns the current setting of the selected interface.
- *
- * This function is called when UDC when know alternate setting of selected interface.
- *
- * \return alternate setting of selected interface
- */
- uint8_t (*getsetting)(void);
-
- /**
- * \brief To signal that a SOF is occurred
- */
- void (*sof_notify)(void);
-} udi_api_t;
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-#endif // _UDI_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_cdc.c b/tmk_core/protocol/arm_atsam/usb/udi_cdc.c
deleted file mode 100644
index d40030f36dfc..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_cdc.c
+++ /dev/null
@@ -1,1267 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device Communication Device Class (CDC) interface.
- *
- * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#include "samd51j18a.h"
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "usb_protocol_cdc.h"
-#include "udd.h"
-#include "udc.h"
-#include "udi_cdc.h"
-#include
-#include "udi_cdc_conf.h"
-#include "udi_device_conf.h"
-#include "stdarg.h"
-#include "tmk_core/protocol/arm_atsam/clks.h"
-
-#ifdef VIRTSER_ENABLE
-
-# ifdef UDI_CDC_LOW_RATE
-# ifdef USB_DEVICE_HS_SUPPORT
-# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
-# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
-# else
-# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE)
-# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE)
-# endif
-# else
-# ifdef USB_DEVICE_HS_SUPPORT
-# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
-# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
-# else
-# define UDI_CDC_TX_BUFFERS (5 * UDI_CDC_DATA_EPS_FS_SIZE)
-# define UDI_CDC_RX_BUFFERS (5 * UDI_CDC_DATA_EPS_FS_SIZE)
-# endif
-# endif
-
-# ifndef UDI_CDC_TX_EMPTY_NOTIFY
-# define UDI_CDC_TX_EMPTY_NOTIFY(port)
-# endif
-
-/**
- * \ingroup udi_cdc_group
- * \defgroup udi_cdc_group_udc Interface with USB Device Core (UDC)
- *
- * Structures and functions required by UDC.
- *
- * @{
- */
-bool udi_cdc_comm_enable(void);
-void udi_cdc_comm_disable(void);
-bool udi_cdc_comm_setup(void);
-bool udi_cdc_data_enable(void);
-void udi_cdc_data_disable(void);
-bool udi_cdc_data_setup(void);
-uint8_t udi_cdc_getsetting(void);
-void udi_cdc_data_sof_notify(void);
-UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm = {.enable = udi_cdc_comm_enable, .disable = udi_cdc_comm_disable, .setup = udi_cdc_comm_setup, .getsetting = udi_cdc_getsetting, .sof_notify = NULL};
-UDC_DESC_STORAGE udi_api_t udi_api_cdc_data = {
- .enable = udi_cdc_data_enable,
- .disable = udi_cdc_data_disable,
- .setup = udi_cdc_data_setup,
- .getsetting = udi_cdc_getsetting,
- .sof_notify = udi_cdc_data_sof_notify,
-};
-//@}
-
-/**
- * \ingroup udi_cdc_group
- * \defgroup udi_cdc_group_internal Implementation of UDI CDC
- *
- * Class internal implementation
- * @{
- */
-
-/**
- * \name Internal routines
- */
-//@{
-
-/**
- * \name Routines to control serial line
- */
-//@{
-
-/**
- * \brief Returns the port number corresponding at current setup request
- *
- * \return port number
- */
-static uint8_t udi_cdc_setup_to_port(void);
-
-/**
- * \brief Sends line coding to application
- *
- * Called after SETUP request when line coding data is received.
- */
-static void udi_cdc_line_coding_received(void);
-
-/**
- * \brief Records new state
- *
- * \param port Communication port number to manage
- * \param b_set State is enabled if true, else disabled
- * \param bit_mask Field to process (see CDC_SERIAL_STATE_ defines)
- */
-static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask);
-
-/**
- * \brief Check and eventually notify the USB host of new state
- *
- * \param port Communication port number to manage
- * \param ep Port communication endpoint
- */
-static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep);
-
-/**
- * \brief Ack sent of serial state message
- * Callback called after serial state message sent
- *
- * \param status UDD_EP_TRANSFER_OK, if transfer finished
- * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted
- * \param n number of data transfered
- */
-static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep);
-
-//@}
-
-/**
- * \name Routines to process data transfer
- */
-//@{
-
-/**
- * \brief Enable the reception of data from the USB host
- *
- * The value udi_cdc_rx_trans_sel indicate the RX buffer to fill.
- *
- * \param port Communication port number to manage
- *
- * \return \c 1 if function was successfully done, otherwise \c 0.
- */
-static bool udi_cdc_rx_start(uint8_t port);
-
-/**
- * \brief Update rx buffer management with a new data
- * Callback called after data reception on USB line
- *
- * \param status UDD_EP_TRANSFER_OK, if transfer finish
- * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted
- * \param n number of data received
- */
-static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep);
-
-/**
- * \brief Ack sent of tx buffer
- * Callback called after data transfer on USB line
- *
- * \param status UDD_EP_TRANSFER_OK, if transfer finished
- * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted
- * \param n number of data transfered
- */
-static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep);
-
-/**
- * \brief Send buffer on line or wait a SOF event
- *
- * \param port Communication port number to manage
- */
-static void udi_cdc_tx_send(uint8_t port);
-
-//@}
-
-//@}
-
-/**
- * \name Information about configuration of communication line
- */
-//@{
-COMPILER_WORD_ALIGNED
-static usb_cdc_line_coding_t udi_cdc_line_coding[UDI_CDC_PORT_NB];
-static bool udi_cdc_serial_state_msg_ongoing[UDI_CDC_PORT_NB];
-static volatile le16_t udi_cdc_state[UDI_CDC_PORT_NB];
-COMPILER_WORD_ALIGNED static usb_cdc_notify_serial_state_t uid_cdc_state_msg[UDI_CDC_PORT_NB];
-
-//! Status of CDC COMM interfaces
-static volatile uint8_t udi_cdc_nb_comm_enabled = 0;
-//@}
-
-/**
- * \name Variables to manage RX/TX transfer requests
- * Two buffers for each sense are used to optimize the speed.
- */
-//@{
-
-//! Status of CDC DATA interfaces
-static volatile uint8_t udi_cdc_nb_data_enabled = 0;
-static volatile bool udi_cdc_data_running = false;
-//! Buffer to receive data
-COMPILER_WORD_ALIGNED static uint8_t udi_cdc_rx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_RX_BUFFERS];
-//! Data available in RX buffers
-static volatile uint16_t udi_cdc_rx_buf_nb[UDI_CDC_PORT_NB][2];
-//! Give the current RX buffer used (rx0 if 0, rx1 if 1)
-static volatile uint8_t udi_cdc_rx_buf_sel[UDI_CDC_PORT_NB];
-//! Read position in current RX buffer
-static volatile uint16_t udi_cdc_rx_pos[UDI_CDC_PORT_NB];
-//! Signal a transfer on-going
-static volatile bool udi_cdc_rx_trans_ongoing[UDI_CDC_PORT_NB];
-
-//! Define a transfer halted
-# define UDI_CDC_TRANS_HALTED 2
-
-//! Buffer to send data
-COMPILER_WORD_ALIGNED static uint8_t udi_cdc_tx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_TX_BUFFERS];
-//! Data available in TX buffers
-static uint16_t udi_cdc_tx_buf_nb[UDI_CDC_PORT_NB][2];
-//! Give current TX buffer used (tx0 if 0, tx1 if 1)
-static volatile uint8_t udi_cdc_tx_buf_sel[UDI_CDC_PORT_NB];
-//! Value of SOF during last TX transfer
-static uint16_t udi_cdc_tx_sof_num[UDI_CDC_PORT_NB];
-//! Signal a transfer on-going
-static volatile bool udi_cdc_tx_trans_ongoing[UDI_CDC_PORT_NB];
-//! Signal that both buffer content data to send
-static volatile bool udi_cdc_tx_both_buf_to_send[UDI_CDC_PORT_NB];
-
-//@}
-
-bool udi_cdc_comm_enable(void) {
- uint8_t port;
- uint8_t iface_comm_num;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- udi_cdc_nb_comm_enabled = 0;
- //#else
- // if (udi_cdc_nb_comm_enabled > UDI_CDC_PORT_NB) {
- // udi_cdc_nb_comm_enabled = 0;
- // }
- // port = udi_cdc_nb_comm_enabled;
- //#endif
-
- // Initialize control signal management
- udi_cdc_state[port] = CPU_TO_LE16(0);
-
- uid_cdc_state_msg[port].header.bmRequestType = USB_REQ_DIR_IN | USB_REQ_TYPE_CLASS | USB_REQ_RECIP_INTERFACE;
- uid_cdc_state_msg[port].header.bNotification = USB_REQ_CDC_NOTIFY_SERIAL_STATE;
- uid_cdc_state_msg[port].header.wValue = LE16(0);
-
- /*
- switch (port) {
- #define UDI_CDC_PORT_TO_IFACE_COMM(index, unused) \
- case index: \
- iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_##index; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_IFACE_COMM, ~)
- #undef UDI_CDC_PORT_TO_IFACE_COMM
- default:
- iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_0;
- break;
- }
- */
- iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_0;
-
- uid_cdc_state_msg[port].header.wIndex = LE16(iface_comm_num);
- uid_cdc_state_msg[port].header.wLength = LE16(2);
- uid_cdc_state_msg[port].value = CPU_TO_LE16(0);
-
- udi_cdc_line_coding[port].dwDTERate = CPU_TO_LE32(UDI_CDC_DEFAULT_RATE);
- udi_cdc_line_coding[port].bCharFormat = UDI_CDC_DEFAULT_STOPBITS;
- udi_cdc_line_coding[port].bParityType = UDI_CDC_DEFAULT_PARITY;
- udi_cdc_line_coding[port].bDataBits = UDI_CDC_DEFAULT_DATABITS;
- // Call application callback
- // to initialize memories or indicate that interface is enabled
-# if 0
- UDI_CDC_SET_CODING_EXT(port,(&udi_cdc_line_coding[port]));
- if (!UDI_CDC_ENABLE_EXT(port)) {
- return false;
- }
-# endif
- udi_cdc_nb_comm_enabled++;
- return true;
-}
-
-bool udi_cdc_data_enable(void) {
- uint8_t port;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- udi_cdc_nb_data_enabled = 0;
- //#else
- // if (udi_cdc_nb_data_enabled > UDI_CDC_PORT_NB) {
- // udi_cdc_nb_data_enabled = 0;
- // }
- // port = udi_cdc_nb_data_enabled;
- //#endif
-
- // Initialize TX management
- udi_cdc_tx_trans_ongoing[port] = false;
- udi_cdc_tx_both_buf_to_send[port] = false;
- udi_cdc_tx_buf_sel[port] = 0;
- udi_cdc_tx_buf_nb[port][0] = 0;
- udi_cdc_tx_buf_nb[port][1] = 0;
- udi_cdc_tx_sof_num[port] = 0;
- udi_cdc_tx_send(port);
-
- // Initialize RX management
- udi_cdc_rx_trans_ongoing[port] = false;
- udi_cdc_rx_buf_sel[port] = 0;
- udi_cdc_rx_buf_nb[port][0] = 0;
- udi_cdc_rx_buf_nb[port][1] = 0;
- udi_cdc_rx_pos[port] = 0;
- if (!udi_cdc_rx_start(port)) {
- return false;
- }
- udi_cdc_nb_data_enabled++;
- if (udi_cdc_nb_data_enabled == UDI_CDC_PORT_NB) {
- udi_cdc_data_running = true;
- }
- return true;
-}
-
-void udi_cdc_comm_disable(void) {
- Assert(udi_cdc_nb_comm_enabled != 0);
- udi_cdc_nb_comm_enabled--;
-}
-
-void udi_cdc_data_disable(void) {
- // uint8_t port;
-
- Assert(udi_cdc_nb_data_enabled != 0);
- udi_cdc_nb_data_enabled--;
- // port = udi_cdc_nb_data_enabled;
- // UDI_CDC_DISABLE_EXT(port);
- udi_cdc_data_running = false;
-}
-
-bool udi_cdc_comm_setup(void) {
- uint8_t port = udi_cdc_setup_to_port();
-
- if (Udd_setup_is_in()) {
- // GET Interface Requests
- if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
- // Requests Class Interface Get
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_CDC_GET_LINE_CODING:
- // Get configuration of CDC line
- if (sizeof(usb_cdc_line_coding_t) != udd_g_ctrlreq.req.wLength) return false; // Error for USB host
- udd_g_ctrlreq.payload = (uint8_t *)&udi_cdc_line_coding[port];
- udd_g_ctrlreq.payload_size = sizeof(usb_cdc_line_coding_t);
- return true;
- }
- }
- }
- if (Udd_setup_is_out()) {
- // SET Interface Requests
- if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
- // Requests Class Interface Set
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_CDC_SET_LINE_CODING:
- // Change configuration of CDC line
- if (sizeof(usb_cdc_line_coding_t) != udd_g_ctrlreq.req.wLength) return false; // Error for USB host
- udd_g_ctrlreq.callback = udi_cdc_line_coding_received;
- udd_g_ctrlreq.payload = (uint8_t *)&udi_cdc_line_coding[port];
- udd_g_ctrlreq.payload_size = sizeof(usb_cdc_line_coding_t);
- return true;
- case USB_REQ_CDC_SET_CONTROL_LINE_STATE:
- // According cdc spec 1.1 chapter 6.2.14
- // UDI_CDC_SET_DTR_EXT(port, (0 !=
- // (udd_g_ctrlreq.req.wValue
- // & CDC_CTRL_SIGNAL_DTE_PRESENT)));
- // UDI_CDC_SET_RTS_EXT(port, (0 !=
- // (udd_g_ctrlreq.req.wValue
- // & CDC_CTRL_SIGNAL_ACTIVATE_CARRIER)));
- return true;
- }
- }
- }
- return false; // request Not supported
-}
-
-bool udi_cdc_data_setup(void) {
- return false; // request Not supported
-}
-
-uint8_t udi_cdc_getsetting(void) {
- return 0; // CDC don't have multiple alternate setting
-}
-
-void udi_cdc_data_sof_notify(void) {
- static uint8_t port_notify = 0;
-
- // A call of udi_cdc_data_sof_notify() is done for each port
- udi_cdc_tx_send(port_notify);
- /*
-#if UDI_CDC_PORT_NB != 1 // To optimize code
- port_notify++;
- if (port_notify >= UDI_CDC_PORT_NB) {
- port_notify = 0;
- }
-#endif
- */
-}
-
-//-------------------------------------------------
-//------- Internal routines to control serial line
-
-static uint8_t udi_cdc_setup_to_port(void) {
- uint8_t port;
-
- /*
- switch (udd_g_ctrlreq.req.wIndex & 0xFF) {
-#define UDI_CDC_IFACE_COMM_TO_PORT(iface, unused) \
- case UDI_CDC_COMM_IFACE_NUMBER_##iface: \
- port = iface; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_IFACE_COMM_TO_PORT, ~)
-#undef UDI_CDC_IFACE_COMM_TO_PORT
- default:
- port = 0;
- break;
- }
- */
- port = 0;
-
- return port;
-}
-
-static void udi_cdc_line_coding_received(void) {
- uint8_t port = udi_cdc_setup_to_port();
- UNUSED(port);
-
- // UDI_CDC_SET_CODING_EXT(port, (&udi_cdc_line_coding[port]));
-}
-
-static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask) {
- udd_ep_id_t ep_comm;
- uint32_t irqflags; // irqflags_t
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- // Update state
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- if (b_set) {
- udi_cdc_state[port] |= bit_mask;
- } else {
- udi_cdc_state[port] &= ~(unsigned)bit_mask;
- }
- __DMB();
- __set_PRIMASK(irqflags);
-
- /*
- // Send it if possible and state changed
- switch (port) {
-#define UDI_CDC_PORT_TO_COMM_EP(index, unused) \
- case index: \
- ep_comm = UDI_CDC_COMM_EP_##index; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_COMM_EP, ~)
-#undef UDI_CDC_PORT_TO_COMM_EP
- default:
- ep_comm = UDI_CDC_COMM_EP_0;
- break;
- }
- */
- ep_comm = UDI_CDC_COMM_EP_0;
-
- udi_cdc_ctrl_state_notify(port, ep_comm);
-}
-
-static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep) {
-# if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
-# endif
-
- // Send it if possible and state changed
- if ((!udi_cdc_serial_state_msg_ongoing[port]) && (udi_cdc_state[port] != uid_cdc_state_msg[port].value)) {
- // Fill notification message
- uid_cdc_state_msg[port].value = udi_cdc_state[port];
- // Send notification message
- udi_cdc_serial_state_msg_ongoing[port] = udd_ep_run(ep, false, (uint8_t *)&uid_cdc_state_msg[port], sizeof(uid_cdc_state_msg[0]), udi_cdc_serial_state_msg_sent);
- }
-}
-
-static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) {
- uint8_t port;
- UNUSED(n);
- UNUSED(status);
-
- /*
- switch (ep) {
-#define UDI_CDC_GET_PORT_FROM_COMM_EP(iface, unused) \
- case UDI_CDC_COMM_EP_##iface: \
- port = iface; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_GET_PORT_FROM_COMM_EP, ~)
-#undef UDI_CDC_GET_PORT_FROM_COMM_EP
- default:
- port = 0;
- break;
- }
- */
- port = 0;
-
- udi_cdc_serial_state_msg_ongoing[port] = false;
-
- // For the irregular signals like break, the incoming ring signal,
- // or the overrun error state, this will reset their values to zero
- // and again will not send another notification until their state changes.
- udi_cdc_state[port] &= ~(CDC_SERIAL_STATE_BREAK | CDC_SERIAL_STATE_RING | CDC_SERIAL_STATE_FRAMING | CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN);
- uid_cdc_state_msg[port].value &= ~(CDC_SERIAL_STATE_BREAK | CDC_SERIAL_STATE_RING | CDC_SERIAL_STATE_FRAMING | CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN);
- // Send it if possible and state changed
- udi_cdc_ctrl_state_notify(port, ep);
-}
-
-//-------------------------------------------------
-//------- Internal routines to process data transfer
-
-static bool udi_cdc_rx_start(uint8_t port) {
- uint32_t irqflags; // irqflags_t
- uint8_t buf_sel_trans;
- udd_ep_id_t ep;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- buf_sel_trans = udi_cdc_rx_buf_sel[port];
- if (udi_cdc_rx_trans_ongoing[port] || (udi_cdc_rx_pos[port] < udi_cdc_rx_buf_nb[port][buf_sel_trans])) {
- // Transfer already on-going or current buffer no empty
- __DMB();
- __set_PRIMASK(irqflags);
- return false;
- }
-
- // Change current buffer
- udi_cdc_rx_pos[port] = 0;
- udi_cdc_rx_buf_sel[port] = (buf_sel_trans == 0) ? 1 : 0;
-
- // Start transfer on RX
- udi_cdc_rx_trans_ongoing[port] = true;
- __DMB();
- __set_PRIMASK(irqflags);
-
- if (udi_cdc_multi_is_rx_ready(port)) {
- // UDI_CDC_RX_NOTIFY(port);
- }
-
- /*
- // Send the buffer with enable of short packet
- switch (port) {
-#define UDI_CDC_PORT_TO_DATA_EP_OUT(index, unused) \
- case index: \
- ep = UDI_CDC_DATA_EP_OUT_##index; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_OUT, ~)
-#undef UDI_CDC_PORT_TO_DATA_EP_OUT
- default:
- ep = UDI_CDC_DATA_EP_OUT_0;
- break;
- }
- */
- ep = UDI_CDC_DATA_EP_OUT_0;
-
- return udd_ep_run(ep, true, udi_cdc_rx_buf[port][buf_sel_trans], UDI_CDC_RX_BUFFERS, udi_cdc_data_received);
-}
-
-static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) {
- uint8_t buf_sel_trans;
- uint8_t port;
-
- /*
- switch (ep) {
-#define UDI_CDC_DATA_EP_OUT_TO_PORT(index, unused) \
- case UDI_CDC_DATA_EP_OUT_##index: \
- port = index; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_OUT_TO_PORT, ~)
-#undef UDI_CDC_DATA_EP_OUT_TO_PORT
- default:
- port = 0;
- break;
- }
- */
- port = 0;
-
- if (UDD_EP_TRANSFER_OK != status) {
- // Abort reception
- return;
- }
-
- buf_sel_trans = (udi_cdc_rx_buf_sel[port] == 0) ? 1 : 0;
-
- if (!n) {
- udd_ep_run(ep, true, udi_cdc_rx_buf[port][buf_sel_trans], UDI_CDC_RX_BUFFERS, udi_cdc_data_received);
- return;
- }
-
- udi_cdc_rx_buf_nb[port][buf_sel_trans] = n;
- udi_cdc_rx_trans_ongoing[port] = false;
- udi_cdc_rx_start(port);
-}
-
-static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) {
- uint8_t port;
- UNUSED(n);
-
- /*
- switch (ep) {
-#define UDI_CDC_DATA_EP_IN_TO_PORT(index, unused) \
- case UDI_CDC_DATA_EP_IN_##index: \
- port = index; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_IN_TO_PORT, ~)
-#undef UDI_CDC_DATA_EP_IN_TO_PORT
- default:
- port = 0;
- break;
- }
- */
- port = 0;
-
- if (UDD_EP_TRANSFER_OK != status) {
- // Abort transfer
- return;
- }
-
- udi_cdc_tx_buf_nb[port][(udi_cdc_tx_buf_sel[port] == 0) ? 1 : 0] = 0;
- udi_cdc_tx_both_buf_to_send[port] = false;
- udi_cdc_tx_trans_ongoing[port] = false;
-
- if (n != 0) {
- UDI_CDC_TX_EMPTY_NOTIFY(port);
- }
-
- udi_cdc_tx_send(port);
-}
-
-static void udi_cdc_tx_send(uint8_t port) {
- uint32_t irqflags; // irqflags_t
- uint8_t buf_sel_trans;
- bool b_short_packet;
- udd_ep_id_t ep;
- static uint16_t sof_zlp_counter = 0;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- if (udi_cdc_tx_trans_ongoing[port]) {
- return; // Already on going or wait next SOF to send next data
- }
- if (udd_is_high_speed()) {
- if (udi_cdc_tx_sof_num[port] == udd_get_micro_frame_number()) {
- return; // Wait next SOF to send next data
- }
- } else {
- if (udi_cdc_tx_sof_num[port] == udd_get_frame_number()) {
- return; // Wait next SOF to send next data
- }
- }
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- buf_sel_trans = udi_cdc_tx_buf_sel[port];
- if (udi_cdc_tx_buf_nb[port][buf_sel_trans] == 0) {
- sof_zlp_counter++;
- if (((!udd_is_high_speed()) && (sof_zlp_counter < 100)) || (udd_is_high_speed() && (sof_zlp_counter < 800))) {
- __DMB();
- __set_PRIMASK(irqflags);
- return;
- }
- }
- sof_zlp_counter = 0;
-
- if (!udi_cdc_tx_both_buf_to_send[port]) {
- // Send current Buffer
- // and switch the current buffer
- udi_cdc_tx_buf_sel[port] = (buf_sel_trans == 0) ? 1 : 0;
- } else {
- // Send the other Buffer
- // and no switch the current buffer
- buf_sel_trans = (buf_sel_trans == 0) ? 1 : 0;
- }
- udi_cdc_tx_trans_ongoing[port] = true;
- __DMB();
- __set_PRIMASK(irqflags);
-
- b_short_packet = (udi_cdc_tx_buf_nb[port][buf_sel_trans] != UDI_CDC_TX_BUFFERS);
- if (b_short_packet) {
- if (udd_is_high_speed()) {
- udi_cdc_tx_sof_num[port] = udd_get_micro_frame_number();
- } else {
- udi_cdc_tx_sof_num[port] = udd_get_frame_number();
- }
- } else {
- udi_cdc_tx_sof_num[port] = 0; // Force next transfer without wait SOF
- }
-
- /*
- // Send the buffer with enable of short packet
- switch (port) {
-#define UDI_CDC_PORT_TO_DATA_EP_IN(index, unused) \
- case index: \
- ep = UDI_CDC_DATA_EP_IN_##index; \
- break;
- MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_IN, ~)
-#undef UDI_CDC_PORT_TO_DATA_EP_IN
- default:
- ep = UDI_CDC_DATA_EP_IN_0;
- break;
- }
- */
- ep = UDI_CDC_DATA_EP_IN_0;
-
- udd_ep_run(ep, b_short_packet, udi_cdc_tx_buf[port][buf_sel_trans], udi_cdc_tx_buf_nb[port][buf_sel_trans], udi_cdc_data_sent);
-}
-
-//---------------------------------------------
-//------- Application interface
-
-void udi_cdc_ctrl_signal_dcd(bool b_set) {
- udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DCD);
-}
-
-void udi_cdc_ctrl_signal_dsr(bool b_set) {
- udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DSR);
-}
-
-void udi_cdc_signal_framing_error(void) {
- udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_FRAMING);
-}
-
-void udi_cdc_signal_parity_error(void) {
- udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_PARITY);
-}
-
-void udi_cdc_signal_overrun(void) {
- udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_OVERRUN);
-}
-
-void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set) {
- udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DCD);
-}
-
-void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set) {
- udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DSR);
-}
-
-void udi_cdc_multi_signal_framing_error(uint8_t port) {
- udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_FRAMING);
-}
-
-void udi_cdc_multi_signal_parity_error(uint8_t port) {
- udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_PARITY);
-}
-
-void udi_cdc_multi_signal_overrun(uint8_t port) {
- udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_OVERRUN);
-}
-
-iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port) {
- uint32_t irqflags; // irqflags_t
- uint16_t pos;
- iram_size_t nb_received;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- pos = udi_cdc_rx_pos[port];
- nb_received = udi_cdc_rx_buf_nb[port][udi_cdc_rx_buf_sel[port]] - pos;
- __DMB();
- __set_PRIMASK(irqflags);
- return nb_received;
-}
-
-iram_size_t udi_cdc_get_nb_received_data(void) {
- return udi_cdc_multi_get_nb_received_data(0);
-}
-
-bool udi_cdc_multi_is_rx_ready(uint8_t port) {
- return (udi_cdc_multi_get_nb_received_data(port) > 0);
-}
-
-bool udi_cdc_is_rx_ready(void) {
- return udi_cdc_multi_is_rx_ready(0);
-}
-
-int udi_cdc_multi_getc(uint8_t port) {
- uint32_t irqflags; // irqflags_t
- int rx_data = 0;
- bool b_databit_9;
- uint16_t pos;
- uint8_t buf_sel;
- bool again;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits);
-
-udi_cdc_getc_process_one_byte:
- // Check available data
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- pos = udi_cdc_rx_pos[port];
- buf_sel = udi_cdc_rx_buf_sel[port];
- again = pos >= udi_cdc_rx_buf_nb[port][buf_sel];
- __DMB();
- __set_PRIMASK(irqflags);
- while (again) {
- if (!udi_cdc_data_running) {
- return 0;
- }
- goto udi_cdc_getc_process_one_byte;
- }
-
- // Read data
- rx_data |= udi_cdc_rx_buf[port][buf_sel][pos];
- udi_cdc_rx_pos[port] = pos + 1;
-
- udi_cdc_rx_start(port);
-
- if (b_databit_9) {
- // Receive MSB
- b_databit_9 = false;
- rx_data = rx_data << 8;
- goto udi_cdc_getc_process_one_byte;
- }
- return rx_data;
-}
-
-int udi_cdc_getc(void) {
- return udi_cdc_multi_getc(0);
-}
-
-iram_size_t udi_cdc_multi_read_buf(uint8_t port, void *buf, iram_size_t size) {
- uint32_t irqflags; // irqflags_t
- uint8_t * ptr_buf = (uint8_t *)buf;
- iram_size_t copy_nb;
- uint16_t pos;
- uint8_t buf_sel;
- bool again;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
-udi_cdc_read_buf_loop_wait:
- // Check available data
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- pos = udi_cdc_rx_pos[port];
- buf_sel = udi_cdc_rx_buf_sel[port];
- again = pos >= udi_cdc_rx_buf_nb[port][buf_sel];
- __DMB();
- __set_PRIMASK(irqflags);
- while (again) {
- if (!udi_cdc_data_running) {
- return size;
- }
- goto udi_cdc_read_buf_loop_wait;
- }
-
- // Read data
- copy_nb = udi_cdc_rx_buf_nb[port][buf_sel] - pos;
- if (copy_nb > size) {
- copy_nb = size;
- }
- memcpy(ptr_buf, &udi_cdc_rx_buf[port][buf_sel][pos], copy_nb);
- udi_cdc_rx_pos[port] += copy_nb;
- ptr_buf += copy_nb;
- size -= copy_nb;
- udi_cdc_rx_start(port);
-
- if (size) {
- goto udi_cdc_read_buf_loop_wait;
- }
- return 0;
-}
-
-static iram_size_t udi_cdc_multi_read_no_polling(uint8_t port, void *buf, iram_size_t size) {
- uint8_t * ptr_buf = (uint8_t *)buf;
- iram_size_t nb_avail_data;
- uint16_t pos;
- uint8_t buf_sel;
- uint32_t irqflags; // irqflags_t
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- // Data interface not started... exit
- if (!udi_cdc_data_running) {
- return 0;
- }
-
- // Get number of available data
- // Check available data
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- pos = udi_cdc_rx_pos[port];
- buf_sel = udi_cdc_rx_buf_sel[port];
- nb_avail_data = udi_cdc_rx_buf_nb[port][buf_sel] - pos;
- __DMB();
- __set_PRIMASK(irqflags);
- // If the buffer contains less than the requested number of data,
- // adjust read size
- if (nb_avail_data < size) {
- size = nb_avail_data;
- }
- if (size > 0) {
- memcpy(ptr_buf, &udi_cdc_rx_buf[port][buf_sel][pos], size);
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- udi_cdc_rx_pos[port] += size;
- __DMB();
- __set_PRIMASK(irqflags);
- ptr_buf += size;
- udi_cdc_rx_start(port);
- }
- return (nb_avail_data);
-}
-
-iram_size_t udi_cdc_read_no_polling(void *buf, iram_size_t size) {
- return udi_cdc_multi_read_no_polling(0, buf, size);
-}
-
-iram_size_t udi_cdc_read_buf(void *buf, iram_size_t size) {
- return udi_cdc_multi_read_buf(0, buf, size);
-}
-
-iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port) {
- uint32_t irqflags; // irqflags_t
- iram_size_t buf_sel_nb, retval;
- uint8_t buf_sel;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- buf_sel = udi_cdc_tx_buf_sel[port];
- buf_sel_nb = udi_cdc_tx_buf_nb[port][buf_sel];
- if (buf_sel_nb == UDI_CDC_TX_BUFFERS) {
- if ((!udi_cdc_tx_trans_ongoing[port]) && (!udi_cdc_tx_both_buf_to_send[port])) {
- /* One buffer is full, but the other buffer is not used.
- * (not used = transfer on-going)
- * then move to the other buffer to store data */
- udi_cdc_tx_both_buf_to_send[port] = true;
- udi_cdc_tx_buf_sel[port] = (buf_sel == 0) ? 1 : 0;
- buf_sel_nb = 0;
- }
- }
- retval = UDI_CDC_TX_BUFFERS - buf_sel_nb;
- __DMB();
- __set_PRIMASK(irqflags);
- return retval;
-}
-
-iram_size_t udi_cdc_get_free_tx_buffer(void) {
- return udi_cdc_multi_get_free_tx_buffer(0);
-}
-
-bool udi_cdc_multi_is_tx_ready(uint8_t port) {
- return (udi_cdc_multi_get_free_tx_buffer(port) != 0);
-}
-
-bool udi_cdc_is_tx_ready(void) {
- return udi_cdc_multi_is_tx_ready(0);
-}
-
-int udi_cdc_multi_putc(uint8_t port, int value) {
- uint32_t irqflags; // irqflags_t
- bool b_databit_9;
- uint8_t buf_sel;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits);
-
-udi_cdc_putc_process_one_byte:
- // Check available space
- if (!udi_cdc_multi_is_tx_ready(port)) {
- if (!udi_cdc_data_running) {
- return false;
- }
- goto udi_cdc_putc_process_one_byte;
- }
-
- // Write value
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- buf_sel = udi_cdc_tx_buf_sel[port];
- udi_cdc_tx_buf[port][buf_sel][udi_cdc_tx_buf_nb[port][buf_sel]++] = value;
- __DMB();
- __set_PRIMASK(irqflags);
-
- if (b_databit_9) {
- // Send MSB
- b_databit_9 = false;
- value = value >> 8;
- goto udi_cdc_putc_process_one_byte;
- }
- return true;
-}
-
-int udi_cdc_putc(int value) {
- return udi_cdc_multi_putc(0, value);
-}
-
-iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void *buf, iram_size_t size) {
- uint32_t irqflags; // irqflags_t
- uint8_t buf_sel;
- uint16_t buf_nb;
- iram_size_t copy_nb;
- uint8_t * ptr_buf = (uint8_t *)buf;
-
- //#if UDI_CDC_PORT_NB == 1 // To optimize code
- port = 0;
- //#endif
-
- if (9 == udi_cdc_line_coding[port].bDataBits) {
- size *= 2;
- }
-
-udi_cdc_write_buf_loop_wait:
-
- // Check available space
- if (!udi_cdc_multi_is_tx_ready(port)) {
- if (!udi_cdc_data_running) {
- return size;
- }
- goto udi_cdc_write_buf_loop_wait;
- }
-
- // Write values
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
- buf_sel = udi_cdc_tx_buf_sel[port];
- buf_nb = udi_cdc_tx_buf_nb[port][buf_sel];
- copy_nb = UDI_CDC_TX_BUFFERS - buf_nb;
- if (copy_nb > size) {
- copy_nb = size;
- }
- memcpy(&udi_cdc_tx_buf[port][buf_sel][buf_nb], ptr_buf, copy_nb);
- udi_cdc_tx_buf_nb[port][buf_sel] = buf_nb + copy_nb;
- __DMB();
- __set_PRIMASK(irqflags);
-
- // Update buffer pointer
- ptr_buf = ptr_buf + copy_nb;
- size -= copy_nb;
-
- if (size) {
- goto udi_cdc_write_buf_loop_wait;
- }
-
- return 0;
-}
-
-iram_size_t udi_cdc_write_buf(const void *buf, iram_size_t size) {
- return udi_cdc_multi_write_buf(0, buf, size);
-}
-
-# define MAX_PRINT 256
-# define CDC_SEND_INTERVAL 2
-uint32_t cdc_tx_send_time_next;
-
-void CDC_send(void) {
- while (timer_read64() < cdc_tx_send_time_next)
- ;
- udi_cdc_tx_send(0);
- cdc_tx_send_time_next = timer_read64() + CDC_SEND_INTERVAL;
-}
-
-uint32_t CDC_print(char *printbuf) {
- uint32_t count = 0;
- char * buf = printbuf;
- char c;
-
- if (timer_read64() < 5000) return 0;
-
- while ((c = *buf++) != 0 && !(count >= MAX_PRINT)) {
- count++;
- if (!udi_cdc_is_tx_ready()) return 0;
- udi_cdc_putc(c);
- if (count >= UDI_CDC_TX_BUFFERS) {
- count = 0;
- CDC_send();
- }
- }
- if (count) {
- CDC_send();
- }
- return 1;
-}
-
-char printbuf[CDC_PRINTBUF_SIZE];
-
-int CDC_printf(const char *_Format, ...) {
- va_list va; // Variable argument list variable
- int result;
-
- va_start(va, _Format); // Initialize the variable argument list
- result = vsnprintf(printbuf, CDC_PRINTBUF_SIZE, _Format, va);
- va_end(va);
-
- CDC_print(printbuf);
-
- return result;
-}
-
-// global "inbuf" if desired
-inbuf_t inbuf;
-
-uint32_t CDC_input_buf(inbuf_t inbuf, uint32_t inbuf_size) {
- int RXChar;
- int entered = 0;
-
- if (!udi_cdc_is_rx_ready()) return 0;
- udi_cdc_get_nb_received_data();
- RXChar = udi_cdc_getc();
-
- if (RXChar) {
- switch (RXChar) {
- case '\t': // tab - repeat last
- inbuf.count = inbuf.lastcount;
- inbuf.buf[inbuf.count + 1] = 0;
- CDC_print(inbuf.buf);
- break;
- case '\r': // enter
- inbuf.buf[inbuf.count] = 0;
- inbuf.lastcount = inbuf.count;
- inbuf.count = 0;
- entered = 1;
- break;
- case '\b': // backspace
- if (inbuf.count > 0) {
- inbuf.count -= 1;
- CDC_print("\b \b\0");
- } else
- CDC_print("\a\0");
- break;
- default:
- if ((RXChar >= 32) && (RXChar <= 126)) {
- if (inbuf.count < inbuf_size - 1) {
- inbuf.buf[inbuf.count] = RXChar;
- inbuf.buf[inbuf.count + 1] = 0;
- CDC_print(&inbuf.buf[inbuf.count]);
- inbuf.count += 1;
- } else
- CDC_print("\a\0");
- }
- break;
- }
- RXChar = 0;
- }
- return entered;
-}
-
-uint32_t CDC_input() {
- return CDC_input_buf(inbuf, CDC_INBUF_SIZE);
-}
-
-void CDC_init(void) {
- inbuf.count = 0;
- inbuf.lastcount = 0;
- printbuf[0] = 0;
- cdc_tx_send_time_next = timer_read64() + CDC_SEND_INTERVAL;
-}
-
-#else // CDC line 62
-
-char printbuf[CDC_PRINTBUF_SIZE];
-
-void CDC_send(void) {
- return;
-}
-
-uint32_t CDC_print(char *printbuf) {
- return 0;
-}
-
-int CDC_printf(const char *_Format, ...) {
- return 0;
-}
-
-inbuf_t inbuf;
-
-uint32_t CDC_input(void) {
- return 0;
-}
-
-void CDC_init(void) {
- inbuf.count = 0;
- inbuf.lastcount = 0;
- printbuf[0] = 0;
-}
-
-#endif // CDC line 62
-
-//@}
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_cdc.h b/tmk_core/protocol/arm_atsam/usb/udi_cdc.h
deleted file mode 100644
index ff4f521ce011..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_cdc.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device Communication Device Class (CDC) interface definitions.
- *
- * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDI_CDC_H_
-#define _UDI_CDC_H_
-
-#ifdef VIRTSER_ENABLE
-
-# include "conf_usb.h"
-# include "usb_protocol.h"
-# include "usb_protocol_cdc.h"
-# include "udd.h"
-# include "udc_desc.h"
-# include "udi.h"
-
-// Check the number of port
-# ifndef UDI_CDC_PORT_NB
-# define UDI_CDC_PORT_NB 1
-# endif
-# if (UDI_CDC_PORT_NB > 1)
-# error UDI_CDC_PORT_NB must be at most 1
-# endif
-
-# ifdef __cplusplus
-extern "C" {
-# endif
-
-/**
- * \addtogroup udi_cdc_group_udc
- * @{
- */
-
-//! Global structure which contains standard UDI API for UDC
-extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm;
-extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_data;
-//@}
-
-//#define CDC_ACM_SIZE 64 see usb_protocol_cdc.h
-//#define CDC_RX_SIZE 64
-
-//! CDC communication endpoints size for all speeds
-# define UDI_CDC_COMM_EP_SIZE CDC_ACM_SIZE
-//! CDC data endpoints size for FS speed (8B, 16B, 32B, 64B)
-# define UDI_CDC_DATA_EPS_FS_SIZE CDC_RX_SIZE
-
-//@}
-
-/**
- * \ingroup udi_group
- * \defgroup udi_cdc_group USB Device Interface (UDI) for Communication Class Device (CDC)
- *
- * Common APIs used by high level application to use this USB class.
- *
- * These routines are used to transfer and control data
- * to/from USB CDC endpoint.
- *
- * See \ref udi_cdc_quickstart.
- * @{
- */
-
-/**
- * \name Interface for application with single CDC interface support
- */
-//@{
-
-/**
- * \brief Notify a state change of DCD signal
- *
- * \param b_set DCD is enabled if true, else disabled
- */
-void udi_cdc_ctrl_signal_dcd(bool b_set);
-
-/**
- * \brief Notify a state change of DSR signal
- *
- * \param b_set DSR is enabled if true, else disabled
- */
-void udi_cdc_ctrl_signal_dsr(bool b_set);
-
-/**
- * \brief Notify a framing error
- */
-void udi_cdc_signal_framing_error(void);
-
-/**
- * \brief Notify a parity error
- */
-void udi_cdc_signal_parity_error(void);
-
-/**
- * \brief Notify a overrun
- */
-void udi_cdc_signal_overrun(void);
-
-/**
- * \brief Gets the number of byte received
- *
- * \return the number of data available
- */
-iram_size_t udi_cdc_get_nb_received_data(void);
-
-/**
- * \brief This function checks if a character has been received on the CDC line
- *
- * \return \c 1 if a byte is ready to be read.
- */
-bool udi_cdc_is_rx_ready(void);
-
-/**
- * \brief Waits and gets a value on CDC line
- *
- * \return value read on CDC line
- */
-int udi_cdc_getc(void);
-
-/**
- * \brief Reads a RAM buffer on CDC line
- *
- * \param buf Values read
- * \param size Number of value read
- *
- * \return the number of data remaining
- */
-iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size);
-
-/**
- * \brief Non polling reads of a up to 'size' data from CDC line
- *
- * \param port Communication port number to manage
- * \param buf Buffer where to store read data
- * \param size Maximum number of data to read (size of buffer)
- *
- * \return the number of data effectively read
- */
-iram_size_t udi_cdc_read_no_polling(void* buf, iram_size_t size);
-
-/**
- * \brief Gets the number of free byte in TX buffer
- *
- * \return the number of free byte in TX buffer
- */
-iram_size_t udi_cdc_get_free_tx_buffer(void);
-
-/**
- * \brief This function checks if a new character sent is possible
- * The type int is used to support scanf redirection from compiler LIB.
- *
- * \return \c 1 if a new character can be sent
- */
-bool udi_cdc_is_tx_ready(void);
-
-/**
- * \brief Puts a byte on CDC line
- * The type int is used to support printf redirection from compiler LIB.
- *
- * \param value Value to put
- *
- * \return \c 1 if function was successfully done, otherwise \c 0.
- */
-int udi_cdc_putc(int value);
-
-/**
- * \brief Writes a RAM buffer on CDC line
- *
- * \param buf Values to write
- * \param size Number of value to write
- *
- * \return the number of data remaining
- */
-iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size);
-//@}
-
-/**
- * \name Interface for application with multi CDC interfaces support
- */
-//@{
-
-/**
- * \brief Notify a state change of DCD signal
- *
- * \param port Communication port number to manage
- * \param b_set DCD is enabled if true, else disabled
- */
-void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set);
-
-/**
- * \brief Notify a state change of DSR signal
- *
- * \param port Communication port number to manage
- * \param b_set DSR is enabled if true, else disabled
- */
-void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set);
-
-/**
- * \brief Notify a framing error
- *
- * \param port Communication port number to manage
- */
-void udi_cdc_multi_signal_framing_error(uint8_t port);
-
-/**
- * \brief Notify a parity error
- *
- * \param port Communication port number to manage
- */
-void udi_cdc_multi_signal_parity_error(uint8_t port);
-
-/**
- * \brief Notify a overrun
- *
- * \param port Communication port number to manage
- */
-void udi_cdc_multi_signal_overrun(uint8_t port);
-
-/**
- * \brief Gets the number of byte received
- *
- * \param port Communication port number to manage
- *
- * \return the number of data available
- */
-iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port);
-
-/**
- * \brief This function checks if a character has been received on the CDC line
- *
- * \param port Communication port number to manage
- *
- * \return \c 1 if a byte is ready to be read.
- */
-bool udi_cdc_multi_is_rx_ready(uint8_t port);
-
-/**
- * \brief Waits and gets a value on CDC line
- *
- * \param port Communication port number to manage
- *
- * \return value read on CDC line
- */
-int udi_cdc_multi_getc(uint8_t port);
-
-/**
- * \brief Reads a RAM buffer on CDC line
- *
- * \param port Communication port number to manage
- * \param buf Values read
- * \param size Number of values read
- *
- * \return the number of data remaining
- */
-iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size);
-
-/**
- * \brief Gets the number of free byte in TX buffer
- *
- * \param port Communication port number to manage
- *
- * \return the number of free byte in TX buffer
- */
-iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port);
-
-/**
- * \brief This function checks if a new character sent is possible
- * The type int is used to support scanf redirection from compiler LIB.
- *
- * \param port Communication port number to manage
- *
- * \return \c 1 if a new character can be sent
- */
-bool udi_cdc_multi_is_tx_ready(uint8_t port);
-
-/**
- * \brief Puts a byte on CDC line
- * The type int is used to support printf redirection from compiler LIB.
- *
- * \param port Communication port number to manage
- * \param value Value to put
- *
- * \return \c 1 if function was successfully done, otherwise \c 0.
- */
-int udi_cdc_multi_putc(uint8_t port, int value);
-
-/**
- * \brief Writes a RAM buffer on CDC line
- *
- * \param port Communication port number to manage
- * \param buf Values to write
- * \param size Number of value to write
- *
- * \return the number of data remaining
- */
-iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size);
-//@}
-
-# define CDC_PRINTBUF_SIZE 256
-extern char printbuf[CDC_PRINTBUF_SIZE];
-
-# define CDC_INBUF_SIZE 256
-
-typedef struct {
- uint32_t count;
- uint32_t lastcount;
- char buf[CDC_INBUF_SIZE];
-} inbuf_t;
-
-#else // VIRTSER_ENABLE
-
-// keep these to accommodate calls if remaining
-# define CDC_PRINTBUF_SIZE 1
-extern char printbuf[CDC_PRINTBUF_SIZE];
-
-# define CDC_INBUF_SIZE 1
-
-typedef struct {
- uint32_t count;
- uint32_t lastcount;
- char buf[CDC_INBUF_SIZE];
-} inbuf_t;
-
-extern inbuf_t inbuf;
-
-#endif // VIRTSER_ENABLE
-
-uint32_t CDC_print(char* printbuf);
-int CDC_printf(const char* _Format, ...);
-uint32_t CDC_input(void);
-void CDC_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _UDI_CDC_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_cdc_conf.h b/tmk_core/protocol/arm_atsam/usb/udi_cdc_conf.h
deleted file mode 100644
index e17ed7bf4451..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_cdc_conf.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * \file
- *
- * \brief Default CDC configuration for a USB Device with a single interface
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDI_CDC_CONF_H_
-#define _UDI_CDC_CONF_H_
-
-#include "usb_protocol_cdc.h"
-#include "conf_usb.h"
-#include "udi_device_conf.h"
-
-#ifndef UDI_CDC_PORT_NB
-# define UDI_CDC_PORT_NB 1
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define UDI_CDC_DATA_EP_IN_0 ((CDC_TX_ENDPOINT) | (USB_EP_DIR_IN)) // TX
-#define UDI_CDC_DATA_EP_OUT_0 ((CDC_RX_ENDPOINT) | (USB_EP_DIR_OUT)) // RX
-#define UDI_CDC_COMM_EP_0 ((CDC_ACM_ENDPOINT) | (USB_EP_DIR_IN)) // Notify endpoint
-
-#define UDI_CDC_COMM_IFACE_NUMBER_0 (CDC_STATUS_INTERFACE)
-#define UDI_CDC_DATA_IFACE_NUMBER_0 (CDC_DATA_INTERFACE)
-
-#ifdef __cplusplus
-}
-#endif
-#endif // _UDI_CDC_CONF_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_device_conf.h b/tmk_core/protocol/arm_atsam/usb/udi_device_conf.h
deleted file mode 100644
index a3c6f1c397d0..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_device_conf.h
+++ /dev/null
@@ -1,806 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _UDI_DEVICE_CONF_H_
-#define _UDI_DEVICE_CONF_H_
-
-#include "udi_device_epsize.h"
-#include "usb_protocol.h"
-#include "compiler.h"
-#include "usb_protocol_hid.h"
-
-#ifndef USB_POLLING_INTERVAL_MS
-# define USB_POLLING_INTERVAL_MS 10
-#endif
-
-#ifdef VIRTSER_ENABLE
-// because CDC uses IAD (interface association descriptor
-// per USB Interface Association Descriptor Device Class Code and Use Model 7/23/2003 Rev 1.0)
-# define DEVICE_CLASS 0xEF
-# define DEVICE_SUBCLASS 0x02
-# define DEVICE_PROTOCOL 0x01
-#else
-# define DEVICE_CLASS 0x00
-# define DEVICE_SUBCLASS 0x00
-# define DEVICE_PROTOCOL 0x00
-#endif
-
-/* number of interfaces */
-#define NEXT_INTERFACE_0 0
-
-#define KEYBOARD_INTERFACE NEXT_INTERFACE_0
-#define NEXT_INTERFACE_1 (KEYBOARD_INTERFACE + 1)
-#define UDI_HID_KBD_IFACE_NUMBER KEYBOARD_INTERFACE
-
-// It is important that the Raw HID interface is at a constant
-// interface number, to support Linux/OSX platforms and chrome.hid
-// If Raw HID is enabled, let it be always 1.
-#ifdef RAW_ENABLE
-# define RAW_INTERFACE NEXT_INTERFACE_1
-# define NEXT_INTERFACE_2 (RAW_INTERFACE + 1)
-#else
-# define NEXT_INTERFACE_2 NEXT_INTERFACE_1
-#endif
-
-#ifdef MOUSE_ENABLE
-# define MOUSE_INTERFACE NEXT_INTERFACE_2
-# define UDI_HID_MOU_IFACE_NUMBER MOUSE_INTERFACE
-# define NEXT_INTERFACE_3 (MOUSE_INTERFACE + 1)
-#else
-# define NEXT_INTERFACE_3 NEXT_INTERFACE_2
-#endif
-
-#ifdef EXTRAKEY_ENABLE
-# define EXTRAKEY_INTERFACE NEXT_INTERFACE_3
-# define NEXT_INTERFACE_4 (EXTRAKEY_INTERFACE + 1)
-# define UDI_HID_EXK_IFACE_NUMBER EXTRAKEY_INTERFACE
-#else
-# define NEXT_INTERFACE_4 NEXT_INTERFACE_3
-#endif
-
-#ifdef CONSOLE_ENABLE
-# define CON_INTERFACE NEXT_INTERFACE_4
-# define NEXT_INTERFACE_5 (CON_INTERFACE + 1)
-# define UDI_HID_CON_IFACE_NUMBER CON_INTERFACE
-#else
-# define NEXT_INTERFACE_5 NEXT_INTERFACE_4
-#endif
-
-#ifdef NKRO_ENABLE
-# define NKRO_INTERFACE NEXT_INTERFACE_5
-# define NEXT_INTERFACE_6 (NKRO_INTERFACE + 1)
-# define UDI_HID_NKRO_IFACE_NUMBER NKRO_INTERFACE
-#else
-# define NEXT_INTERFACE_6 NEXT_INTERFACE_5
-#endif
-
-#ifdef MIDI_ENABLE
-# define AC_INTERFACE NEXT_INTERFACE_6
-# define AS_INTERFACE (AC_INTERFACE + 1)
-# define NEXT_INTERFACE_7 (AS_INTERFACE + 1)
-#else
-# define NEXT_INTERFACE_7 NEXT_INTERFACE_6
-#endif
-
-#ifdef VIRTSER_ENABLE
-# define CCI_INTERFACE NEXT_INTERFACE_7
-# define CDI_INTERFACE (CCI_INTERFACE + 1)
-# define NEXT_INTERFACE_8 (CDI_INTERFACE + 1)
-# define CDC_STATUS_INTERFACE CCI_INTERFACE
-# define CDC_DATA_INTERFACE CDI_INTERFACE
-#else
-# define NEXT_INTERFACE_8 NEXT_INTERFACE_7
-#endif
-
-/* nubmer of interfaces */
-#define TOTAL_INTERFACES NEXT_INTERFACE_8
-#define USB_DEVICE_NB_INTERFACE TOTAL_INTERFACES
-
-// **********************************************************************
-// Endopoint number and size
-// **********************************************************************
-#define USB_DEVICE_EP_CTRL_SIZE 8
-
-#define NEXT_IN_EPNUM_0 1
-#define NEXT_OUT_EPNUM_0 1
-
-#define KEYBOARD_IN_EPNUM NEXT_IN_EPNUM_0
-#define UDI_HID_KBD_EP_IN KEYBOARD_IN_EPNUM
-#define NEXT_IN_EPNUM_1 (KEYBOARD_IN_EPNUM + 1)
-#define UDI_HID_KBD_EP_SIZE KEYBOARD_EPSIZE
-#define KBD_POLLING_INTERVAL USB_POLLING_INTERVAL_MS
-#ifndef UDI_HID_KBD_STRING_ID
-# define UDI_HID_KBD_STRING_ID 0
-#endif
-
-#ifdef MOUSE_ENABLE
-# define MOUSE_IN_EPNUM NEXT_IN_EPNUM_1
-# define NEXT_IN_EPNUM_2 (MOUSE_IN_EPNUM + 1)
-# define UDI_HID_MOU_EP_IN MOUSE_IN_EPNUM
-# define UDI_HID_MOU_EP_SIZE MOUSE_EPSIZE
-# define MOU_POLLING_INTERVAL USB_POLLING_INTERVAL_MS
-# ifndef UDI_HID_MOU_STRING_ID
-# define UDI_HID_MOU_STRING_ID 0
-# endif
-#else
-# define NEXT_IN_EPNUM_2 NEXT_IN_EPNUM_1
-#endif
-
-#ifdef EXTRAKEY_ENABLE
-# define EXTRAKEY_IN_EPNUM NEXT_IN_EPNUM_2
-# define UDI_HID_EXK_EP_IN EXTRAKEY_IN_EPNUM
-# define NEXT_IN_EPNUM_3 (EXTRAKEY_IN_EPNUM + 1)
-# define UDI_HID_EXK_EP_SIZE EXTRAKEY_EPSIZE
-# define EXTRAKEY_POLLING_INTERVAL USB_POLLING_INTERVAL_MS
-# ifndef UDI_HID_EXK_STRING_ID
-# define UDI_HID_EXK_STRING_ID 0
-# endif
-#else
-# define NEXT_IN_EPNUM_3 NEXT_IN_EPNUM_2
-#endif
-
-#ifdef RAW_ENABLE
-# define RAW_IN_EPNUM NEXT_IN_EPNUM_3
-# define UDI_HID_RAW_EP_IN RAW_IN_EPNUM
-# define NEXT_IN_EPNUM_4 (RAW_IN_EPNUM + 1)
-# define RAW_OUT_EPNUM NEXT_OUT_EPNUM_0
-# define UDI_HID_RAW_EP_OUT RAW_OUT_EPNUM
-# define NEXT_OUT_EPNUM_1 (RAW_OUT_EPNUM + 1)
-# define RAW_POLLING_INTERVAL 1
-# ifndef UDI_HID_RAW_STRING_ID
-# define UDI_HID_RAW_STRING_ID 0
-# endif
-#else
-# define NEXT_IN_EPNUM_4 NEXT_IN_EPNUM_3
-# define NEXT_OUT_EPNUM_1 NEXT_OUT_EPNUM_0
-#endif
-
-#ifdef CONSOLE_ENABLE
-# define CON_IN_EPNUM NEXT_IN_EPNUM_4
-# define UDI_HID_CON_EP_IN CON_IN_EPNUM
-# define NEXT_IN_EPNUM_5 (CON_IN_EPNUM + 1)
-# define CON_OUT_EPNUM NEXT_OUT_EPNUM_1
-# define UDI_HID_CON_EP_OUT CON_OUT_EPNUM
-# define NEXT_OUT_EPNUM_2 (CON_OUT_EPNUM + 1)
-# define CON_POLLING_INTERVAL 1
-# ifndef UDI_HID_CON_STRING_ID
-# define UDI_HID_CON_STRING_ID 0
-# endif
-#else
-# define NEXT_IN_EPNUM_5 NEXT_IN_EPNUM_4
-# define NEXT_OUT_EPNUM_2 NEXT_OUT_EPNUM_1
-#endif
-
-#ifdef NKRO_ENABLE
-# define NKRO_IN_EPNUM NEXT_IN_EPNUM_5
-# define UDI_HID_NKRO_EP_IN NKRO_IN_EPNUM
-# define NEXT_IN_EPNUM_6 (NKRO_IN_EPNUM + 1)
-# define UDI_HID_NKRO_EP_SIZE NKRO_EPSIZE
-# define NKRO_POLLING_INTERVAL 1
-# ifndef UDI_HID_NKRO_STRING_ID
-# define UDI_HID_NKRO_STRING_ID 0
-# endif
-#else
-# define NEXT_IN_EPNUM_6 NEXT_IN_EPNUM_5
-#endif
-
-#ifdef MIDI_ENABLE
-# define MIDI_STREAM_IN_EPNUM NEXT_IN_EPNUM_6
-# define NEXT_IN_EPNUM_7 (MIDI_STREAM_IN_EPNUM + 1)
-# define MIDI_STREAM_OUT_EPNUM NEXT_OUT_EPNUM_2
-# define NEXT_OUT_EPNUM_3 (MIDI_STREAM_OUT_EPNUM + 1)
-# define MIDI_POLLING_INTERVAL 5
-#else
-# define NEXT_IN_EPNUM_7 NEXT_IN_EPNUM_6
-# define NEXT_OUT_EPNUM_3 NEXT_OUT_EPNUM_2
-#endif
-
-#ifdef VIRTSER_ENABLE
-# define CDC_NOTIFICATION_EPNUM NEXT_IN_EPNUM_7
-# define CDC_ACM_ENDPOINT CDC_NOTIFICATION_EPNUM
-# define CDC_TX_ENDPOINT (CDC_NOTIFICATION_EPNUM + 1)
-# define NEXT_IN_EPNUM_8 (CDC_TX_ENDPOINT + 1)
-
-# define CDC_OUT_EPNUM NEXT_OUT_EPNUM_3
-# define CDC_RX_ENDPOINT CDC_OUT_EPNUM
-# define NEXT_OUT_EPNUM_4 (CDC_OUT_EPNUM + 1)
-
-# define CDC_ACM_SIZE CDC_NOTIFICATION_EPSIZE
-# define CDC_RX_SIZE CDC_EPSIZE // KFSMOD was 64
-# define CDC_TX_SIZE CDC_RX_SIZE
-# define CDC_ACM_POLLING_INTERVAL 255
-# define CDC_EP_INTERVAL_STATUS CDC_ACM_POLLING_INTERVAL
-# define CDC_DATA_POLLING_INTERVAL 5
-# define CDC_EP_INTERVAL_DATA CDC_DATA_POLLING_INTERVAL
-# define CDC_STATUS_NAME L"Virtual Serial Port - Status"
-# define CDC_DATA_NAME L"Virtual Serial Port - Data"
-#else
-# define NEXT_IN_EPNUM_8 NEXT_IN_EPNUM_7
-# define NEXT_OUT_EPNUM_4 NEXT_OUT_EPNUM_3
-#endif
-
-#define TOTAL_OUT_EP NEXT_OUT_EPNUM_4
-#define TOTAL_IN_EP NEXT_IN_EPNUM_8
-#define USB_DEVICE_MAX_EP (max(NEXT_OUT_EPNUM_4, NEXT_IN_EPNUM_8))
-
-#if USB_DEVICE_MAX_EP > 8
-# error "There are not enough available endpoints to support all functions. Remove some in the rules.mk file.(MOUSEKEY, EXTRAKEY, CONSOLE, NKRO, MIDI, VIRTSER)"
-#endif
-
-// **********************************************************************
-// KBD Descriptor structure and content
-// **********************************************************************
-COMPILER_PACK_SET(1)
-
-typedef struct {
- usb_iface_desc_t iface;
- usb_hid_descriptor_t hid;
- usb_ep_desc_t ep;
-} udi_hid_kbd_desc_t;
-
-typedef struct {
- uint8_t array[59];
-} udi_hid_kbd_report_desc_t;
-
-// clang-format off
-
-# define UDI_HID_KBD_DESC { \
- .iface = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = UDI_HID_KBD_IFACE_NUMBER, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 1, \
- .bInterfaceClass = HID_CLASS, \
- .bInterfaceSubClass = HID_SUB_CLASS_BOOT, \
- .bInterfaceProtocol = HID_PROTOCOL_KEYBOARD, \
- .iInterface = UDI_HID_KBD_STRING_ID, \
- }, \
- .hid = { \
- .bLength = sizeof(usb_hid_descriptor_t), \
- .bDescriptorType = USB_DT_HID, \
- .bcdHID = LE16(USB_HID_BDC_V1_11), \
- .bCountryCode = USB_HID_NO_COUNTRY_CODE, \
- .bNumDescriptors = USB_HID_NUM_DESC, \
- .bRDescriptorType = USB_DT_HID_REPORT, \
- .wDescriptorLength = LE16(sizeof(udi_hid_kbd_report_desc_t)), \
- }, \
- .ep = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_KBD_EP_IN | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(UDI_HID_KBD_EP_SIZE), \
- .bInterval = KBD_POLLING_INTERVAL \
- } \
-}
-
-// clang-format on
-
-// set report buffer (from host)
-extern uint8_t udi_hid_kbd_report_set;
-
-// report buffer (to host)
-#define UDI_HID_KBD_REPORT_SIZE 8
-extern uint8_t udi_hid_kbd_report[UDI_HID_KBD_REPORT_SIZE];
-
-COMPILER_PACK_RESET()
-
-// **********************************************************************
-// EXK Descriptor structure and content
-// **********************************************************************
-#ifdef EXTRAKEY_ENABLE
-
-COMPILER_PACK_SET(1)
-
-typedef struct {
- usb_iface_desc_t iface;
- usb_hid_descriptor_t hid;
- usb_ep_desc_t ep;
-} udi_hid_exk_desc_t;
-
-typedef struct {
- uint8_t array[50];
-} udi_hid_exk_report_desc_t;
-
-// clang-format off
-
-# define UDI_HID_EXK_DESC { \
- .iface = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = UDI_HID_EXK_IFACE_NUMBER, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 1, \
- .bInterfaceClass = HID_CLASS, \
- .bInterfaceSubClass = HID_SUB_CLASS_BOOT, \
- .bInterfaceProtocol = HID_PROTOCOL_GENERIC, \
- .iInterface = UDI_HID_EXK_STRING_ID \
- }, \
- .hid = { \
- .bLength = sizeof(usb_hid_descriptor_t), \
- .bDescriptorType = USB_DT_HID, \
- .bcdHID = LE16(USB_HID_BDC_V1_11), \
- .bCountryCode = USB_HID_NO_COUNTRY_CODE, \
- .bNumDescriptors = USB_HID_NUM_DESC, \
- .bRDescriptorType = USB_DT_HID_REPORT, \
- .wDescriptorLength = LE16(sizeof(udi_hid_exk_report_desc_t)) \
- }, \
- .ep = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_EXK_EP_IN | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(UDI_HID_EXK_EP_SIZE), \
- .bInterval = EXTRAKEY_POLLING_INTERVAL \
- } \
-}
-
-// clang-format on
-
-// report buffer
-# define UDI_HID_EXK_REPORT_SIZE 3
-extern uint8_t udi_hid_exk_report[UDI_HID_EXK_REPORT_SIZE];
-
-COMPILER_PACK_RESET()
-
-#endif // EXTRAKEY_ENABLE
-
-// **********************************************************************
-// NKRO Descriptor structure and content
-// **********************************************************************
-#ifdef NKRO_ENABLE
-
-COMPILER_PACK_SET(1)
-
-typedef struct {
- usb_iface_desc_t iface;
- usb_hid_descriptor_t hid;
- usb_ep_desc_t ep;
-} udi_hid_nkro_desc_t;
-
-typedef struct {
- uint8_t array[57];
-} udi_hid_nkro_report_desc_t;
-
-// clang-format off
-
-# define UDI_HID_NKRO_DESC { \
- .iface = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = UDI_HID_NKRO_IFACE_NUMBER, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 1, \
- .bInterfaceClass = HID_CLASS, \
- .bInterfaceSubClass = HID_SUB_CLASS_NOBOOT, \
- .bInterfaceProtocol = HID_PROTOCOL_KEYBOARD, \
- .iInterface = UDI_HID_NKRO_STRING_ID \
- }, \
- .hid = { \
- .bLength = sizeof(usb_hid_descriptor_t), \
- .bDescriptorType = USB_DT_HID, \
- .bcdHID = LE16(USB_HID_BDC_V1_11), \
- .bCountryCode = USB_HID_NO_COUNTRY_CODE, \
- .bNumDescriptors = USB_HID_NUM_DESC, \
- .bRDescriptorType = USB_DT_HID_REPORT, \
- .wDescriptorLength = LE16(sizeof(udi_hid_nkro_report_desc_t)) \
- }, \
- .ep = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_NKRO_EP_IN | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(UDI_HID_NKRO_EP_SIZE), \
- .bInterval = NKRO_POLLING_INTERVAL \
- } \
-}
-
-// clang-format on
-
-// set report buffer
-extern uint8_t udi_hid_nkro_report_set;
-
-// report buffer
-# define UDI_HID_NKRO_REPORT_SIZE 32
-extern uint8_t udi_hid_nkro_report[UDI_HID_NKRO_REPORT_SIZE];
-
-COMPILER_PACK_RESET()
-
-#endif // NKRO_ENABLE
-
-// **********************************************************************
-// MOU Descriptor structure and content
-// **********************************************************************
-#ifdef MOUSE_ENABLE
-
-COMPILER_PACK_SET(1)
-
-typedef struct {
- usb_iface_desc_t iface;
- usb_hid_descriptor_t hid;
- usb_ep_desc_t ep;
-} udi_hid_mou_desc_t;
-
-typedef struct {
- uint8_t array[77]; // MOU PDS
-} udi_hid_mou_report_desc_t;
-
-// clang-format off
-
-# define UDI_HID_MOU_DESC { \
- .iface = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = MOUSE_INTERFACE, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 1, \
- .bInterfaceClass = HID_CLASS, \
- .bInterfaceSubClass = HID_SUB_CLASS_BOOT, \
- .bInterfaceProtocol = HID_PROTOCOL_MOUSE, \
- .iInterface = UDI_HID_MOU_STRING_ID \
- }, \
- .hid = { \
- .bLength = sizeof(usb_hid_descriptor_t), \
- .bDescriptorType = USB_DT_HID, \
- .bcdHID = LE16(USB_HID_BDC_V1_11), \
- .bCountryCode = USB_HID_NO_COUNTRY_CODE, \
- .bNumDescriptors = USB_HID_NUM_DESC, \
- .bRDescriptorType = USB_DT_HID_REPORT, \
- .wDescriptorLength = LE16(sizeof(udi_hid_mou_report_desc_t)) \
- }, \
- .ep = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_MOU_EP_IN | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(UDI_HID_MOU_EP_SIZE), \
- .bInterval = MOU_POLLING_INTERVAL \
- } \
-}
-
-// clang-format on
-
-// report buffer
-# define UDI_HID_MOU_REPORT_SIZE 5 // MOU PDS
-extern uint8_t udi_hid_mou_report[UDI_HID_MOU_REPORT_SIZE];
-
-COMPILER_PACK_RESET()
-
-#endif // MOUSE_ENABLE
-
-// **********************************************************************
-// RAW Descriptor structure and content
-// **********************************************************************
-#ifdef RAW_ENABLE
-
-COMPILER_PACK_SET(1)
-
-typedef struct {
- usb_iface_desc_t iface;
- usb_hid_descriptor_t hid;
- usb_ep_desc_t ep_out;
- usb_ep_desc_t ep_in;
-} udi_hid_raw_desc_t;
-
-typedef struct {
- uint8_t array[26];
-} udi_hid_raw_report_desc_t;
-
-// clang-format off
-
-# define UDI_HID_RAW_DESC { \
- .iface = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = RAW_INTERFACE, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 2, \
- .bInterfaceClass = HID_CLASS, \
- .bInterfaceSubClass = HID_SUB_CLASS_NOBOOT, \
- .bInterfaceProtocol = HID_SUB_CLASS_NOBOOT, \
- .iInterface = UDI_HID_RAW_STRING_ID \
- }, \
- .hid = { \
- .bLength = sizeof(usb_hid_descriptor_t), \
- .bDescriptorType = USB_DT_HID, \
- .bcdHID = LE16(USB_HID_BDC_V1_11), \
- .bCountryCode = USB_HID_NO_COUNTRY_CODE, \
- .bNumDescriptors = USB_HID_NUM_DESC, \
- .bRDescriptorType = USB_DT_HID_REPORT, \
- .wDescriptorLength = LE16(sizeof(udi_hid_raw_report_desc_t)) \
- }, \
- .ep_out = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_RAW_EP_OUT | USB_EP_DIR_OUT, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(RAW_EPSIZE), \
- .bInterval = RAW_POLLING_INTERVAL \
- }, \
- .ep_in = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_RAW_EP_IN | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(RAW_EPSIZE), \
- .bInterval = RAW_POLLING_INTERVAL \
- } \
-}
-
-// clang-format on
-
-# define UDI_HID_RAW_REPORT_SIZE RAW_EPSIZE
-
-extern uint8_t udi_hid_raw_report_set[UDI_HID_RAW_REPORT_SIZE];
-
-// report buffer
-extern uint8_t udi_hid_raw_report[UDI_HID_RAW_REPORT_SIZE];
-
-COMPILER_PACK_RESET()
-
-#endif // RAW_ENABLE
-
-// **********************************************************************
-// CON Descriptor structure and content
-// **********************************************************************
-#ifdef CONSOLE_ENABLE
-
-COMPILER_PACK_SET(1)
-
-typedef struct {
- usb_iface_desc_t iface;
- usb_hid_descriptor_t hid;
- usb_ep_desc_t ep_out;
- usb_ep_desc_t ep_in;
-} udi_hid_con_desc_t;
-
-typedef struct {
- uint8_t array[34];
-} udi_hid_con_report_desc_t;
-
-// clang-format off
-
-# define UDI_HID_CON_DESC { \
- .iface = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = UDI_HID_CON_IFACE_NUMBER, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 2, \
- .bInterfaceClass = HID_CLASS, \
- .bInterfaceSubClass = HID_SUB_CLASS_NOBOOT, \
- .bInterfaceProtocol = HID_SUB_CLASS_NOBOOT, \
- .iInterface = UDI_HID_CON_STRING_ID \
- }, \
- .hid = { \
- .bLength = sizeof(usb_hid_descriptor_t), \
- .bDescriptorType = USB_DT_HID, \
- .bcdHID = LE16(USB_HID_BDC_V1_11), \
- .bCountryCode = USB_HID_NO_COUNTRY_CODE, \
- .bNumDescriptors = USB_HID_NUM_DESC, \
- .bRDescriptorType = USB_DT_HID_REPORT, \
- .wDescriptorLength = LE16(sizeof(udi_hid_con_report_desc_t)) \
- }, \
- .ep_out = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_CON_EP_OUT | USB_EP_DIR_OUT, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(CONSOLE_EPSIZE), \
- .bInterval = CON_POLLING_INTERVAL \
- }, \
- .ep_in = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = UDI_HID_CON_EP_IN | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(CONSOLE_EPSIZE), \
- .bInterval = CON_POLLING_INTERVAL \
- } \
-}
-
-// clang-format on
-
-# define UDI_HID_CON_REPORT_SIZE CONSOLE_EPSIZE
-
-extern uint8_t udi_hid_con_report_set[UDI_HID_CON_REPORT_SIZE];
-
-// report buffer
-extern uint8_t udi_hid_con_report[UDI_HID_CON_REPORT_SIZE];
-
-COMPILER_PACK_RESET()
-
-#endif // CONSOLE_ENABLE
-
-// **********************************************************************
-// CDC Descriptor structure and content
-// **********************************************************************
-#ifdef VIRTSER_ENABLE
-
-COMPILER_PACK_SET(1)
-
-typedef struct {
- uint8_t bFunctionLength;
- uint8_t bDescriptorType;
- uint8_t bDescriptorSubtype;
- le16_t bcdCDC;
-} usb_cdc_hdr_desc_t;
-
-typedef struct {
- uint8_t bFunctionLength;
- uint8_t bDescriptorType;
- uint8_t bDescriptorSubtype;
- uint8_t bmCapabilities;
- uint8_t bDataInterface;
-} usb_cdc_call_mgmt_desc_t;
-
-typedef struct {
- uint8_t bFunctionLength;
- uint8_t bDescriptorType;
- uint8_t bDescriptorSubtype;
- uint8_t bmCapabilities;
-} usb_cdc_acm_desc_t;
-
-typedef struct {
- uint8_t bFunctionLength;
- uint8_t bDescriptorType;
- uint8_t bDescriptorSubtype;
- uint8_t bMasterInterface;
- uint8_t bSlaveInterface0;
-} usb_cdc_union_desc_t;
-
-typedef struct {
- usb_association_desc_t iaface;
- usb_iface_desc_t iface_c;
- usb_cdc_hdr_desc_t fd;
- usb_cdc_call_mgmt_desc_t mfd;
- usb_cdc_acm_desc_t acmd;
- usb_cdc_union_desc_t ufd;
- usb_ep_desc_t ep_c;
- usb_iface_desc_t iface_d;
- usb_ep_desc_t ep_tx;
- usb_ep_desc_t ep_rx;
-} udi_cdc_desc_t;
-
-// clang-format off
-
-# define CDC_DESCRIPTOR { \
- .iaface = { \
- .bLength = sizeof(usb_association_desc_t), \
- .bDescriptorType = USB_DT_IAD, \
- .bFirstInterface = CDC_STATUS_INTERFACE, \
- .bInterfaceCount = 2, \
- .bFunctionClass = CDC_CLASS_DEVICE, \
- .bFunctionSubClass = CDC_SUBCLASS_ACM, \
- .bFunctionProtocol = CDC_PROTOCOL_V25TER, \
- .iFunction = 0 \
- }, \
- .iface_c = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = CDC_STATUS_INTERFACE, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 1, \
- .bInterfaceClass = 0x02, \
- .bInterfaceSubClass = 0x02, \
- .bInterfaceProtocol = CDC_PROTOCOL_V25TER, \
- .iInterface = 0 \
- }, \
- .fd = { \
- .bFunctionLength = sizeof(usb_cdc_hdr_desc_t), \
- .bDescriptorType = CDC_CS_INTERFACE, \
- .bDescriptorSubtype = CDC_SCS_HEADER, \
- .bcdCDC = 0x0110 \
- }, \
- .mfd = { \
- .bFunctionLength = sizeof(usb_cdc_call_mgmt_desc_t), \
- .bDescriptorType = CDC_CS_INTERFACE, \
- .bDescriptorSubtype = CDC_SCS_CALL_MGMT, \
- .bmCapabilities = CDC_CALL_MGMT_SUPPORTED, \
- .bDataInterface = CDC_DATA_INTERFACE \
- }, \
- .acmd = { \
- .bFunctionLength = sizeof(usb_cdc_acm_desc_t), \
- .bDescriptorType = CDC_CS_INTERFACE, \
- .bDescriptorSubtype = CDC_SCS_ACM, \
- .bmCapabilities = CDC_ACM_SUPPORT_LINE_REQUESTS \
- }, \
- .ufd = { \
- .bFunctionLength = sizeof(usb_cdc_union_desc_t), \
- .bDescriptorType = CDC_CS_INTERFACE, \
- .bDescriptorSubtype = CDC_SCS_UNION, \
- .bMasterInterface = CDC_STATUS_INTERFACE, \
- .bSlaveInterface0 = CDC_DATA_INTERFACE \
- }, \
- .ep_c = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = CDC_ACM_ENDPOINT | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_INTERRUPT, \
- .wMaxPacketSize = LE16(CDC_ACM_SIZE), \
- .bInterval = CDC_EP_INTERVAL_STATUS \
- }, \
- .iface_d = { \
- .bLength = sizeof(usb_iface_desc_t), \
- .bDescriptorType = USB_DT_INTERFACE, \
- .bInterfaceNumber = CDC_DATA_INTERFACE, \
- .bAlternateSetting = 0, \
- .bNumEndpoints = 2, \
- .bInterfaceClass = CDC_CLASS_DATA, \
- .bInterfaceSubClass = 0, \
- .bInterfaceProtocol = 0, \
- .iInterface = 0 \
- }, \
- .ep_rx = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = CDC_RX_ENDPOINT | USB_EP_DIR_OUT, \
- .bmAttributes = USB_EP_TYPE_BULK, \
- .wMaxPacketSize = LE16(CDC_RX_SIZE), \
- .bInterval = CDC_EP_INTERVAL_DATA \
- }, \
- .ep_tx = { \
- .bLength = sizeof(usb_ep_desc_t), \
- .bDescriptorType = USB_DT_ENDPOINT, \
- .bEndpointAddress = CDC_TX_ENDPOINT | USB_EP_DIR_IN, \
- .bmAttributes = USB_EP_TYPE_BULK, \
- .wMaxPacketSize = LE16(CDC_TX_SIZE), \
- .bInterval = CDC_EP_INTERVAL_DATA \
- } \
-}
-
-// clang-format on
-
-COMPILER_PACK_RESET()
-
-#endif // VIRTSER_ENABLE
-
-// **********************************************************************
-// CONFIGURATION Descriptor structure and content
-// **********************************************************************
-COMPILER_PACK_SET(1)
-
-typedef struct {
- usb_conf_desc_t conf;
- udi_hid_kbd_desc_t hid_kbd;
-#ifdef MOUSE_ENABLE
- udi_hid_mou_desc_t hid_mou;
-#endif
-#ifdef EXTRAKEY_ENABLE
- udi_hid_exk_desc_t hid_exk;
-#endif
-#ifdef RAW_ENABLE
- udi_hid_raw_desc_t hid_raw;
-#endif
-#ifdef CONSOLE_ENABLE
- udi_hid_con_desc_t hid_con;
-#endif
-#ifdef NKRO_ENABLE
- udi_hid_nkro_desc_t hid_nkro;
-#endif
-#ifdef MIDI_ENABLE
- udi_hid_midi_desc_t hid_midi;
-#endif
-#ifdef VIRTSER_ENABLE
- udi_cdc_desc_t cdc_serial;
-#endif
-} udc_desc_t;
-
-COMPILER_PACK_RESET()
-
-#endif //_UDI_DEVICE_CONF_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_device_epsize.h b/tmk_core/protocol/arm_atsam/usb/udi_device_epsize.h
deleted file mode 100644
index 47bd02c07439..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_device_epsize.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _UDI_DEVICE_EPSIZE_H_
-#define _UDI_DEVICE_EPSIZE_H_
-
-#define KEYBOARD_EPSIZE 8
-#define MOUSE_EPSIZE 16
-#define EXTRAKEY_EPSIZE 8
-#define RAW_EPSIZE 32
-#define CONSOLE_EPSIZE 32
-#define NKRO_EPSIZE 32
-#define MIDI_STREAM_EPSIZE 64
-#define CDC_NOTIFICATION_EPSIZE 8
-#define CDC_EPSIZE 16
-
-#endif //_UDI_DEVICE_EPSIZE_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_hid.c b/tmk_core/protocol/arm_atsam/usb/udi_hid.c
deleted file mode 100644
index 73e384a03927..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_hid.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device Human Interface Device (HID) interface.
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "udd.h"
-#include "udc.h"
-#include "udi_hid.h"
-
-/**
- * \ingroup udi_hid_group
- * \defgroup udi_hid_group_internal Implementation of HID common library
- * @{
- */
-
-/**
- * \brief Send the specific descriptors requested by SETUP request
- *
- * \retval true if the descriptor is supported
- */
-static bool udi_hid_reqstdifaceget_descriptor(uint8_t *report_desc);
-
-bool udi_hid_setup(uint8_t *rate, uint8_t *protocol, uint8_t *report_desc, bool (*setup_report)(void)) {
- if (Udd_setup_is_in()) {
- // Requests Interface GET
- if (Udd_setup_type() == USB_REQ_TYPE_STANDARD) {
- // Requests Standard Interface Get
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_GET_DESCRIPTOR:
- return udi_hid_reqstdifaceget_descriptor(report_desc);
- }
- }
- if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
- // Requests Class Interface Get
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_HID_GET_REPORT:
- return setup_report();
-
- case USB_REQ_HID_GET_IDLE:
- udd_g_ctrlreq.payload = rate;
- udd_g_ctrlreq.payload_size = 1;
- return true;
-
- case USB_REQ_HID_GET_PROTOCOL:
- udd_g_ctrlreq.payload = protocol;
- udd_g_ctrlreq.payload_size = 1;
- return true;
- }
- }
- }
- if (Udd_setup_is_out()) {
- // Requests Interface SET
- if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
- // Requests Class Interface Set
- switch (udd_g_ctrlreq.req.bRequest) {
- case USB_REQ_HID_SET_REPORT:
- return setup_report();
-
- case USB_REQ_HID_SET_IDLE:
- *rate = udd_g_ctrlreq.req.wValue >> 8;
- return true;
-
- case USB_REQ_HID_SET_PROTOCOL:
- if (0 != udd_g_ctrlreq.req.wLength) return false;
- *protocol = udd_g_ctrlreq.req.wValue;
- return true;
- }
- }
- }
- return false; // Request not supported
-}
-
-//---------------------------------------------
-//------- Internal routines
-
-static bool udi_hid_reqstdifaceget_descriptor(uint8_t *report_desc) {
- usb_hid_descriptor_t UDC_DESC_STORAGE *ptr_hid_desc;
-
- // Get the USB descriptor which is located after the interface descriptor
- // This descriptor must be the HID descriptor
- ptr_hid_desc = (usb_hid_descriptor_t UDC_DESC_STORAGE *)((uint8_t *)udc_get_interface_desc() + sizeof(usb_iface_desc_t));
- if (USB_DT_HID != ptr_hid_desc->bDescriptorType) return false;
-
- // The SETUP request can ask for:
- // - an USB_DT_HID descriptor
- // - or USB_DT_HID_REPORT descriptor
- // - or USB_DT_HID_PHYSICAL descriptor
- if (USB_DT_HID == (uint8_t)(udd_g_ctrlreq.req.wValue >> 8)) {
- // USB_DT_HID descriptor requested then send it
- udd_g_ctrlreq.payload = (uint8_t *)ptr_hid_desc;
- udd_g_ctrlreq.payload_size = min(udd_g_ctrlreq.req.wLength, ptr_hid_desc->bLength);
- return true;
- }
- // The HID_X descriptor requested must correspond to report type
- // included in the HID descriptor
- if (ptr_hid_desc->bRDescriptorType == (uint8_t)(udd_g_ctrlreq.req.wValue >> 8)) {
- // Send HID Report descriptor given by high level
- udd_g_ctrlreq.payload = report_desc;
- udd_g_ctrlreq.payload_size = min(udd_g_ctrlreq.req.wLength, le16_to_cpu(ptr_hid_desc->wDescriptorLength));
- return true;
- }
- return false;
-}
-
-//@}
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_hid.h b/tmk_core/protocol/arm_atsam/usb/udi_hid.h
deleted file mode 100644
index a08b7db744c8..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_hid.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device Human Interface Device (HID) interface definitions.
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDI_HID_H_
-#define _UDI_HID_H_
-
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "usb_protocol_hid.h"
-#include "udd.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \ingroup udi_group
- * \defgroup udi_hid_group USB Device Interface (UDI) for Human Interface Device (HID)
- *
- * Common library for all Human Interface Device (HID) implementation.
- *
- * @{
- */
-
-/**
- * \brief Decode HID setup request
- *
- * \param rate Pointer on rate of current HID interface
- * \param protocol Pointer on protocol of current HID interface
- * \param report_desc Pointer on report descriptor of current HID interface
- * \param set_report Pointer on set_report callback of current HID interface
- *
- * \return \c 1 if function was successfully done, otherwise \c 0.
- */
-bool udi_hid_setup(uint8_t *rate, uint8_t *protocol, uint8_t *report_desc, bool (*setup_report)(void));
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-#endif // _UDI_HID_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.c b/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.c
deleted file mode 100644
index bf190b1f1812..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device Human Interface Device (HID) keyboard interface.
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#include "samd51j18a.h"
-#include "d51_util.h"
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "udd.h"
-#include "udc.h"
-#include "udi_device_conf.h"
-#include "udi_hid.h"
-#include "udi_hid_kbd.h"
-#include
-#include "report.h"
-#include "usb_descriptor_common.h"
-
-//***************************************************************************
-// KBD
-//***************************************************************************
-bool udi_hid_kbd_enable(void);
-void udi_hid_kbd_disable(void);
-bool udi_hid_kbd_setup(void);
-uint8_t udi_hid_kbd_getsetting(void);
-
-UDC_DESC_STORAGE udi_api_t udi_api_hid_kbd = {
- .enable = (bool (*)(void))udi_hid_kbd_enable,
- .disable = (void (*)(void))udi_hid_kbd_disable,
- .setup = (bool (*)(void))udi_hid_kbd_setup,
- .getsetting = (uint8_t(*)(void))udi_hid_kbd_getsetting,
- .sof_notify = NULL,
-};
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_kbd_rate;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_kbd_protocol;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_kbd_report_set;
-
-bool udi_hid_kbd_b_report_valid;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_kbd_report[UDI_HID_KBD_REPORT_SIZE];
-
-volatile bool udi_hid_kbd_b_report_trans_ongoing;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_kbd_report_trans[UDI_HID_KBD_REPORT_SIZE];
-
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE udi_hid_kbd_report_desc_t udi_hid_kbd_report_desc = {{
- 0x05, 0x01, // Usage Page (Generic Desktop)
- 0x09, 0x06, // Usage (Keyboard)
- 0xA1, 0x01, // Collection (Application)
- // Modifiers (8 bits)
- 0x05, 0x07, // Usage Page (Keyboard)
- 0x19, 0xE0, // Usage Minimum (Keyboard Left Control)
- 0x29, 0xE7, // Usage Maximum (Keyboard Right GUI)
- 0x15, 0x00, // Logical Minimum (0)
- 0x25, 0x01, // Logical Maximum (1)
- 0x95, 0x08, // Report Count (8)
- 0x75, 0x01, // Report Size (1)
- 0x81, 0x02, // Input (Data, Variable, Absolute)
- // Reserved (1 byte)
- 0x81, 0x01, // Input (Constant)
- // Keycodes (6 bytes)
- 0x19, 0x00, // Usage Minimum (0)
- 0x29, 0xFF, // Usage Maximum (255)
- 0x15, 0x00, // Logical Minimum (0)
- 0x25, 0xFF, // Logical Maximum (255)
- 0x95, 0x06, // Report Count (6)
- 0x75, 0x08, // Report Size (8)
- 0x81, 0x00, // Input (Data, Array, Absolute)
-
- // Status LEDs (5 bits)
- 0x05, 0x08, // Usage Page (LED)
- 0x19, 0x01, // Usage Minimum (Num Lock)
- 0x29, 0x05, // Usage Maximum (Kana)
- 0x15, 0x00, // Logical Minimum (0)
- 0x25, 0x01, // Logical Maximum (1)
- 0x95, 0x05, // Report Count (5)
- 0x75, 0x01, // Report Size (1)
- 0x91, 0x02, // Output (Data, Variable, Absolute)
- // LED padding (3 bits)
- 0x95, 0x03, // Report Count (3)
- 0x91, 0x01, // Output (Constant)
- 0xC0 // End Collection
-}};
-
-static bool udi_hid_kbd_setreport(void);
-
-static void udi_hid_kbd_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep);
-
-static void udi_hid_kbd_setreport_valid(void);
-
-bool udi_hid_kbd_enable(void) {
- // Initialize internal values
- udi_hid_kbd_rate = 0;
- udi_hid_kbd_protocol = 0;
- udi_hid_kbd_b_report_trans_ongoing = false;
- memset(udi_hid_kbd_report, 0, UDI_HID_KBD_REPORT_SIZE);
- udi_hid_kbd_b_report_valid = false;
- return UDI_HID_KBD_ENABLE_EXT();
-}
-
-void udi_hid_kbd_disable(void) {
- UDI_HID_KBD_DISABLE_EXT();
-}
-
-bool udi_hid_kbd_setup(void) {
- return udi_hid_setup(&udi_hid_kbd_rate, &udi_hid_kbd_protocol, (uint8_t *)&udi_hid_kbd_report_desc, udi_hid_kbd_setreport);
-}
-
-uint8_t udi_hid_kbd_getsetting(void) {
- return 0;
-}
-
-static bool udi_hid_kbd_setreport(void) {
- if ((USB_HID_REPORT_TYPE_OUTPUT == (udd_g_ctrlreq.req.wValue >> 8)) && (0 == (0xFF & udd_g_ctrlreq.req.wValue)) && (1 == udd_g_ctrlreq.req.wLength)) {
- // Report OUT type on report ID 0 from USB Host
- udd_g_ctrlreq.payload = &udi_hid_kbd_report_set;
- udd_g_ctrlreq.callback = udi_hid_kbd_setreport_valid;
- udd_g_ctrlreq.payload_size = 1;
- return true;
- }
- return false;
-}
-
-bool udi_hid_kbd_send_report(void) {
- if (!main_b_kbd_enable) {
- return false;
- }
-
- if (udi_hid_kbd_b_report_trans_ongoing) {
- return false;
- }
-
- memcpy(udi_hid_kbd_report_trans, udi_hid_kbd_report, UDI_HID_KBD_REPORT_SIZE);
- udi_hid_kbd_b_report_valid = false;
- udi_hid_kbd_b_report_trans_ongoing = udd_ep_run(UDI_HID_KBD_EP_IN | USB_EP_DIR_IN, false, udi_hid_kbd_report_trans, UDI_HID_KBD_REPORT_SIZE, udi_hid_kbd_report_sent);
-
- return udi_hid_kbd_b_report_trans_ongoing;
-}
-
-static void udi_hid_kbd_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep) {
- UNUSED(status);
- UNUSED(nb_sent);
- UNUSED(ep);
- udi_hid_kbd_b_report_trans_ongoing = false;
- if (udi_hid_kbd_b_report_valid) {
- udi_hid_kbd_send_report();
- }
-}
-
-static void udi_hid_kbd_setreport_valid(void) {
- // UDI_HID_KBD_CHANGE_LED(udi_hid_kbd_report_set);
-}
-
-//********************************************************************************************
-// NKRO Keyboard
-//********************************************************************************************
-#ifdef NKRO_ENABLE
-
-bool udi_hid_nkro_enable(void);
-void udi_hid_nkro_disable(void);
-bool udi_hid_nkro_setup(void);
-uint8_t udi_hid_nkro_getsetting(void);
-
-UDC_DESC_STORAGE udi_api_t udi_api_hid_nkro = {
- .enable = (bool (*)(void))udi_hid_nkro_enable,
- .disable = (void (*)(void))udi_hid_nkro_disable,
- .setup = (bool (*)(void))udi_hid_nkro_setup,
- .getsetting = (uint8_t(*)(void))udi_hid_nkro_getsetting,
- .sof_notify = NULL,
-};
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_nkro_rate;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_nkro_protocol;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_nkro_report_set;
-
-bool udi_hid_nkro_b_report_valid;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_nkro_report[UDI_HID_NKRO_REPORT_SIZE];
-
-volatile bool udi_hid_nkro_b_report_trans_ongoing;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_nkro_report_trans[UDI_HID_NKRO_REPORT_SIZE];
-
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE udi_hid_nkro_report_desc_t udi_hid_nkro_report_desc = {{
- 0x05, 0x01, // Usage Page (Generic Desktop)
- 0x09, 0x06, // Usage (Keyboard)
- 0xA1, 0x01, // Collection (Application)
-
- // Modifiers (8 bits)
- 0x05, 0x07, // Usage Page (Keyboard/Keypad)
- 0x19, 0xE0, // Usage Minimum (Keyboard Left Control)
- 0x29, 0xE7, // Usage Maximum (Keyboard Right GUI)
- 0x15, 0x00, // Logical Minimum (0)
- 0x25, 0x01, // Logical Maximum (1)
- 0x95, 0x08, // Report Count (8)
- 0x75, 0x01, // Report Size (1)
- 0x81, 0x02, // Input (Data, Variable, Absolute)
- // Keycodes
- 0x05, 0x07, // Usage Page (Keyboard/Keypad)
- 0x19, 0x00, // Usage Minimum (0)
- 0x29, 0xF7, // Usage Maximum (247)
- 0x15, 0x00, // Logical Minimum (0)
- 0x25, 0x01, // Logical Maximum (1)
- 0x95, 0xF8, // Report Count (248)
- 0x75, 0x01, // Report Size (1)
- 0x81, 0x02, // Input (Data, Variable, Absolute, Bitfield)
-
- // Status LEDs (5 bits)
- 0x05, 0x08, // Usage Page (LED)
- 0x19, 0x01, // Usage Minimum (Num Lock)
- 0x29, 0x05, // Usage Maximum (Kana)
- 0x95, 0x05, // Report Count (5)
- 0x75, 0x01, // Report Size (1)
- 0x91, 0x02, // Output (Data, Variable, Absolute)
- // LED padding (3 bits)
- 0x95, 0x01, // Report Count (1)
- 0x75, 0x03, // Report Size (3)
- 0x91, 0x03, // Output (Constant)
- 0xC0 // End Collection
-}};
-
-static bool udi_hid_nkro_setreport(void);
-static void udi_hid_nkro_setreport_valid(void);
-static void udi_hid_nkro_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep);
-
-bool udi_hid_nkro_enable(void) {
- // Initialize internal values
- udi_hid_nkro_rate = 0;
- udi_hid_nkro_protocol = 0;
- udi_hid_nkro_b_report_trans_ongoing = false;
- memset(udi_hid_nkro_report, 0, UDI_HID_NKRO_REPORT_SIZE);
- udi_hid_nkro_b_report_valid = false;
- return UDI_HID_NKRO_ENABLE_EXT();
-}
-
-void udi_hid_nkro_disable(void) {
- UDI_HID_NKRO_DISABLE_EXT();
-}
-
-bool udi_hid_nkro_setup(void) {
- return udi_hid_setup(&udi_hid_nkro_rate, &udi_hid_nkro_protocol, (uint8_t *)&udi_hid_nkro_report_desc, udi_hid_nkro_setreport);
-}
-
-uint8_t udi_hid_nkro_getsetting(void) {
- return 0;
-}
-
-// keyboard receives LED report here
-static bool udi_hid_nkro_setreport(void) {
- if ((USB_HID_REPORT_TYPE_OUTPUT == (udd_g_ctrlreq.req.wValue >> 8)) && (0 == (0xFF & udd_g_ctrlreq.req.wValue)) && (1 == udd_g_ctrlreq.req.wLength)) {
- // Report OUT type on report ID 0 from USB Host
- udd_g_ctrlreq.payload = &udi_hid_nkro_report_set;
- udd_g_ctrlreq.callback = udi_hid_nkro_setreport_valid; // must call routine to transform setreport to LED state
- udd_g_ctrlreq.payload_size = 1;
- return true;
- }
- return false;
-}
-
-bool udi_hid_nkro_send_report(void) {
- if (!main_b_nkro_enable) {
- return false;
- }
-
- if (udi_hid_nkro_b_report_trans_ongoing) {
- return false;
- }
-
- memcpy(udi_hid_nkro_report_trans, udi_hid_nkro_report, UDI_HID_NKRO_REPORT_SIZE);
- udi_hid_nkro_b_report_valid = false;
- udi_hid_nkro_b_report_trans_ongoing = udd_ep_run(UDI_HID_NKRO_EP_IN | USB_EP_DIR_IN, false, udi_hid_nkro_report_trans, UDI_HID_NKRO_REPORT_SIZE, udi_hid_nkro_report_sent);
-
- return udi_hid_nkro_b_report_trans_ongoing;
-}
-
-static void udi_hid_nkro_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep) {
- UNUSED(status);
- UNUSED(nb_sent);
- UNUSED(ep);
- udi_hid_nkro_b_report_trans_ongoing = false;
- if (udi_hid_nkro_b_report_valid) {
- udi_hid_nkro_send_report();
- }
-}
-
-static void udi_hid_nkro_setreport_valid(void) {
- // UDI_HID_NKRO_CHANGE_LED(udi_hid_nkro_report_set);
-}
-
-#endif // NKRO_ENABLE
-
-//********************************************************************************************
-// EXK (extra-keys) SYS-CTRL Keyboard
-//********************************************************************************************
-#ifdef EXTRAKEY_ENABLE
-
-bool udi_hid_exk_enable(void);
-void udi_hid_exk_disable(void);
-bool udi_hid_exk_setup(void);
-uint8_t udi_hid_exk_getsetting(void);
-
-UDC_DESC_STORAGE udi_api_t udi_api_hid_exk = {
- .enable = (bool (*)(void))udi_hid_exk_enable,
- .disable = (void (*)(void))udi_hid_exk_disable,
- .setup = (bool (*)(void))udi_hid_exk_setup,
- .getsetting = (uint8_t(*)(void))udi_hid_exk_getsetting,
- .sof_notify = NULL,
-};
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_exk_rate;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_exk_protocol;
-
-// COMPILER_WORD_ALIGNED
-// uint8_t udi_hid_exk_report_set;
-
-bool udi_hid_exk_b_report_valid;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_exk_report[UDI_HID_EXK_REPORT_SIZE];
-
-static bool udi_hid_exk_b_report_trans_ongoing;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_exk_report_trans[UDI_HID_EXK_REPORT_SIZE];
-
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE udi_hid_exk_report_desc_t udi_hid_exk_report_desc = {{
- // clang-format off
- 0x05, 0x01, // Usage Page (Generic Desktop)
- 0x09, 0x80, // Usage (System Control)
- 0xA1, 0x01, // Collection (Application)
- 0x85, REPORT_ID_SYSTEM, // Report ID
- 0x19, 0x01, // Usage Minimum (Pointer)
- 0x2A, 0xB7, 0x00, // Usage Maximum (System Display LCD Autoscale)
- 0x15, 0x01, // Logical Minimum
- 0x26, 0xB7, 0x00, // Logical Maximum
- 0x95, 0x01, // Report Count (1)
- 0x75, 0x10, // Report Size (16)
- 0x81, 0x00, // Input (Data, Array, Absolute)
- 0xC0, // End Collection
-
- 0x05, 0x0C, // Usage Page (Consumer)
- 0x09, 0x01, // Usage (Consumer Control)
- 0xA1, 0x01, // Collection (Application)
- 0x85, REPORT_ID_CONSUMER, // Report ID
- 0x19, 0x01, // Usage Minimum (Consumer Control)
- 0x2A, 0xA0, 0x02, // Usage Maximum (AC Desktop Show All Applications)
- 0x15, 0x01, // Logical Minimum
- 0x26, 0xA0, 0x02, // Logical Maximum
- 0x95, 0x01, // Report Count (1)
- 0x75, 0x10, // Report Size (16)
- 0x81, 0x00, // Input (Data, Array, Absolute)
- 0xC0 // End Collection
- //clang-format on
-}};
-
-static void udi_hid_exk_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep);
-
-bool udi_hid_exk_enable(void) {
- // Initialize internal values
- udi_hid_exk_rate = 0;
- udi_hid_exk_protocol = 0;
- udi_hid_exk_b_report_trans_ongoing = false;
- memset(udi_hid_exk_report, 0, UDI_HID_EXK_REPORT_SIZE);
- udi_hid_exk_b_report_valid = false;
- return UDI_HID_EXK_ENABLE_EXT();
-}
-
-void udi_hid_exk_disable(void) { UDI_HID_EXK_DISABLE_EXT(); }
-
-bool udi_hid_exk_setup(void) { return udi_hid_setup(&udi_hid_exk_rate, &udi_hid_exk_protocol, (uint8_t *)&udi_hid_exk_report_desc, NULL); }
-
-uint8_t udi_hid_exk_getsetting(void) { return 0; }
-
-bool udi_hid_exk_send_report(void) {
- if (!main_b_exk_enable) {
- return false;
- }
-
- if (udi_hid_exk_b_report_trans_ongoing) {
- return false;
- }
-
- memcpy(udi_hid_exk_report_trans, udi_hid_exk_report, UDI_HID_EXK_REPORT_SIZE);
- udi_hid_exk_b_report_valid = false;
- udi_hid_exk_b_report_trans_ongoing = udd_ep_run(UDI_HID_EXK_EP_IN | USB_EP_DIR_IN, false, udi_hid_exk_report_trans, UDI_HID_EXK_REPORT_SIZE, udi_hid_exk_report_sent);
-
- return udi_hid_exk_b_report_trans_ongoing;
-}
-
-static void udi_hid_exk_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep) {
- UNUSED(status);
- UNUSED(nb_sent);
- UNUSED(ep);
- udi_hid_exk_b_report_trans_ongoing = false;
- if (udi_hid_exk_b_report_valid) {
- udi_hid_exk_send_report();
- }
-}
-
-#endif // EXTRAKEY_ENABLE
-
-//********************************************************************************************
-// MOU Mouse
-//********************************************************************************************
-#ifdef MOUSE_ENABLE
-
-bool udi_hid_mou_enable(void);
-void udi_hid_mou_disable(void);
-bool udi_hid_mou_setup(void);
-uint8_t udi_hid_mou_getsetting(void);
-
-UDC_DESC_STORAGE udi_api_t udi_api_hid_mou = {
- .enable = (bool (*)(void))udi_hid_mou_enable,
- .disable = (void (*)(void))udi_hid_mou_disable,
- .setup = (bool (*)(void))udi_hid_mou_setup,
- .getsetting = (uint8_t(*)(void))udi_hid_mou_getsetting,
- .sof_notify = NULL,
-};
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_mou_rate;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_mou_protocol;
-
-// COMPILER_WORD_ALIGNED
-// uint8_t udi_hid_mou_report_set; //No set report
-
-bool udi_hid_mou_b_report_valid;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_mou_report[UDI_HID_MOU_REPORT_SIZE];
-
-static bool udi_hid_mou_b_report_trans_ongoing;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_mou_report_trans[UDI_HID_MOU_REPORT_SIZE];
-
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE udi_hid_mou_report_desc_t udi_hid_mou_report_desc = {{
- 0x05, 0x01, // Usage Page (Generic Desktop)
- 0x09, 0x02, // Usage (Mouse)
- 0xA1, 0x01, // Collection (Application)
- 0x09, 0x01, // Usage (Pointer)
- 0xA1, 0x00, // Collection (Physical)
- // Buttons (5 bits)
- 0x05, 0x09, // Usage Page (Button)
- 0x19, 0x01, // Usage Minimum (Button 1)
- 0x29, 0x05, // Usage Maximun (Button 5)
- 0x15, 0x00, // Logical Minimum (0)
- 0x25, 0x01, // Logical Maximum (1)
- 0x95, 0x05, // Report Count (5)
- 0x75, 0x01, // Report Size (1)
- 0x81, 0x02, // Input (Data, Variable, Absolute)
- // Button padding (3 bits)
- 0x95, 0x01, // Report Count (1)
- 0x75, 0x03, // Report Size (3)
- 0x81, 0x01, // Input (Constant)
-
- // X/Y position (2 bytes)
- 0x05, 0x01, // Usage Page (Generic Desktop)
- 0x09, 0x30, // Usage (X)
- 0x09, 0x31, // Usage (Y)
- 0x15, 0x81, // Logical Minimum (-127)
- 0x25, 0x7F, // Logical Maximum (127)
- 0x95, 0x02, // Report Count (2)
- 0x75, 0x08, // Report Size (8)
- 0x81, 0x06, // Input (Data, Variable, Relative)
-
- // Vertical wheel (1 byte)
- 0x09, 0x38, // Usage (Wheel)
- 0x15, 0x81, // Logical Minimum (-127)
- 0x25, 0x7F, // Logical Maximum (127)
- 0x95, 0x01, // Report Count (1)
- 0x75, 0x08, // Report Size (8)
- 0x81, 0x06, // Input (Data, Variable, Relative)
-
- // Horizontal wheel (1 byte)
- 0x05, 0x0C, // Usage Page (Consumer)
- 0x0A, 0x38, 0x02, // Usage (AC Pan)
- 0x15, 0x81, // Logical Minimum (-127)
- 0x25, 0x7F, // Logical Maximum (127)
- 0x95, 0x01, // Report Count (1)
- 0x75, 0x08, // Report Size (8)
- 0x81, 0x06, // Input (Data, Variable, Relative)
- 0xC0, // End Collection
- 0xC0 // End Collection
-}};
-
-static void udi_hid_mou_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep);
-
-bool udi_hid_mou_enable(void) {
- // Initialize internal values
- udi_hid_mou_rate = 0;
- udi_hid_mou_protocol = 0;
- udi_hid_mou_b_report_trans_ongoing = false;
- memset(udi_hid_mou_report, 0, UDI_HID_MOU_REPORT_SIZE);
- udi_hid_mou_b_report_valid = false;
- return UDI_HID_MOU_ENABLE_EXT();
-}
-
-void udi_hid_mou_disable(void) { UDI_HID_MOU_DISABLE_EXT(); }
-
-bool udi_hid_mou_setup(void) { return udi_hid_setup(&udi_hid_mou_rate, &udi_hid_mou_protocol, (uint8_t *)&udi_hid_mou_report_desc, NULL); }
-
-uint8_t udi_hid_mou_getsetting(void) { return 0; }
-
-bool udi_hid_mou_send_report(void) {
- if (!main_b_mou_enable) {
- return false;
- }
-
- if (udi_hid_mou_b_report_trans_ongoing) {
- return false;
- }
-
- memcpy(udi_hid_mou_report_trans, udi_hid_mou_report, UDI_HID_MOU_REPORT_SIZE);
- udi_hid_mou_b_report_valid = false;
- udi_hid_mou_b_report_trans_ongoing = udd_ep_run(UDI_HID_MOU_EP_IN | USB_EP_DIR_IN, false, udi_hid_mou_report_trans, UDI_HID_MOU_REPORT_SIZE, udi_hid_mou_report_sent);
-
- return udi_hid_mou_b_report_trans_ongoing;
-}
-
-static void udi_hid_mou_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep) {
- UNUSED(status);
- UNUSED(nb_sent);
- UNUSED(ep);
- udi_hid_mou_b_report_trans_ongoing = false;
- if (udi_hid_mou_b_report_valid) {
- udi_hid_mou_send_report();
- }
-}
-
-#endif // MOUSE_ENABLE
-
-//********************************************************************************************
-// RAW
-//********************************************************************************************
-#ifdef RAW_ENABLE
-
-bool udi_hid_raw_enable(void);
-void udi_hid_raw_disable(void);
-bool udi_hid_raw_setup(void);
-uint8_t udi_hid_raw_getsetting(void);
-
-UDC_DESC_STORAGE udi_api_t udi_api_hid_raw = {
- .enable = (bool (*)(void))udi_hid_raw_enable,
- .disable = (void (*)(void))udi_hid_raw_disable,
- .setup = (bool (*)(void))udi_hid_raw_setup,
- .getsetting = (uint8_t(*)(void))udi_hid_raw_getsetting,
- .sof_notify = NULL,
-};
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_raw_rate;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_raw_protocol;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_raw_report_set[UDI_HID_RAW_REPORT_SIZE];
-
-static bool udi_hid_raw_b_report_valid;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_raw_report[UDI_HID_RAW_REPORT_SIZE];
-
-static bool udi_hid_raw_b_report_trans_ongoing;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_raw_report_trans[UDI_HID_RAW_REPORT_SIZE];
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_raw_report_recv[UDI_HID_RAW_REPORT_SIZE];
-
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE udi_hid_raw_report_desc_t udi_hid_raw_report_desc = {{
- 0x06, HID_VALUE_16(RAW_USAGE_PAGE), // Usage Page (Vendor Defined)
- 0x09, RAW_USAGE_ID, // Usage (Vendor Defined)
- 0xA1, 0x01, // Collection (Application)
- 0x75, 0x08, // Report Size (8)
- 0x15, 0x00, // Logical Minimum (0)
- 0x25, 0xFF, // Logical Maximum (255)
- // Data to host
- 0x09, 0x62, // Usage (Vendor Defined)
- 0x95, RAW_EPSIZE, // Report Count
- 0x81, 0x02, // Input (Data, Variable, Absolute)
- // Data from host
- 0x09, 0x63, // Usage (Vendor Defined)
- 0x95, RAW_EPSIZE, // Report Count
- 0x91, 0x02, // Output (Data, Variable, Absolute)
- 0xC0 // End Collection
-}};
-
-static bool udi_hid_raw_setreport(void);
-static void udi_hid_raw_setreport_valid(void);
-
-static void udi_hid_raw_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep);
-static void udi_hid_raw_report_rcvd(udd_ep_status_t status, iram_size_t nb_rcvd, udd_ep_id_t ep);
-
-bool udi_hid_raw_enable(void) {
- // Initialize internal values
- udi_hid_raw_rate = 0;
- udi_hid_raw_protocol = 0;
- udi_hid_raw_b_report_trans_ongoing = false;
- memset(udi_hid_raw_report, 0, UDI_HID_RAW_REPORT_SIZE);
- udi_hid_raw_b_report_valid = false;
- return UDI_HID_RAW_ENABLE_EXT();
-}
-
-void udi_hid_raw_disable(void) { UDI_HID_RAW_DISABLE_EXT(); }
-
-bool udi_hid_raw_setup(void) { return udi_hid_setup(&udi_hid_raw_rate, &udi_hid_raw_protocol, (uint8_t *)&udi_hid_raw_report_desc, udi_hid_raw_setreport); }
-
-uint8_t udi_hid_raw_getsetting(void) { return 0; }
-
-static bool udi_hid_raw_setreport(void) {
- if ((USB_HID_REPORT_TYPE_OUTPUT == (udd_g_ctrlreq.req.wValue >> 8)) && (0 == (0xFF & udd_g_ctrlreq.req.wValue)) && (UDI_HID_RAW_REPORT_SIZE == udd_g_ctrlreq.req.wLength)) {
- // Report OUT type on report ID 0 from USB Host
- udd_g_ctrlreq.payload = udi_hid_raw_report_set;
- udd_g_ctrlreq.callback = udi_hid_raw_setreport_valid; // must call routine to transform setreport to LED state
- udd_g_ctrlreq.payload_size = UDI_HID_RAW_REPORT_SIZE;
- return true;
- }
- return false;
-}
-
-bool udi_hid_raw_send_report(void) {
- if (!main_b_raw_enable) {
- return false;
- }
-
- if (udi_hid_raw_b_report_trans_ongoing) {
- return false;
- }
-
- memcpy(udi_hid_raw_report_trans, udi_hid_raw_report, UDI_HID_RAW_REPORT_SIZE);
- udi_hid_raw_b_report_valid = false;
- udi_hid_raw_b_report_trans_ongoing = udd_ep_run(UDI_HID_RAW_EP_IN | USB_EP_DIR_IN, false, udi_hid_raw_report_trans, UDI_HID_RAW_REPORT_SIZE, udi_hid_raw_report_sent);
-
- return udi_hid_raw_b_report_trans_ongoing;
-}
-
-static void udi_hid_raw_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep) {
- UNUSED(status);
- UNUSED(nb_sent);
- UNUSED(ep);
- udi_hid_raw_b_report_trans_ongoing = false;
- if (udi_hid_raw_b_report_valid) {
- udi_hid_raw_send_report();
- }
-}
-
-static void udi_hid_raw_setreport_valid(void) {}
-
-void raw_hid_send(uint8_t *data, uint8_t length) {
- if (main_b_raw_enable && !udi_hid_raw_b_report_trans_ongoing && length == UDI_HID_RAW_REPORT_SIZE) {
- memcpy(udi_hid_raw_report, data, UDI_HID_RAW_REPORT_SIZE);
- udi_hid_raw_send_report();
- }
-}
-
-bool udi_hid_raw_receive_report(void) {
- if (!main_b_raw_enable) {
- return false;
- }
-
- return udd_ep_run(UDI_HID_RAW_EP_OUT | USB_EP_DIR_OUT, false, udi_hid_raw_report_recv, UDI_HID_RAW_REPORT_SIZE, udi_hid_raw_report_rcvd);
-}
-
-static void udi_hid_raw_report_rcvd(udd_ep_status_t status, iram_size_t nb_rcvd, udd_ep_id_t ep) {
- UNUSED(ep);
-
- if (status == UDD_EP_TRANSFER_OK && nb_rcvd == UDI_HID_RAW_REPORT_SIZE) {
- UDI_HID_RAW_RECEIVE(udi_hid_raw_report_recv, UDI_HID_RAW_REPORT_SIZE);
- }
-}
-
-#endif // RAW_ENABLE
-
-//********************************************************************************************
-// CON
-//********************************************************************************************
-#ifdef CONSOLE_ENABLE
-
-bool udi_hid_con_enable(void);
-void udi_hid_con_disable(void);
-bool udi_hid_con_setup(void);
-uint8_t udi_hid_con_getsetting(void);
-
-UDC_DESC_STORAGE udi_api_t udi_api_hid_con = {
- .enable = (bool (*)(void))udi_hid_con_enable,
- .disable = (void (*)(void))udi_hid_con_disable,
- .setup = (bool (*)(void))udi_hid_con_setup,
- .getsetting = (uint8_t(*)(void))udi_hid_con_getsetting,
- .sof_notify = NULL,
-};
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_con_rate;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_con_protocol;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_con_report_set[UDI_HID_CON_REPORT_SIZE];
-
-bool udi_hid_con_b_report_valid;
-
-COMPILER_WORD_ALIGNED
-uint8_t udi_hid_con_report[UDI_HID_CON_REPORT_SIZE];
-
-volatile bool udi_hid_con_b_report_trans_ongoing;
-
-COMPILER_WORD_ALIGNED
-static uint8_t udi_hid_con_report_trans[UDI_HID_CON_REPORT_SIZE];
-
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE udi_hid_con_report_desc_t udi_hid_con_report_desc = {{
- 0x06, 0x31, 0xFF, // Usage Page (Vendor Defined - PJRC Teensy compatible)
- 0x09, 0x74, // Usage (Vendor Defined - PJRC Teensy compatible)
- 0xA1, 0x01, // Collection (Application)
- // Data to host
- 0x09, 0x75, // Usage (Vendor Defined)
- 0x15, 0x00, // Logical Minimum (0x00)
- 0x26, 0xFF, 0x00, // Logical Maximum (0x00FF)
- 0x95, CONSOLE_EPSIZE, // Report Count
- 0x75, 0x08, // Report Size (8)
- 0x81, 0x02, // Input (Data, Variable, Absolute)
- // Data from host
- 0x09, 0x76, // Usage (Vendor Defined)
- 0x15, 0x00, // Logical Minimum (0x00)
- 0x26, 0xFF, 0x00, // Logical Maximum (0x00FF)
- 0x95, CONSOLE_EPSIZE, // Report Count
- 0x75, 0x08, // Report Size (8)
- 0x91, 0x02, // Output (Data)
- 0xC0 // End Collection
-}};
-
-static bool udi_hid_con_setreport(void);
-static void udi_hid_con_setreport_valid(void);
-
-static void udi_hid_con_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep);
-
-bool udi_hid_con_enable(void) {
- // Initialize internal values
- udi_hid_con_rate = 0;
- udi_hid_con_protocol = 0;
- udi_hid_con_b_report_trans_ongoing = false;
- memset(udi_hid_con_report, 0, UDI_HID_CON_REPORT_SIZE);
- udi_hid_con_b_report_valid = false;
- return UDI_HID_CON_ENABLE_EXT();
-}
-
-void udi_hid_con_disable(void) { UDI_HID_CON_DISABLE_EXT(); }
-
-bool udi_hid_con_setup(void) { return udi_hid_setup(&udi_hid_con_rate, &udi_hid_con_protocol, (uint8_t *)&udi_hid_con_report_desc, udi_hid_con_setreport); }
-
-uint8_t udi_hid_con_getsetting(void) { return 0; }
-
-static bool udi_hid_con_setreport(void) {
- if ((USB_HID_REPORT_TYPE_OUTPUT == (udd_g_ctrlreq.req.wValue >> 8)) && (0 == (0xFF & udd_g_ctrlreq.req.wValue)) && (UDI_HID_CON_REPORT_SIZE == udd_g_ctrlreq.req.wLength)) {
- udd_g_ctrlreq.payload = udi_hid_con_report_set;
- udd_g_ctrlreq.callback = udi_hid_con_setreport_valid;
- udd_g_ctrlreq.payload_size = UDI_HID_CON_REPORT_SIZE;
- return true;
- }
- return false;
-}
-
-bool udi_hid_con_send_report(void) {
- if (!main_b_con_enable) {
- return false;
- }
-
- if (udi_hid_con_b_report_trans_ongoing) {
- return false;
- }
-
- memcpy(udi_hid_con_report_trans, udi_hid_con_report, UDI_HID_CON_REPORT_SIZE);
- udi_hid_con_b_report_valid = false;
- udi_hid_con_b_report_trans_ongoing = udd_ep_run(UDI_HID_CON_EP_IN | USB_EP_DIR_IN, false, udi_hid_con_report_trans, UDI_HID_CON_REPORT_SIZE, udi_hid_con_report_sent);
-
- return udi_hid_con_b_report_trans_ongoing;
-}
-
-static void udi_hid_con_report_sent(udd_ep_status_t status, iram_size_t nb_sent, udd_ep_id_t ep) {
- UNUSED(status);
- UNUSED(nb_sent);
- UNUSED(ep);
- udi_hid_con_b_report_trans_ongoing = false;
- if (udi_hid_con_b_report_valid) {
- udi_hid_con_send_report();
- }
-}
-
-static void udi_hid_con_setreport_valid(void) {}
-
-#endif // CONSOLE_ENABLE
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.h b/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.h
deleted file mode 100644
index e17538fa70e4..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device Human Interface Device (HID) keyboard interface.
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDC_HID_KBD_H_
-#define _UDC_HID_KBD_H_
-
-#include "udc_desc.h"
-#include "udi.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//******************************************************************************
-// Keyboard interface definitions
-//******************************************************************************
-extern UDC_DESC_STORAGE udi_api_t udi_api_hid_kbd;
-extern bool udi_hid_kbd_b_report_valid;
-extern volatile bool udi_hid_kbd_b_report_trans_ongoing;
-extern uint8_t udi_hid_kbd_report_set;
-bool udi_hid_kbd_send_report(void);
-
-//********************************************************************************************
-// NKRO Keyboard
-//********************************************************************************************
-#ifdef NKRO_ENABLE
-extern UDC_DESC_STORAGE udi_api_t udi_api_hid_nkro;
-extern bool udi_hid_nkro_b_report_valid;
-extern volatile bool udi_hid_nkro_b_report_trans_ongoing;
-bool udi_hid_nkro_send_report(void);
-#endif // NKRO_ENABLE
-
-//********************************************************************************************
-// SYS-CTRL interface
-//********************************************************************************************
-#ifdef EXTRAKEY_ENABLE
-extern UDC_DESC_STORAGE udi_api_t udi_api_hid_exk;
-extern bool udi_hid_exk_b_report_valid;
-bool udi_hid_exk_send_report(void);
-#endif // EXTRAKEY_ENABLE
-
-//********************************************************************************************
-// CON Console
-//********************************************************************************************
-#ifdef CONSOLE_ENABLE
-extern UDC_DESC_STORAGE udi_api_t udi_api_hid_con;
-extern bool udi_hid_con_b_report_valid;
-extern uint8_t udi_hid_con_report_set[UDI_HID_CON_REPORT_SIZE];
-extern volatile bool udi_hid_con_b_report_trans_ongoing;
-bool udi_hid_con_send_report(void);
-#endif // CONSOLE_ENABLE
-
-//********************************************************************************************
-// MOU Mouse
-//********************************************************************************************
-#ifdef MOUSE_ENABLE
-extern UDC_DESC_STORAGE udi_api_t udi_api_hid_mou;
-extern bool udi_hid_mou_b_report_valid;
-bool udi_hid_mou_send_report(void);
-#endif // MOUSE_ENABLE
-
-//********************************************************************************************
-// RAW Raw
-//********************************************************************************************
-#ifdef RAW_ENABLE
-extern UDC_DESC_STORAGE udi_api_t udi_api_hid_raw;
-bool udi_hid_raw_send_report(void);
-bool udi_hid_raw_receive_report(void);
-#endif // RAW_ENABLE
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _UDC_HID_KBD_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_conf.h b/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_conf.h
deleted file mode 100644
index db5db17ed506..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_conf.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/**
- * \file
- *
- * \brief Default HID keyboard configuration for a USB Device
- * with a single interface HID keyboard
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UDI_HID_KBD_CONF_H_
-#define _UDI_HID_KBD_CONF_H_
-
-/**
- * \addtogroup udi_hid_keyboard_group_single_desc
- * @{
- */
-
-#include "udi_device_conf.h"
-
-#include "udi_hid_kbd.h"
-
-#endif // _UDI_HID_KBD_CONF_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_desc.c b/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_desc.c
deleted file mode 100644
index 2a60868ed288..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_desc.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * \brief Default descriptors for a USB Device
- * with a single interface HID keyboard
- *
- * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#include "conf_usb.h"
-#include "usb_protocol.h"
-#include "udc_desc.h"
-#include "udi_device_conf.h"
-#include "udi_hid_kbd.h"
-#include "udi_cdc.h"
-
-/**
- * \ingroup udi_hid_keyboard_group
- * \defgroup udi_hid_keyboard_group_single_desc USB device descriptors for a single interface
- *
- * The following structures provide the USB device descriptors required
- * for USB Device with a single interface HID keyboard.
- *
- * It is ready to use and do not require more definition.
- * @{
- */
-
-//! USB Device Descriptor
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = {.bLength = sizeof(usb_dev_desc_t),
- .bDescriptorType = USB_DT_DEVICE,
- .bcdUSB = LE16(USB_V2_0),
- .bDeviceClass = DEVICE_CLASS,
- .bDeviceSubClass = DEVICE_SUBCLASS,
- .bDeviceProtocol = DEVICE_PROTOCOL,
- .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE,
- .idVendor = LE16(USB_DEVICE_VENDOR_ID),
- .idProduct = LE16(USB_DEVICE_PRODUCT_ID),
- .bcdDevice = LE16(USB_DEVICE_VERSION),
-#ifdef USB_DEVICE_MANUFACTURE_NAME
- .iManufacturer = 1,
-#else
- .iManufacturer = 0, // No manufacture string
-#endif
-#ifdef USB_DEVICE_PRODUCT_NAME
- .iProduct = 2,
-#else
- .iProduct = 0, // No product string
-#endif
-#if (defined USB_DEVICE_SERIAL_NAME || defined USB_DEVICE_GET_SERIAL_NAME_POINTER)
- .iSerialNumber = 3,
-#else
- .iSerialNumber = 0, // No serial string
-#endif
- .bNumConfigurations = 1};
-
-#if 0
-# ifdef USB_DEVICE_HS_SUPPORT
-//! USB Device Qualifier Descriptor for HS
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = {
- .bLength = sizeof(usb_dev_qual_desc_t),
- .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
- .bcdUSB = LE16(USB_V2_0),
- .bDeviceClass = 0,
- .bDeviceSubClass = 0,
- .bDeviceProtocol = 0,
- .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE,
- .bNumConfigurations = 1
-};
-# endif
-#endif
-
-//! USB Device Configuration Descriptor filled for FS and HS
-COMPILER_WORD_ALIGNED
-UDC_DESC_STORAGE udc_desc_t udc_desc = {
- .conf.bLength = sizeof(usb_conf_desc_t),
- .conf.bDescriptorType = USB_DT_CONFIGURATION,
- .conf.wTotalLength = LE16(sizeof(udc_desc_t)),
- .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE,
- .conf.bConfigurationValue = 1,
- .conf.iConfiguration = 0,
- .conf.bmAttributes = /* USB_CONFIG_ATTR_MUST_SET | */ USB_DEVICE_ATTR,
- .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
- .hid_kbd = UDI_HID_KBD_DESC,
-#ifdef RAW_ENABLE
- .hid_raw = UDI_HID_RAW_DESC,
-#endif
-#ifdef MOUSE_ENABLE
- .hid_mou = UDI_HID_MOU_DESC,
-#endif
-#ifdef EXTRAKEY_ENABLE
- .hid_exk = UDI_HID_EXK_DESC,
-#endif
-#ifdef CONSOLE_ENABLE
- .hid_con = UDI_HID_CON_DESC,
-#endif
-#ifdef NKRO_ENABLE
- .hid_nkro = UDI_HID_NKRO_DESC,
-#endif
-#ifdef VIRTSER_ENABLE
- .cdc_serial = CDC_DESCRIPTOR,
-#endif
-};
-
-UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = {
- &udi_api_hid_kbd,
-#ifdef RAW_ENABLE
- &udi_api_hid_raw,
-#endif
-#ifdef MOUSE_ENABLE
- &udi_api_hid_mou,
-#endif
-#ifdef EXTRAKEY_ENABLE
- &udi_api_hid_exk,
-#endif
-#ifdef CONSOLE_ENABLE
- &udi_api_hid_con,
-#endif
-#ifdef NKRO_ENABLE
- &udi_api_hid_nkro,
-#endif
-#ifdef VIRTSER_ENABLE
- &udi_api_cdc_comm, &udi_api_cdc_data,
-#endif
-};
-
-//! Add UDI with USB Descriptors FS & HS
-UDC_DESC_STORAGE udc_config_speed_t udc_config_fshs[1] = {{
- .desc = (usb_conf_desc_t UDC_DESC_STORAGE *)&udc_desc,
- .udi_apis = udi_apis,
-}};
-
-//! Add all information about USB Device in global structure for UDC
-UDC_DESC_STORAGE udc_config_t udc_config = {
- .confdev_lsfs = &udc_device_desc,
- .conf_lsfs = udc_config_fshs,
-};
-
-//@}
-//@}
diff --git a/tmk_core/protocol/arm_atsam/usb/ui.c b/tmk_core/protocol/arm_atsam/usb/ui.c
deleted file mode 100644
index f5263d728937..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/ui.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
- * \file
- *
- * \brief User Interface
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef ARM_MATH_CM4
-# define ARM_MATH_CM4
-#endif
-
-#undef LITTLE_ENDIAN // redefined in samd51j18a.h
-#include "samd51j18a.h"
-#include "ui.h"
-
-//! Sequence process running each \c SEQUENCE_PERIOD ms
-#define SEQUENCE_PERIOD 150
-
-#if 0
-/* Interrupt on "pin change" from push button to do wakeup on USB
- * Note:
- * This interrupt is enable when the USB host enable remote wakeup feature
- * This interrupt wakeup the CPU if this one is in idle mode
- */
-static void ui_wakeup_handler(void)
-{
- /* It is a wakeup then send wakeup USB */
- udc_remotewakeup();
-}
-#endif
-
-void ui_init(void) {}
-
-void ui_powerdown(void) {}
-
-void ui_wakeup_enable(void) {}
-
-void ui_wakeup_disable(void) {}
-
-void ui_wakeup(void) {}
-
-void ui_process(uint16_t framenumber) {}
-
-void ui_kbd_led(uint8_t value) {}
diff --git a/tmk_core/protocol/arm_atsam/usb/ui.h b/tmk_core/protocol/arm_atsam/usb/ui.h
deleted file mode 100644
index d1c767d45764..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/ui.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
- * \file
- *
- * \brief Common User Interface for HID Keyboard application
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _UI_H_
-#define _UI_H_
-
-//! \brief Initializes the user interface
-void ui_init(void);
-
-//! \brief Enters the user interface in power down mode
-void ui_powerdown(void);
-
-//! \brief Enables the asynchronous interrupts of the user interface
-void ui_wakeup_enable(void);
-
-//! \brief Disables the asynchronous interrupts of the user interface
-void ui_wakeup_disable(void);
-
-//! \brief Exits the user interface of power down mode
-void ui_wakeup(void);
-
-/*! \brief This process is called each 1ms
- * It is called only if the USB interface is enabled.
- *
- * \param framenumber Current frame number
- */
-void ui_process(uint16_t framenumber);
-
-/*! \brief Turn on or off the keyboard LEDs
- */
-void ui_kbd_led(uint8_t value);
-
-#endif // _UI_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/usb.c b/tmk_core/protocol/arm_atsam/usb/usb.c
deleted file mode 100644
index 1abf0a2f4de7..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb.c
+++ /dev/null
@@ -1,1083 +0,0 @@
-/**
- * \file
- *
- * \brief SAM USB Driver.
- *
- * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#define DEVICE_MODE_ONLY true
-#define SAMD11 DEVICE_MODE_ONLY
-
-#ifndef ARM_MATH_CM4
-# define ARM_MATH_CM4
-#endif
-
-#include "compiler.h"
-#undef LITTLE_ENDIAN // redefined in samd51j18a.h
-#include "samd51j18a.h"
-#include
-#include
-#include "arm_math.h"
-#include "status_codes.h"
-#include "usb.h"
-
-/** Fields definition from a LPM TOKEN */
-#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0)
-#define USB_LPM_ATTRIBUT_HIRD_MASK (0xF << 4)
-#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8)
-#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0)
-#define USB_LPM_ATTRIBUT_HIRD(value) ((value & 0xF) << 4)
-#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8)
-#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1)
-
-/**
- * \brief Mask selecting the index part of an endpoint address
- */
-#define USB_EP_ADDR_MASK 0x0f
-
-/**
- * \brief Endpoint transfer direction is IN
- */
-#define USB_EP_DIR_IN 0x80
-
-/**
- * \brief Endpoint transfer direction is OUT
- */
-#define USB_EP_DIR_OUT 0x00
-
-/**
- * \name USB SRAM data containing pipe descriptor table
- * The content of the USB SRAM can be :
- * - modified by USB hardware interface to update pipe status.
- * Thereby, it is read by software.
- * - modified by USB software to control pipe.
- * Thereby, it is read by hardware.
- * This data section is volatile.
- *
- * @{
- */
-COMPILER_PACK_SET(1)
-COMPILER_WORD_ALIGNED
-union {
- UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
-} usb_descriptor_table;
-COMPILER_PACK_RESET()
-/** @} */
-
-/**
- * \brief Local USB module instance
- */
-static struct usb_module *_usb_instances;
-
-/* Device LPM callback variable */
-static uint32_t device_callback_lpm_wakeup_enable;
-
-/**
- * \brief Device endpoint callback parameter variable, used to transfer info to UDD wrapper layer
- */
-static struct usb_endpoint_callback_parameter ep_callback_para;
-
-/**
- * \internal USB Device IRQ Mask Bits Map
- */
-static const uint16_t _usb_device_irq_bits[USB_DEVICE_CALLBACK_N] = {
- USB_DEVICE_INTFLAG_SOF, USB_DEVICE_INTFLAG_EORST, USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM, USB_DEVICE_INTFLAG_RAMACER, USB_DEVICE_INTFLAG_SUSPEND, USB_DEVICE_INTFLAG_LPMNYET, USB_DEVICE_INTFLAG_LPMSUSP,
-};
-
-/**
- * \internal USB Device IRQ Mask Bits Map
- */
-static const uint8_t _usb_endpoint_irq_bits[USB_DEVICE_EP_CALLBACK_N] = {USB_DEVICE_EPINTFLAG_TRCPT_Msk, USB_DEVICE_EPINTFLAG_TRFAIL_Msk, USB_DEVICE_EPINTFLAG_RXSTP, USB_DEVICE_EPINTFLAG_STALL_Msk};
-
-/**
- * \brief Registers a USB device callback
- *
- * Registers a callback function which is implemented by the user.
- *
- * \note The callback must be enabled by \ref usb_device_enable_callback,
- * in order for the interrupt handler to call it when the conditions for the
- * callback type is met.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] callback_type Callback type given by an enum
- * \param[in] callback_func Pointer to callback function
- *
- * \return Status of the registration operation.
- * \retval STATUS_OK The callback was registered successfully.
- */
-enum status_code usb_device_register_callback(struct usb_module *module_inst, enum usb_device_callback callback_type, usb_device_callback_t callback_func) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(callback_func);
-
- /* Register callback function */
- module_inst->device_callback[callback_type] = callback_func;
-
- /* Set the bit corresponding to the callback_type */
- module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
-
- return STATUS_OK;
-}
-
-/**
- * \brief Unregisters a USB device callback
- *
- * Unregisters an asynchronous callback implemented by the user. Removing it
- * from the internal callback registration table.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] callback_type Callback type given by an enum
- *
- * \return Status of the de-registration operation.
- * \retval STATUS_OK The callback was unregistered successfully.
- */
-enum status_code usb_device_unregister_callback(struct usb_module *module_inst, enum usb_device_callback callback_type) {
- /* Sanity check arguments */
- Assert(module_inst);
-
- /* Unregister callback function */
- module_inst->device_callback[callback_type] = NULL;
-
- /* Clear the bit corresponding to the callback_type */
- module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
-
- return STATUS_OK;
-}
-
-/**
- * \brief Enables USB device callback generation for a given type.
- *
- * Enables asynchronous callbacks for a given logical type.
- * This must be called before USB device generate callback events.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] callback_type Callback type given by an enum
- *
- * \return Status of the callback enable operation.
- * \retval STATUS_OK The callback was enabled successfully.
- */
-enum status_code usb_device_enable_callback(struct usb_module *module_inst, enum usb_device_callback callback_type) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
-
- /* clear related flag */
- module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
-
- /* Enable callback */
- module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
-
- module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
-
- return STATUS_OK;
-}
-
-/**
- * \brief Disables USB device callback generation for a given type.
- *
- * Disables asynchronous callbacks for a given logical type.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] callback_type Callback type given by an enum
- *
- * \return Status of the callback disable operation.
- * \retval STATUS_OK The callback was disabled successfully.
- */
-enum status_code usb_device_disable_callback(struct usb_module *module_inst, enum usb_device_callback callback_type) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
-
- /* Disable callback */
- module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
-
- module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
-
- return STATUS_OK;
-}
-
-/**
- * \brief Registers a USB device endpoint callback
- *
- * Registers a callback function which is implemented by the user.
- *
- * \note The callback must be enabled by \ref usb_device_endpoint_enable_callback,
- * in order for the interrupt handler to call it when the conditions for the
- * callback type is met.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] ep_num Endpoint to configure
- * \param[in] callback_type Callback type given by an enum
- * \param[in] callback_func Pointer to callback function
- *
- * \return Status of the registration operation.
- * \retval STATUS_OK The callback was registered successfully.
- */
-enum status_code usb_device_endpoint_register_callback(struct usb_module *module_inst, uint8_t ep_num, enum usb_device_endpoint_callback callback_type, usb_device_endpoint_callback_t callback_func) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(ep_num < USB_EPT_NUM);
- Assert(callback_func);
-
- /* Register callback function */
- module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
-
- /* Set the bit corresponding to the callback_type */
- module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
-
- return STATUS_OK;
-}
-
-/**
- * \brief Unregisters a USB device endpoint callback
- *
- * Unregisters an callback implemented by the user. Removing it
- * from the internal callback registration table.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] ep_num Endpoint to configure
- * \param[in] callback_type Callback type given by an enum
- *
- * \return Status of the de-registration operation.
- * \retval STATUS_OK The callback was unregistered successfully.
- */
-enum status_code usb_device_endpoint_unregister_callback(struct usb_module *module_inst, uint8_t ep_num, enum usb_device_endpoint_callback callback_type) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(ep_num < USB_EPT_NUM);
-
- /* Unregister callback function */
- module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
-
- /* Clear the bit corresponding to the callback_type */
- module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
-
- return STATUS_OK;
-}
-
-/**
- * \brief Enables USB device endpoint callback generation for a given type.
- *
- * Enables callbacks for a given logical type.
- * This must be called before USB device pipe generate callback events.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] ep Endpoint to configure
- * \param[in] callback_type Callback type given by an enum
- *
- * \return Status of the callback enable operation.
- * \retval STATUS_OK The callback was enabled successfully.
- */
-enum status_code usb_device_endpoint_enable_callback(struct usb_module *module_inst, uint8_t ep, enum usb_device_endpoint_callback callback_type) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
-
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
- Assert(ep_num < USB_EPT_NUM);
-
- /* Enable callback */
- module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
- if (ep_num == 0) { // control endpoint
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
- } else if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
- }
- }
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
- if (ep_num == 0) { // control endpoint
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
- } else if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
- }
- }
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
- }
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
- if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
- }
- }
-
- return STATUS_OK;
-}
-
-/**
- * \brief Disables USB device endpoint callback generation for a given type.
- *
- * Disables callbacks for a given logical type.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] ep Endpoint to configure
- * \param[in] callback_type Callback type given by an enum
- *
- * \return Status of the callback disable operation.
- * \retval STATUS_OK The callback was disabled successfully.
- */
-enum status_code usb_device_endpoint_disable_callback(struct usb_module *module_inst, uint8_t ep, enum usb_device_endpoint_callback callback_type) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
-
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
- Assert(ep_num < USB_EPT_NUM);
-
- /* Enable callback */
- module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
- if (ep_num == 0) { // control endpoint
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
- } else if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT0;
- }
- }
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
- if (ep_num == 0) { // control endpoint
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
- } else if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
- }
- }
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
- }
-
- if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
- if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
- }
- }
-
- return STATUS_OK;
-}
-
-/**
- * \brief Initializes an USB device endpoint configuration structure to defaults.
- *
- * Initializes a given USB device endpoint configuration structure to a
- * set of known default values. This function should be called on all new
- * instances of these configuration structures before being modified by the
- * user application.
- *
- * The default configuration is as follows:
- * \li endpoint address is 0
- * \li endpoint size is 8 bytes
- * \li auto_zlp is false
- * \li endpoint type is control
- *
- * \param[out] ep_config Configuration structure to initialize to default values
- */
-void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config) {
- /* Sanity check arguments */
- Assert(ep_config);
-
- /* Write default config to config struct */
- ep_config->ep_address = 0;
- ep_config->ep_size = USB_ENDPOINT_8_BYTE;
- ep_config->auto_zlp = false;
- ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
-}
-
-/**
- * \brief Writes an USB device endpoint configuration to the hardware module.
- *
- * Writes out a given configuration of an USB device endpoint
- * configuration to the hardware module. If the pipe is already configured,
- * the new configuration will replace the existing one.
- *
- * \param[in] module_inst Pointer to USB software instance struct
- * \param[in] ep_config Configuration settings for the endpoint
- *
- * \return Status of the device endpoint configuration operation
- * \retval STATUS_OK The device endpoint was configured successfully
- * \retval STATUS_ERR_DENIED The endpoint address is already configured
- */
-enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst, struct usb_device_endpoint_config *ep_config) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(ep_config);
-
- uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
- uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
-
- switch (ep_config->ep_type) {
- case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) | USB_DEVICE_EPCFG_EPTYPE1(0);
- return STATUS_OK;
-
- case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
- if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
- } else {
- return STATUS_ERR_DENIED;
- }
- if (true == ep_config->auto_zlp) {
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
- } else {
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
- }
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
- return STATUS_OK;
-
- case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
- if (ep_bank) {
- if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
- } else {
- return STATUS_ERR_DENIED;
- }
- } else {
- if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
- } else {
- return STATUS_ERR_DENIED;
- }
- }
- break;
-
- case USB_DEVICE_ENDPOINT_TYPE_BULK:
- if (ep_bank) {
- if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
- } else {
- return STATUS_ERR_DENIED;
- }
- } else {
- if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
- } else {
- return STATUS_ERR_DENIED;
- }
- }
- break;
-
- case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
- if (ep_bank) {
- if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
- } else {
- return STATUS_ERR_DENIED;
- }
- } else {
- if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
- } else {
- return STATUS_ERR_DENIED;
- }
- }
- break;
-
- default:
- break;
- }
-
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
-
- if (true == ep_config->auto_zlp) {
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
- } else {
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
- }
-
- return STATUS_OK;
-}
-
-/**
- * \brief Check if current endpoint is configured
- *
- * \param module_inst Pointer to USB software instance struct
- * \param ep Endpoint address (direction & number)
- *
- * \return \c true if endpoint is configured and ready to use
- */
-bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep) {
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
- uint8_t flag;
-
- if (ep & USB_EP_DIR_IN) {
- flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
- } else {
- flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
- }
- return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
-}
-
-/**
- * \brief Abort ongoing job on the endpoint
- *
- * \param module_inst Pointer to USB software instance struct
- * \param ep Endpoint address
- */
-void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep) {
- uint8_t ep_num;
- ep_num = ep & USB_EP_ADDR_MASK;
-
- // Stop transfer
- if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
- // Eventually ack a transfer occur during abort
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
- // Eventually ack a transfer occur during abort
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
- }
-}
-
-/**
- * \brief Check if endpoint is halted
- *
- * \param module_inst Pointer to USB software instance struct
- * \param ep Endpoint address
- *
- * \return \c true if the endpoint is halted
- */
-bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep) {
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
- if (ep & USB_EP_DIR_IN) {
- return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
- } else {
- return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
- }
-}
-
-/**
- * \brief Halt the endpoint (send STALL)
- *
- * \param module_inst Pointer to USB software instance struct
- * \param ep Endpoint address
- */
-void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep) {
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
- // Stall endpoint
- if (ep & USB_EP_DIR_IN) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
- } else {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
- }
-}
-
-/**
- * \brief Clear endpoint halt state
- *
- * \param module_inst Pointer to USB software instance struct
- * \param ep Endpoint address
- */
-void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep) {
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
- if (ep & USB_EP_DIR_IN) {
- if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1) {
- // Remove stall request
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
- if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
- // The Stall has occurred, then reset data toggle
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
- }
- }
- } else {
- if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0) {
- // Remove stall request
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
- if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
- // The Stall has occurred, then reset data toggle
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
- }
- }
- }
-}
-
-/**
- * \brief Start write buffer job on a endpoint
- *
- * \param module_inst Pointer to USB module instance
- * \param ep_num Endpoint number
- * \param pbuf Pointer to buffer
- * \param buf_size Size of buffer
- *
- * \return Status of procedure
- * \retval STATUS_OK Job started successfully
- * \retval STATUS_ERR_DENIED Endpoint is not ready
- */
-enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst, uint8_t ep_num, uint8_t *pbuf, uint32_t buf_size) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
- Assert(ep_num < USB_EPT_NUM);
-
- uint8_t flag;
- flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
- if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
- return STATUS_ERR_DENIED;
- };
-
- /* get endpoint configuration from setting register */
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
-
- return STATUS_OK;
-}
-
-/**
- * \brief Start read buffer job on a endpoint
- *
- * \param module_inst Pointer to USB module instance
- * \param ep_num Endpoint number
- * \param pbuf Pointer to buffer
- * \param buf_size Size of buffer
- *
- * \return Status of procedure
- * \retval STATUS_OK Job started successfully
- * \retval STATUS_ERR_DENIED Endpoint is not ready
- */
-enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst, uint8_t ep_num, uint8_t *pbuf, uint32_t buf_size) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
- Assert(ep_num < USB_EPT_NUM);
-
- uint8_t flag;
- flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
- if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
- return STATUS_ERR_DENIED;
- };
-
- /* get endpoint configuration from setting register */
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
- usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
- module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
-
- return STATUS_OK;
-}
-
-/**
- * \brief Start setup packet read job on a endpoint
- *
- * \param module_inst Pointer to USB device module instance
- * \param pbuf Pointer to buffer
- *
- * \return Status of procedure
- * \retval STATUS_OK Job started successfully
- * \retval STATUS_ERR_DENIED Endpoint is not ready
- */
-enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst, uint8_t *pbuf) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
-
- /* get endpoint configuration from setting register */
- usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
- usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
- usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
- module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
-
- return STATUS_OK;
-}
-
-static void _usb_device_interrupt_handler(void) {
- uint16_t ep_inst;
- uint16_t flags, flags_run;
- ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
-
- /* device interrupt */
- if (0 == ep_inst) {
- int i;
-
- /* get interrupt flags */
- flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
- flags_run = flags & _usb_instances->device_enabled_callback_mask & _usb_instances->device_registered_callback_mask;
-
- for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) {
- if (flags & _usb_device_irq_bits[i]) {
- _usb_instances->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[i];
- }
- if (flags_run & _usb_device_irq_bits[i]) {
- if (i == USB_DEVICE_CALLBACK_LPMSUSP) {
- device_callback_lpm_wakeup_enable = usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE & USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
- }
- (_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
- }
- }
-
- } else {
- /* endpoint interrupt */
-
- for (uint8_t i = 0; i < USB_EPT_NUM; i++) {
- if (ep_inst & (1 << i)) {
- flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
- flags_run = flags & _usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_instances->device_endpoint_registered_callback_mask[i];
-
- // endpoint transfer stall interrupt
- if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk) {
- if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
- _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
- ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
- } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
- _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
- ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
- }
-
- if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk) {
- (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances, &ep_callback_para);
- }
- return;
- }
-
- // endpoint received setup interrupt
- if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
- _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
- if (_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP]) {
- ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
- (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances, &ep_callback_para);
- }
- return;
- }
-
- // endpoint transfer complete interrupt
- if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
- if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
- _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
- ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
- ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
-
- } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
- _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
- ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
- ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
- ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
- }
- if (flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
- (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances, &ep_callback_para);
- }
- return;
- }
-
- // endpoint transfer fail interrupt
- if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
- if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) {
- _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
- if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
- usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
- }
- ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
- if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
- return;
- }
- } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) {
- _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
- if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
- usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
- }
- ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
- if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
- return;
- }
- }
-
- if (flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
- (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances, &ep_callback_para);
- }
- return;
- }
- }
- }
- }
-}
-
-/**
- * \brief Enable the USB module peripheral
- *
- * \param module_inst pointer to USB module instance
- */
-void usb_enable(struct usb_module *module_inst) {
- Assert(module_inst);
- Assert(module_inst->hw);
-
- module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
- while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE)
- ;
-}
-
-/**
- * \brief Disable the USB module peripheral
- *
- * \param module_inst pointer to USB module instance
- */
-void usb_disable(struct usb_module *module_inst) {
- Assert(module_inst);
- Assert(module_inst->hw);
-
- module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
- module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
- module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
- while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE)
- ;
-}
-
-/**
- * \brief Interrupt handler for the USB module.
- */
-void USB_0_Handler(void) {
- if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE) {
- } else {
- /*device mode ISR */
- _usb_device_interrupt_handler();
- }
-}
-
-void USB_1_Handler(void) {
- _usb_device_interrupt_handler();
-}
-
-void USB_2_Handler(void) {
- _usb_device_interrupt_handler();
-}
-
-void USB_3_Handler(void) {
- _usb_device_interrupt_handler();
-}
-
-/**
- * \brief Get the default USB module settings
- *
- * \param[out] module_config Configuration structure to initialize to default values
- */
-void usb_get_config_defaults(struct usb_config *module_config) {
- Assert(module_config);
-
- /* Sanity check arguments */
- Assert(module_config);
- /* Write default configuration to config struct */
- module_config->select_host_mode = 0;
- module_config->run_in_standby = 1;
- module_config->source_generator = 0;
- module_config->speed_mode = USB_SPEED_FULL;
-}
-
-#define NVM_USB_PAD_TRANSN_POS 45
-#define NVM_USB_PAD_TRANSN_SIZE 5
-#define NVM_USB_PAD_TRANSP_POS 50
-#define NVM_USB_PAD_TRANSP_SIZE 5
-#define NVM_USB_PAD_TRIM_POS 55
-#define NVM_USB_PAD_TRIM_SIZE 3
-
-/**
- * \brief Initializes USB module instance
- *
- * Enables the clock and initializes the USB module, based on the given
- * configuration values.
- *
- * \param[in,out] module_inst Pointer to the software module instance struct
- * \param[in] hw Pointer to the USB hardware module
- * \param[in] module_config Pointer to the USB configuration options struct
- *
- * \return Status of the initialization procedure.
- *
- * \retval STATUS_OK The module was initialized successfully
- */
-
-#define GCLK_USB 10
-
-enum status_code usb_init(struct usb_module *module_inst, Usb *const hw, struct usb_config *module_config) {
- /* Sanity check arguments */
- Assert(hw);
- Assert(module_inst);
- Assert(module_config);
-
- uint32_t i, j;
- uint32_t pad_transn, pad_transp, pad_trim;
-
- Gclk * pgclk = GCLK;
- Mclk * pmclk = MCLK;
- Port * pport = PORT;
- Oscctrl *posc = OSCCTRL;
-
- _usb_instances = module_inst;
-
- /* Associate the software module instance with the hardware module */
- module_inst->hw = hw;
-
- // setup peripheral and synchronous bus clocks to USB
- pmclk->AHBMASK.bit.USB_ = 1;
- pmclk->APBBMASK.bit.USB_ = 1;
-
- /* Set up the USB DP/DN pins */
- pport->Group[0].PMUX[12].reg = 0x77; // PA24, PA25, function column H for USB D-, D+
- pport->Group[0].PINCFG[24].bit.PMUXEN = 1;
- pport->Group[0].PINCFG[25].bit.PMUXEN = 1;
- pport->Group[1].PMUX[11].bit.PMUXE = 7; // PB22, function column H for USB SOF_1KHz output
- pport->Group[1].PINCFG[22].bit.PMUXEN = 1;
-
- // configure and enable DFLL for USB clock recovery mode at 48MHz
- posc->DFLLCTRLA.bit.ENABLE = 0;
- while (posc->DFLLSYNC.bit.ENABLE)
- ;
- while (posc->DFLLSYNC.bit.DFLLCTRLB)
- ;
- posc->DFLLCTRLB.bit.USBCRM = 1;
- while (posc->DFLLSYNC.bit.DFLLCTRLB)
- ;
- posc->DFLLCTRLB.bit.MODE = 1;
- while (posc->DFLLSYNC.bit.DFLLCTRLB)
- ;
- posc->DFLLCTRLB.bit.QLDIS = 0;
- while (posc->DFLLSYNC.bit.DFLLCTRLB)
- ;
- posc->DFLLCTRLB.bit.CCDIS = 1;
- posc->DFLLMUL.bit.MUL = 0xbb80; // 4800 x 1KHz
- while (posc->DFLLSYNC.bit.DFLLMUL)
- ;
- posc->DFLLCTRLA.bit.ENABLE = 1;
- while (posc->DFLLSYNC.bit.ENABLE)
- ;
-
- /* Setup clock for module */
- pgclk->PCHCTRL[GCLK_USB].bit.GEN = 0;
- pgclk->PCHCTRL[GCLK_USB].bit.CHEN = 1;
-
- /* Reset */
- hw->DEVICE.CTRLA.bit.SWRST = 1;
- while (hw->DEVICE.SYNCBUSY.bit.SWRST) {
- /* Sync wait */
- }
-
- /* Change QOS values to have the best performance and correct USB behaviour */
- USB->DEVICE.QOSCTRL.bit.CQOS = 2;
- USB->DEVICE.QOSCTRL.bit.DQOS = 2;
-
- /* Load Pad Calibration */
-
- pad_transn = (USB_FUSES_TRANSN_ADDR >> USB_FUSES_TRANSN_Pos) & USB_FUSES_TRANSN_Msk;
- if (pad_transn == 0x1F) {
- pad_transn = 5;
- }
-
- hw->DEVICE.PADCAL.bit.TRANSN = pad_transn;
-
- pad_transp = (USB_FUSES_TRANSP_ADDR >> USB_FUSES_TRANSP_Pos) & USB_FUSES_TRANSP_Msk;
- if (pad_transp == 0x1F) {
- pad_transp = 29;
- }
-
- hw->DEVICE.PADCAL.bit.TRANSP = pad_transp;
-
- pad_trim = (USB_FUSES_TRIM_ADDR >> USB_FUSES_TRIM_Pos) & USB_FUSES_TRIM_Msk;
- if (pad_trim == 0x07) {
- pad_trim = 3;
- }
-
- hw->DEVICE.PADCAL.bit.TRIM = pad_trim;
-
- /* Set the configuration */
- hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode;
- hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
- hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
- if (USB_SPEED_FULL == module_config->speed_mode) {
- module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
- } else if (USB_SPEED_LOW == module_config->speed_mode) {
- module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val;
- }
-
- memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0, sizeof(usb_descriptor_table.usb_endpoint_table));
-
- /* device callback related */
- for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) {
- module_inst->device_callback[i] = NULL;
- }
- for (i = 0; i < USB_EPT_NUM; i++) {
- for (j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++) {
- module_inst->device_endpoint_callback[i][j] = NULL;
- }
- }
- module_inst->device_registered_callback_mask = 0;
- module_inst->device_enabled_callback_mask = 0;
- for (j = 0; j < USB_EPT_NUM; j++) {
- module_inst->device_endpoint_registered_callback_mask[j] = 0;
- module_inst->device_endpoint_enabled_callback_mask[j] = 0;
- }
-
- /* Enable interrupts for this USB module */
- NVIC_EnableIRQ(USB_0_IRQn);
- NVIC_EnableIRQ(USB_2_IRQn);
- NVIC_EnableIRQ(USB_3_IRQn);
-
- return STATUS_OK;
-}
diff --git a/tmk_core/protocol/arm_atsam/usb/usb.h b/tmk_core/protocol/arm_atsam/usb/usb.h
deleted file mode 100644
index 270143a11237..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb.h
+++ /dev/null
@@ -1,462 +0,0 @@
-/**
- * \file
- *
- * \brief SAM USB Driver
- *
- * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-#ifndef USB_H_INCLUDED
-#define USB_H_INCLUDED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup asfdoc_sam0_usb_group SAM Universal Serial Bus (USB)
- *
- * The Universal Serial Bus (USB) module complies with the USB 2.1 specification.
- *
- * The following peripherals are used by this module:
- * - USB (Universal Serial Bus)
- *
- * The following devices can use this module:
- * - Atmel | SMART SAM D51
- *
- * The USB module covers following mode:
- * \if USB_DEVICE_MODE
- * - USB Device Mode
- * \endif
- * \if USB_HOST_MODE
- * - USB Host Mode
- * \endif
- *
- * The USB module covers following speed:
- * \if USB_HS_MODE
- * - USB High Speed (480Mbit/s)
- * \endif
- * - USB Full Speed (12Mbit/s)
- * \if USB_LS_MODE
- * - USB Low Speed (1.5Mbit/s)
- * \endif
- *
- * \if USB_LPM_MODE
- * The USB module supports Link Power Management (LPM-L1) protocol.
- * \endif
- *
- * USB support needs whole set of enumeration process, to make the device
- * recognizable and usable. The USB driver is designed to interface to the
- * USB Stack in Atmel Software Framework (ASF).
- *
- * \if USB_DEVICE_MODE
- * \section asfdoc_sam0_usb_device USB Device Mode
- * The ASF USB Device Stack has defined the USB Device Driver (UDD) interface,
- * to support USB device operations. The USB module device driver complies with
- * this interface, so that the USB Device Stack can work based on the
- * USB module.
- *
- * Refer to
- * "ASF - USB Device Stack" for more details.
- * \endif
- *
- * \if USB_HOST_MODE
- * \section adfdoc_sam0_usb_host USB Host Mode
- * The ASF USB Host Stack has defined the USB Host Driver (UHD) interface,
- * to support USB host operations. The USB module host driver complies with
- * this interface, so that the USB Host Stack can work based on the USB module.
- *
- * Refer to
- * "ASF - USB Host Stack" for more details.
- * \endif
- */
-
-/** Enum for the speed status for the USB module */
-enum usb_speed {
- USB_SPEED_LOW,
- USB_SPEED_FULL,
-};
-
-/** Enum for the possible callback types for the USB in host module */
-enum usb_host_callback {
- USB_HOST_CALLBACK_SOF,
- USB_HOST_CALLBACK_RESET,
- USB_HOST_CALLBACK_WAKEUP,
- USB_HOST_CALLBACK_DNRSM,
- USB_HOST_CALLBACK_UPRSM,
- USB_HOST_CALLBACK_RAMACER,
- USB_HOST_CALLBACK_CONNECT,
- USB_HOST_CALLBACK_DISCONNECT,
- USB_HOST_CALLBACK_N,
-};
-
-/** Enum for the possible callback types for the USB pipe in host module */
-enum usb_host_pipe_callback {
- USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE,
- USB_HOST_PIPE_CALLBACK_ERROR,
- USB_HOST_PIPE_CALLBACK_SETUP,
- USB_HOST_PIPE_CALLBACK_STALL,
- USB_HOST_PIPE_CALLBACK_N,
-};
-
-/**
- * \brief Host pipe types.
- */
-enum usb_host_pipe_type {
- USB_HOST_PIPE_TYPE_DISABLE,
- USB_HOST_PIPE_TYPE_CONTROL,
- USB_HOST_PIPE_TYPE_ISO,
- USB_HOST_PIPE_TYPE_BULK,
- USB_HOST_PIPE_TYPE_INTERRUPT,
- USB_HOST_PIPE_TYPE_EXTENDED,
-};
-
-/**
- * \brief Host pipe token types.
- */
-enum usb_host_pipe_token {
- USB_HOST_PIPE_TOKEN_SETUP,
- USB_HOST_PIPE_TOKEN_IN,
- USB_HOST_PIPE_TOKEN_OUT,
-};
-
-/**
- * \brief Enumeration for the possible callback types for the USB in device module
- */
-enum usb_device_callback {
- USB_DEVICE_CALLBACK_SOF,
- USB_DEVICE_CALLBACK_RESET,
- USB_DEVICE_CALLBACK_WAKEUP,
- USB_DEVICE_CALLBACK_RAMACER,
- USB_DEVICE_CALLBACK_SUSPEND,
- USB_DEVICE_CALLBACK_LPMNYET,
- USB_DEVICE_CALLBACK_LPMSUSP,
- USB_DEVICE_CALLBACK_N,
-};
-
-/**
- * \brief Enumeration for the possible callback types for the USB endpoint in device module
- */
-enum usb_device_endpoint_callback {
- USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,
- USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,
- USB_DEVICE_ENDPOINT_CALLBACK_RXSTP,
- USB_DEVICE_ENDPOINT_CALLBACK_STALL,
- USB_DEVICE_EP_CALLBACK_N,
-};
-
-/**
- * \brief Device Endpoint types.
- */
-enum usb_device_endpoint_type {
- USB_DEVICE_ENDPOINT_TYPE_DISABLE,
- USB_DEVICE_ENDPOINT_TYPE_CONTROL,
- USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS,
- USB_DEVICE_ENDPOINT_TYPE_BULK,
- USB_DEVICE_ENDPOINT_TYPE_INTERRUPT,
-};
-
-/**
- * \brief Endpoint Size
- */
-enum usb_endpoint_size {
- USB_ENDPOINT_8_BYTE,
- USB_ENDPOINT_16_BYTE,
- USB_ENDPOINT_32_BYTE,
- USB_ENDPOINT_64_BYTE,
- USB_ENDPOINT_128_BYTE,
- USB_ENDPOINT_256_BYTE,
- USB_ENDPOINT_512_BYTE,
- USB_ENDPOINT_1023_BYTE,
-};
-
-/**
- * \brief Link Power Management Handshake.
- */
-enum usb_device_lpm_mode {
- USB_DEVICE_LPM_NOT_SUPPORT,
- USB_DEVICE_LPM_ACK,
- USB_DEVICE_LPM_NYET,
-};
-
-/**
- * \brief Module structure
- */
-struct usb_module;
-
-/**
- * \name Host Callback Functions Types
- * @{
- */
-typedef void (*usb_host_callback_t)(struct usb_module *module_inst);
-typedef void (*usb_host_pipe_callback_t)(struct usb_module *module_inst, void *);
-/** @} */
-
-/**
- * \name Device Callback Functions Types
- * @{
- */
-typedef void (*usb_device_callback_t)(struct usb_module *module_inst, void *pointer);
-typedef void (*usb_device_endpoint_callback_t)(struct usb_module *module_inst, void *pointer);
-/** @} */
-
-/** USB configurations */
-struct usb_config {
- /** \c true for host, \c false for device. */
- bool select_host_mode;
- /** When \c true the module is enabled during standby. */
- bool run_in_standby;
- /** Generic Clock Generator source channel. */
- // enum gclk_generator source_generator;
- uint8_t source_generator;
- /** Speed mode */
- // enum usb_speed speed_mode;
- uint8_t speed_mode;
-};
-
-/**
- * \brief USB software module instance structure.
- *
- * USB software module instance structure, used to retain software state
- * information of an associated hardware module instance.
- *
- */
-struct usb_module {
- /** Hardware module pointer of the associated USB peripheral. */
- Usb *hw;
-
- /** Array to store device related callback functions */
- usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N];
- usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N];
- /** Bit mask for device callbacks registered */
- uint16_t device_registered_callback_mask;
- /** Bit mask for device callbacks enabled */
- uint16_t device_enabled_callback_mask;
- /** Bit mask for device endpoint callbacks registered */
- uint8_t device_endpoint_registered_callback_mask[USB_EPT_NUM];
- /** Bit mask for device endpoint callbacks enabled */
- uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM];
-};
-
-/** USB device endpoint configurations */
-struct usb_device_endpoint_config {
- /** device address */
- uint8_t ep_address;
- /** endpoint size */
- enum usb_endpoint_size ep_size;
- /** automatic zero length packet mode, \c true to enable */
- bool auto_zlp;
- /** type of endpoint with Bank */
- enum usb_device_endpoint_type ep_type;
-};
-
-/** USB device endpoint callback status parameter structure */
-struct usb_endpoint_callback_parameter {
- uint16_t received_bytes;
- uint16_t sent_bytes;
- uint16_t out_buffer_size;
- uint8_t endpoint_address;
-};
-
-void usb_enable(struct usb_module *module_inst);
-void usb_disable(struct usb_module *module_inst);
-
-/**
- * \brief Get the status of USB module's state machine
- *
- * \param module_inst Pointer to USB module instance
- */
-static inline uint8_t usb_get_state_machine_status(struct usb_module *module_inst) {
- /* Sanity check arguments */
- Assert(module_inst);
- Assert(module_inst->hw);
-
- return module_inst->hw->DEVICE.FSMSTATUS.reg;
-}
-
-void usb_get_config_defaults(struct usb_config *module_config);
-enum status_code usb_init(struct usb_module *module_inst, Usb *const hw, struct usb_config *module_config);
-
-/**
- * \brief Attach USB device to the bus
- *
- * \param module_inst Pointer to USB device module instance
- */
-static inline void usb_device_attach(struct usb_module *module_inst) {
- module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
-}
-
-/**
- * \brief Detach USB device from the bus
- *
- * \param module_inst Pointer to USB device module instance
- */
-static inline void usb_device_detach(struct usb_module *module_inst) {
- module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
-}
-
-/**
- * \brief Get the speed mode of USB device
- *
- * \param module_inst Pointer to USB device module instance
- * \return USB Speed mode (\ref usb_speed).
- */
-static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst) {
- if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk)) {
- return USB_SPEED_FULL;
- } else {
- return USB_SPEED_LOW;
- }
-}
-
-/**
- * \brief Get the address of USB device
- *
- * \param module_inst Pointer to USB device module instance
- * \return USB device address value.
- */
-static inline uint8_t usb_device_get_address(struct usb_module *module_inst) {
- return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD));
-}
-
-/**
- * \brief Set the speed mode of USB device
- *
- * \param module_inst Pointer to USB device module instance
- * \param address USB device address value
- */
-static inline void usb_device_set_address(struct usb_module *module_inst, uint8_t address) {
- module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address;
-}
-
-/**
- * \brief Get the frame number of USB device
- *
- * \param module_inst Pointer to USB device module instance
- * \return USB device frame number value.
- */
-static inline uint16_t usb_device_get_frame_number(struct usb_module *module_inst) {
- return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM));
-}
-
-/**
- * \brief Get the micro-frame number of USB device
- *
- * \param module_inst Pointer to USB device module instance
- * \return USB device micro-frame number value.
- */
-static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *module_inst) {
- return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg));
-}
-
-/**
- * \brief USB device send the resume wakeup
- *
- * \param module_inst Pointer to USB device module instance
- */
-static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst) {
- module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
-}
-
-/**
- * \brief USB device set the LPM mode
- *
- * \param module_inst Pointer to USB device module instance
- * \param lpm_mode LPM mode
- */
-static inline void usb_device_set_lpm_mode(struct usb_module *module_inst, enum usb_device_lpm_mode lpm_mode) {
- module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode;
-}
-
-/**
- * \name USB Device Callback Management
- * @{
- */
-enum status_code usb_device_register_callback(struct usb_module *module_inst, enum usb_device_callback callback_type, usb_device_callback_t callback_func);
-enum status_code usb_device_unregister_callback(struct usb_module *module_inst, enum usb_device_callback callback_type);
-enum status_code usb_device_enable_callback(struct usb_module *module_inst, enum usb_device_callback callback_type);
-enum status_code usb_device_disable_callback(struct usb_module *module_inst, enum usb_device_callback callback_type);
-/** @} */
-
-/**
- * \name USB Device Endpoint Configuration
- * @{
- */
-void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config);
-enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst, struct usb_device_endpoint_config *ep_config);
-bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep);
-/** @} */
-
-/**
- * \name USB Device Endpoint Callback Management
- * @{
- */
-enum status_code usb_device_endpoint_register_callback(struct usb_module *module_inst, uint8_t ep_num, enum usb_device_endpoint_callback callback_type, usb_device_endpoint_callback_t callback_func);
-enum status_code usb_device_endpoint_unregister_callback(struct usb_module *module_inst, uint8_t ep_num, enum usb_device_endpoint_callback callback_type);
-enum status_code usb_device_endpoint_enable_callback(struct usb_module *module_inst, uint8_t ep, enum usb_device_endpoint_callback callback_type);
-enum status_code usb_device_endpoint_disable_callback(struct usb_module *module_inst, uint8_t ep, enum usb_device_endpoint_callback callback_type);
-/** @} */
-
-/**
- * \name USB Device Endpoint Job Management
- * @{
- */
-enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst, uint8_t ep_num, uint8_t *pbuf, uint32_t buf_size);
-enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst, uint8_t ep_num, uint8_t *pbuf, uint32_t buf_size);
-enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst, uint8_t *pbuf);
-void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep);
-/** @} */
-
-/**
- * \name USB Device Endpoint Operations
- * @{
- */
-
-bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep);
-void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep);
-void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep);
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* USB_H_INCLUDED */
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_atmel.h b/tmk_core/protocol/arm_atsam/usb/usb_atmel.h
deleted file mode 100644
index 82bafdc7d156..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_atmel.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/**
- * \file
- *
- * \brief All USB VIDs and PIDs from Atmel USB applications
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _USB_ATMEL_H_
-#define _USB_ATMEL_H_
-
-/**
- * \defgroup usb_group USB Stack
- *
- * This stack includes the USB Device Stack, USB Host Stack and common
- * definitions.
- * @{
- */
-
-//! @}
-
-/**
- * \ingroup usb_group
- * \defgroup usb_atmel_ids_group Atmel USB Identifiers
- *
- * This module defines Atmel PID and VIDs constants.
- *
- * @{
- */
-
-//! \name Vendor Identifier assigned by USB org to ATMEL
-#define USB_VID_ATMEL 0x03EB
-
-//! \name Product Identifier assigned by ATMEL to AVR applications
-//! @{
-
-//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others.
-//! @{
-#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013
-#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017
-#define USB_PID_ATMEL_MEGA_CDC 0x2018
-#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019
-#define USB_PID_ATMEL_MEGA_MS 0x201A
-#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B
-#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C
-#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D
-#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E
-#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022
-#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023
-#define USB_PID_ATMEL_MEGA_MS_2 0x2029
-#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A
-#define USB_PID_ATMEL_MEGA_MS_3 0x2032
-#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050
-//! @}
-
-//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools.
-//! @{
-#define USB_PID_ATMEL_XPLAINED 0x2122
-#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A
-#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B
-//! @}
-
-//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=>
-//! @{
-#define USB_PID_ATMEL_UC3_ENUM 0x2300
-#define USB_PID_ATMEL_UC3_MS 0x2301
-#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302
-#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303
-#define USB_PID_ATMEL_UC3_HID 0x2304
-#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305
-#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306
-#define USB_PID_ATMEL_UC3_CDC 0x2307
-#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308
-#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx
-#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311
-#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312
-//! @}
-
-//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications
-//! @{
-#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400
-#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401
-#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402
-#define USB_PID_ATMEL_ASF_MSC 0x2403
-#define USB_PID_ATMEL_ASF_CDC 0x2404
-#define USB_PID_ATMEL_ASF_PHDC 0x2405
-#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406
-#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420
-#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421
-#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422
-#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423
-#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424
-#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425
-#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426
-#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430
-#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431
-#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432
-#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433
-#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434
-//! @}
-
-//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders
-//! Note, !!!! don't use this range for demos or examples !!!!
-//! @{
-#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6
-#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7
-#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8
-#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9
-#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA
-#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB
-#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC
-#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD
-#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE
-
-#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF
-#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0
-#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1
-#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2
-#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3
-#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4
-#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5
-#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6
-#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7
-#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8
-#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9
-#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA
-#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB
-#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC
-#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED
-#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE
-#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF
-#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0
-#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1
-#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2
-#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3
-#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4
-#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5
-#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6
-#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7
-#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8
-#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9
-#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA
-#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB
-// 2FFCh to 2FFFh used by C51 family products
-//! @}
-
-//! @}
-
-//! @}
-
-#endif // _USB_ATMEL_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_device_udd.c b/tmk_core/protocol/arm_atsam/usb/usb_device_udd.c
deleted file mode 100644
index bc5e79d9f09c..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_device_udd.c
+++ /dev/null
@@ -1,1046 +0,0 @@
-/**
- * \file
- *
- * \brief USB Device wrapper layer for compliance with common driver UDD
- *
- * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-#include "samd51j18a.h"
-#include
-#include
-
-// Get USB device configuration
-#include "conf_usb.h"
-#include "udd.h"
-#include "usb.h"
-#include "status_codes.h"
-
-/**
- * \ingroup usb_device_group
- * \defgroup usb_device_udd_group USB Device Driver Implement (UDD)
- * USB low-level driver for USB device mode
- * @{
- */
-// Check USB device configuration
-#ifdef USB_DEVICE_HS_SUPPORT
-# error The High speed mode is not supported on this part, please remove USB_DEVICE_HS_SUPPORT in conf_usb.h
-#endif
-
-// Note: This driver is adapted for SAMD51
-
-#ifndef UDC_REMOTEWAKEUP_LPM_ENABLE
-# define UDC_REMOTEWAKEUP_LPM_ENABLE()
-#endif
-#ifndef UDC_REMOTEWAKEUP_LPM_DISABLE
-# define UDC_REMOTEWAKEUP_LPM_DISABLE()
-#endif
-#ifndef UDC_SUSPEND_LPM_EVENT
-# define UDC_SUSPEND_LPM_EVENT()
-#endif
-
-/* for debug text */
-#ifdef USB_DEBUG
-# define dbg_print printf
-#else
-# define dbg_print(...)
-#endif
-
-/** Maximum size of a transfer in multi-packet mode */
-#define UDD_ENDPOINT_MAX_TRANS ((8 * 1024) - 1)
-
-/** USB software device instance structure */
-struct usb_module usb_device;
-
-/**
- * \name Clock management
- *
- * @{
- */
-
-#define UDD_CLOCK_GEN 0
-
-static inline void udd_wait_clock_ready(void) {}
-
-/**
- * \name Power management
- *
- * @{
- */
-#define udd_sleep_mode(arg)
-/** @} */
-
-/**
- * \name Control endpoint low level management routine.
- *
- * This function performs control endpoint management.
- * It handles the SETUP/DATA/HANDSHAKE phases of a control transaction.
- *
- * @{
- */
-
-/**
- * \brief Buffer to store the data received on control endpoint (SETUP/OUT endpoint 0)
- *
- * Used to avoid a RAM buffer overflow in case of the payload buffer
- * is smaller than control endpoint size
- */
-UDC_BSS(4)
-uint8_t udd_ctrl_buffer[USB_DEVICE_EP_CTRL_SIZE];
-
-/** Bit definitions about endpoint control state machine for udd_ep_control_state */
-typedef enum {
- UDD_EPCTRL_SETUP = 0, //!< Wait a SETUP packet
- UDD_EPCTRL_DATA_OUT = 1, //!< Wait a OUT data packet
- UDD_EPCTRL_DATA_IN = 2, //!< Wait a IN data packet
- UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP = 3, //!< Wait a IN ZLP packet
- UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, //!< Wait a OUT ZLP packet
- UDD_EPCTRL_STALL_REQ = 5, //!< STALL enabled on IN & OUT packet
-} udd_ctrl_ep_state_t;
-
-/** Global variable to give and record information of the set up request management */
-udd_ctrl_request_t udd_g_ctrlreq;
-
-/** State of the endpoint control management */
-static udd_ctrl_ep_state_t udd_ep_control_state;
-
-/** Total number of data received/sent during data packet phase with previous payload buffers */
-static uint16_t udd_ctrl_prev_payload_nb_trans;
-
-/** Number of data received/sent to/from udd_g_ctrlreq.payload buffer */
-static uint16_t udd_ctrl_payload_nb_trans;
-
-/** @} */
-
-/**
- * \name Management of bulk/interrupt/isochronous endpoints
- *
- * The UDD manages the data transfer on endpoints:
- * - Start data transfer on endpoint with USB Device DMA
- * - Send a ZLP packet if requested
- * - Call callback registered to signal end of transfer
- * The transfer abort and stall feature are supported.
- *
- * @{
- */
-
-/**
- * \brief Buffer to store the data received on bulk/interrupt endpoints
- *
- * Used to avoid a RAM buffer overflow in case of the user buffer
- * is smaller than endpoint size
- *
- * \warning The protected interrupt endpoint size is 512 bytes maximum.
- * \warning The isochronous and endpoint is not protected by this system and
- * the user must always use a buffer corresponding at endpoint size.
- */
-
-#if (defined USB_DEVICE_LOW_SPEED)
-UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][8];
-#elif (defined USB_DEVICE_HS_SUPPORT)
-UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][512];
-#else
-UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][64];
-#endif
-
-/** Structure definition about job registered on an endpoint */
-typedef struct {
- union {
- //! Callback to call at the end of transfer
- udd_callback_trans_t call_trans;
- //! Callback to call when the endpoint halt is cleared
- udd_callback_halt_cleared_t call_nohalt;
- };
- //! Buffer located in internal RAM to send or fill during job
- uint8_t *buf;
- //! Size of buffer to send or fill
- iram_size_t buf_size;
- //! Total number of data transferred on endpoint
- iram_size_t nb_trans;
- //! Endpoint size
- uint16_t ep_size;
- //! A job is registered on this endpoint
- uint8_t busy : 1;
- //! A short packet is requested for this job on endpoint IN
- uint8_t b_shortpacket : 1;
- //! The cache buffer is currently used on endpoint OUT
- uint8_t b_use_out_cache_buffer : 1;
-} udd_ep_job_t;
-
-/** Array to register a job on bulk/interrupt/isochronous endpoint */
-static udd_ep_job_t udd_ep_job[2 * USB_DEVICE_MAX_EP];
-
-/** @} */
-
-/**
- * \brief Get the detailed job by endpoint number
- * \param[in] ep Endpoint Address
- * \retval pointer to an udd_ep_job_t structure instance
- */
-static udd_ep_job_t *udd_ep_get_job(udd_ep_id_t ep) {
- if ((ep == 0) || (ep == 0x80)) {
- return NULL;
- } else {
- return &udd_ep_job[(2 * (ep & USB_EP_ADDR_MASK) + ((ep & USB_EP_DIR_IN) ? 1 : 0)) - 2];
- }
-}
-
-/**
- * \brief Endpoint IN process, continue to send packets or zero length packet
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void udd_ep_trans_in_next(void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
- udd_ep_id_t ep = ep_callback_para->endpoint_address;
- uint16_t ep_size, nb_trans;
- uint16_t next_trans;
- udd_ep_id_t ep_num;
- udd_ep_job_t * ptr_job;
-
- ptr_job = udd_ep_get_job(ep);
- ep_num = ep & USB_EP_ADDR_MASK;
-
- ep_size = ptr_job->ep_size;
- /* Update number of data transferred */
- nb_trans = ep_callback_para->sent_bytes;
- ptr_job->nb_trans += nb_trans;
-
- /* Need to send other data */
- if (ptr_job->nb_trans != ptr_job->buf_size) {
- next_trans = ptr_job->buf_size - ptr_job->nb_trans;
- if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
- /* The USB hardware support a maximum
- * transfer size of UDD_ENDPOINT_MAX_TRANS Bytes */
- next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ep_size);
- }
- /* Need ZLP, if requested and last packet is not a short packet */
- ptr_job->b_shortpacket = ptr_job->b_shortpacket && (0 == (next_trans % ep_size));
- usb_device_endpoint_write_buffer_job(&usb_device, ep_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
- return;
- }
-
- /* Need to send a ZLP after all data transfer */
- if (ptr_job->b_shortpacket) {
- ptr_job->b_shortpacket = false;
- /* Start new transfer */
- usb_device_endpoint_write_buffer_job(&usb_device, ep_num, &ptr_job->buf[ptr_job->nb_trans], 0);
- return;
- }
-
- /* Job complete then call callback */
- ptr_job->busy = false;
- if (NULL != ptr_job->call_trans) {
- ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
- }
-}
-
-/**
- * \brief Endpoint OUT process, continue to receive packets or zero length packet
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void udd_ep_trans_out_next(void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
- udd_ep_id_t ep = ep_callback_para->endpoint_address;
- uint16_t ep_size, nb_trans;
- uint16_t next_trans;
- udd_ep_id_t ep_num;
- udd_ep_job_t * ptr_job;
-
- ptr_job = udd_ep_get_job(ep);
- ep_num = ep & USB_EP_ADDR_MASK;
-
- ep_size = ptr_job->ep_size;
- /* Update number of data transferred */
- nb_trans = ep_callback_para->received_bytes;
-
- /* Can be necessary to copy data receive from cache buffer to user buffer */
- if (ptr_job->b_use_out_cache_buffer) {
- memcpy(&ptr_job->buf[ptr_job->nb_trans], udd_ep_out_cache_buffer[ep_num - 1], ptr_job->buf_size % ep_size);
- }
-
- /* Update number of data transferred */
- ptr_job->nb_trans += nb_trans;
- if (ptr_job->nb_trans > ptr_job->buf_size) {
- ptr_job->nb_trans = ptr_job->buf_size;
- }
-
- /* If all previous data requested are received and user buffer not full
- * then need to receive other data */
- if ((nb_trans == ep_callback_para->out_buffer_size) && (ptr_job->nb_trans != ptr_job->buf_size)) {
- next_trans = ptr_job->buf_size - ptr_job->nb_trans;
- if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
- /* The USB hardware support a maximum transfer size
- * of UDD_ENDPOINT_MAX_TRANS Bytes */
- next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ep_size);
- } else {
- next_trans -= next_trans % ep_size;
- }
-
- if (next_trans < ep_size) {
- /* Use the cache buffer for Bulk or Interrupt size endpoint */
- ptr_job->b_use_out_cache_buffer = true;
- usb_device_endpoint_read_buffer_job(&usb_device, ep_num, udd_ep_out_cache_buffer[ep_num - 1], ep_size);
- } else {
- usb_device_endpoint_read_buffer_job(&usb_device, ep_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
- }
- return;
- }
-
- /* Job complete then call callback */
- ptr_job->busy = false;
- if (NULL != ptr_job->call_trans) {
- ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
- }
-}
-
-/**
- * \brief Endpoint Transfer Complete callback function, to do the next transfer depends on the direction(IN or OUT)
- * \param[in] module_inst Pointer to USB module instance
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void udd_ep_transfer_process(struct usb_module *module_inst, void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
- udd_ep_id_t ep = ep_callback_para->endpoint_address;
-
- if (ep & USB_EP_DIR_IN) {
- udd_ep_trans_in_next(pointer);
- } else {
- udd_ep_trans_out_next(pointer);
- }
-}
-
-void udd_ep_abort(udd_ep_id_t ep) {
- udd_ep_job_t *ptr_job;
-
- usb_device_endpoint_abort_job(&usb_device, ep);
-
- /* Job complete then call callback */
- ptr_job = udd_ep_get_job(ep);
- if (!ptr_job->busy) {
- return;
- }
- ptr_job->busy = false;
- if (NULL != ptr_job->call_trans) {
- /* It can be a Transfer or stall callback */
- ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, ptr_job->nb_trans, ep);
- }
-}
-
-bool udd_is_high_speed(void) {
- return false;
-}
-
-uint16_t udd_get_frame_number(void) {
- return usb_device_get_frame_number(&usb_device);
-}
-
-uint16_t udd_get_micro_frame_number(void) {
- return usb_device_get_micro_frame_number(&usb_device);
-}
-
-void udd_ep_free(udd_ep_id_t ep) {
- struct usb_device_endpoint_config config_ep;
- usb_device_endpoint_get_config_defaults(&config_ep);
-
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
- udd_ep_abort(ep);
-
- config_ep.ep_address = ep;
- config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_DISABLE;
- usb_device_endpoint_set_config(&usb_device, &config_ep);
- usb_device_endpoint_unregister_callback(&usb_device, ep_num, USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
- usb_device_endpoint_disable_callback(&usb_device, ep, USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
-}
-
-bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize) {
- struct usb_device_endpoint_config config_ep;
- usb_device_endpoint_get_config_defaults(&config_ep);
-
- config_ep.ep_address = ep;
-
- if (MaxEndpointSize <= 8) {
- config_ep.ep_size = USB_ENDPOINT_8_BYTE;
- } else if (MaxEndpointSize <= 16) {
- config_ep.ep_size = USB_ENDPOINT_16_BYTE;
- } else if (MaxEndpointSize <= 32) {
- config_ep.ep_size = USB_ENDPOINT_32_BYTE;
- } else if (MaxEndpointSize <= 64) {
- config_ep.ep_size = USB_ENDPOINT_64_BYTE;
- } else if (MaxEndpointSize <= 128) {
- config_ep.ep_size = USB_ENDPOINT_128_BYTE;
- } else if (MaxEndpointSize <= 256) {
- config_ep.ep_size = USB_ENDPOINT_256_BYTE;
- } else if (MaxEndpointSize <= 512) {
- config_ep.ep_size = USB_ENDPOINT_512_BYTE;
- } else if (MaxEndpointSize <= 1023) {
- config_ep.ep_size = USB_ENDPOINT_1023_BYTE;
- } else {
- return false;
- }
- udd_ep_job_t *ptr_job = udd_ep_get_job(ep);
- ptr_job->ep_size = MaxEndpointSize;
-
- bmAttributes = bmAttributes & USB_EP_TYPE_MASK;
-
- /* Check endpoint type */
- if (USB_EP_TYPE_ISOCHRONOUS == bmAttributes) {
- config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS;
- } else if (USB_EP_TYPE_BULK == bmAttributes) {
- config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_BULK;
- } else if (USB_EP_TYPE_INTERRUPT == bmAttributes) {
- config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_INTERRUPT;
- } else {
- return false;
- }
-
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
- if (STATUS_OK != usb_device_endpoint_set_config(&usb_device, &config_ep)) {
- return false;
- }
- usb_device_endpoint_register_callback(&usb_device, ep_num, USB_DEVICE_ENDPOINT_CALLBACK_TRCPT, udd_ep_transfer_process);
- usb_device_endpoint_enable_callback(&usb_device, ep, USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
- usb_device_endpoint_enable_callback(&usb_device, ep, USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
-
- return true;
-}
-
-bool udd_ep_is_halted(udd_ep_id_t ep) {
- return usb_device_endpoint_is_halted(&usb_device, ep);
-}
-
-bool udd_ep_set_halt(udd_ep_id_t ep) {
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
- if (USB_DEVICE_MAX_EP < ep_num) {
- return false;
- }
-
- usb_device_endpoint_set_halt(&usb_device, ep);
-
- udd_ep_abort(ep);
- return true;
-}
-
-bool udd_ep_clear_halt(udd_ep_id_t ep) {
- udd_ep_job_t *ptr_job;
- uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
- if (USB_DEVICE_MAX_EP < ep_num) {
- return false;
- }
- ptr_job = udd_ep_get_job(ep);
-
- usb_device_endpoint_clear_halt(&usb_device, ep);
-
- /* If a job is register on clear halt action then execute callback */
- if (ptr_job->busy == true) {
- ptr_job->busy = false;
- ptr_job->call_nohalt();
- }
-
- return true;
-}
-
-bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback) {
- udd_ep_id_t ep_num;
- udd_ep_job_t *ptr_job;
-
- ep_num = ep & USB_EP_ADDR_MASK;
- if (USB_DEVICE_MAX_EP < ep_num) {
- return false;
- }
-
- ptr_job = udd_ep_get_job(ep);
- if (ptr_job->busy == true) {
- return false; /* Job already on going */
- }
-
- /* Wait clear halt endpoint */
- if (usb_device_endpoint_is_halted(&usb_device, ep)) {
- /* Endpoint halted then registers the callback */
- ptr_job->busy = true;
- ptr_job->call_nohalt = callback;
- return true;
- } else if (usb_device_endpoint_is_configured(&usb_device, ep)) {
- callback(); /* Endpoint not halted then call directly callback */
- return true;
- } else {
- return false;
- }
-}
-
-/**
- * \brief Control Endpoint stall sending data
- */
-static void udd_ctrl_stall_data(void) {
- udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
-
- usb_device_endpoint_set_halt(&usb_device, USB_EP_DIR_IN);
- usb_device_endpoint_clear_halt(&usb_device, USB_EP_DIR_OUT);
-}
-
-bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t *buf, iram_size_t buf_size, udd_callback_trans_t callback) {
- udd_ep_id_t ep_num;
- udd_ep_job_t *ptr_job;
- uint32_t irqflags;
-
- ep_num = ep & USB_EP_ADDR_MASK;
-
- if ((USB_DEVICE_MAX_EP < ep_num) || (udd_ep_is_halted(ep))) {
- return false;
- }
-
- ptr_job = udd_ep_get_job(ep);
-
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
-
- if (ptr_job->busy == true) {
- __DMB();
- __set_PRIMASK(irqflags);
- return false; /* Job already on going */
- }
-
- ptr_job->busy = true;
- __DMB();
- __set_PRIMASK(irqflags);
-
- /* No job running, set up a new one */
- ptr_job->buf = buf;
- ptr_job->buf_size = buf_size;
- ptr_job->nb_trans = 0;
- ptr_job->call_trans = callback;
- ptr_job->b_shortpacket = b_shortpacket;
- ptr_job->b_use_out_cache_buffer = false;
-
- /* Initialize value to simulate a empty transfer */
- uint16_t next_trans;
-
- if (ep & USB_EP_DIR_IN) {
- if (0 != ptr_job->buf_size) {
- next_trans = ptr_job->buf_size;
- if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
- next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
- }
- ptr_job->b_shortpacket = ptr_job->b_shortpacket && (0 == (next_trans % ptr_job->ep_size));
- } else if (true == ptr_job->b_shortpacket) {
- ptr_job->b_shortpacket = false; /* avoid to send zero length packet again */
- next_trans = 0;
- } else {
- ptr_job->busy = false;
- if (NULL != ptr_job->call_trans) {
- ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
- }
- return true;
- }
- return (STATUS_OK == usb_device_endpoint_write_buffer_job(&usb_device, ep_num, &ptr_job->buf[0], next_trans));
- } else {
- if (0 != ptr_job->buf_size) {
- next_trans = ptr_job->buf_size;
- if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
- /* The USB hardware support a maximum transfer size
- * of UDD_ENDPOINT_MAX_TRANS Bytes */
- next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
- } else {
- next_trans -= next_trans % ptr_job->ep_size;
- }
- if (next_trans < ptr_job->ep_size) {
- ptr_job->b_use_out_cache_buffer = true;
- return (STATUS_OK == usb_device_endpoint_read_buffer_job(&usb_device, ep_num, udd_ep_out_cache_buffer[ep_num - 1], ptr_job->ep_size));
- } else {
- return (STATUS_OK == usb_device_endpoint_read_buffer_job(&usb_device, ep_num, &ptr_job->buf[0], next_trans));
- }
- } else {
- ptr_job->busy = false;
- if (NULL != ptr_job->call_trans) {
- ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
- }
- return true;
- }
- }
-}
-
-void udd_set_address(uint8_t address) {
- usb_device_set_address(&usb_device, address);
-}
-
-uint8_t udd_getaddress(void) {
- return usb_device_get_address(&usb_device);
-}
-
-void udd_send_remotewakeup(void) {
- uint32_t try = 5;
- udd_wait_clock_ready();
- udd_sleep_mode(UDD_STATE_IDLE);
- while (2 != usb_get_state_machine_status(&usb_device) && try--) {
- usb_device_send_remote_wake_up(&usb_device);
- }
-}
-
-void udd_set_setup_payload(uint8_t *payload, uint16_t payload_size) {
- udd_g_ctrlreq.payload = payload;
- udd_g_ctrlreq.payload_size = payload_size;
-}
-
-/**
- * \brief Control Endpoint translate the data in buffer into Device Request Struct
- */
-static void udd_ctrl_fetch_ram(void) {
- udd_g_ctrlreq.req.bmRequestType = udd_ctrl_buffer[0];
- udd_g_ctrlreq.req.bRequest = udd_ctrl_buffer[1];
- udd_g_ctrlreq.req.wValue = ((uint16_t)(udd_ctrl_buffer[3]) << 8) + udd_ctrl_buffer[2];
- udd_g_ctrlreq.req.wIndex = ((uint16_t)(udd_ctrl_buffer[5]) << 8) + udd_ctrl_buffer[4];
- udd_g_ctrlreq.req.wLength = ((uint16_t)(udd_ctrl_buffer[7]) << 8) + udd_ctrl_buffer[6];
-}
-
-/**
- * \brief Control Endpoint send out zero length packet
- */
-static void udd_ctrl_send_zlp_in(void) {
- udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP;
- usb_device_endpoint_setup_buffer_job(&usb_device, udd_ctrl_buffer);
- usb_device_endpoint_write_buffer_job(&usb_device, 0, udd_g_ctrlreq.payload, 0);
-}
-
-/**
- * \brief Process control endpoint IN transaction
- */
-static void udd_ctrl_in_sent(void) {
- static bool b_shortpacket = false;
- uint16_t nb_remain;
-
- nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
-
- if (0 == nb_remain) {
- /* All content of current buffer payload are sent Update number of total data sending by previous payload buffer */
- udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
- if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_nb_trans) || b_shortpacket) {
- /* All data requested are transferred or a short packet has been sent, then it is the end of data phase.
- * Generate an OUT ZLP for handshake phase */
- udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
- usb_device_endpoint_setup_buffer_job(&usb_device, udd_ctrl_buffer);
- return;
- }
- /* Need of new buffer because the data phase is not complete */
- if ((!udd_g_ctrlreq.over_under_run) || (!udd_g_ctrlreq.over_under_run())) {
- /* Under run then send zlp on IN
- * Here nb_remain=0, this allows to send a IN ZLP */
- } else {
- /* A new payload buffer is given */
- udd_ctrl_payload_nb_trans = 0;
- nb_remain = udd_g_ctrlreq.payload_size;
- }
- }
-
- /* Continue transfer and send next data */
- if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE) {
- nb_remain = USB_DEVICE_EP_CTRL_SIZE;
- b_shortpacket = false;
- } else {
- b_shortpacket = true;
- }
-
- /* Link payload buffer directly on USB hardware */
- usb_device_endpoint_write_buffer_job(&usb_device, 0, udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans, nb_remain);
-
- udd_ctrl_payload_nb_trans += nb_remain;
-}
-
-/**
- * \brief Process control endpoint OUT transaction
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void udd_ctrl_out_received(void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
-
- uint16_t nb_data;
- nb_data = ep_callback_para->received_bytes; /* Read data received during OUT phase */
-
- if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_nb_trans + nb_data)) {
- /* Payload buffer too small */
- nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
- }
-
- memcpy((uint8_t *)(udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans), udd_ctrl_buffer, nb_data);
- udd_ctrl_payload_nb_trans += nb_data;
-
- if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) || (udd_g_ctrlreq.req.wLength <= (udd_ctrl_prev_payload_nb_trans + udd_ctrl_payload_nb_trans))) {
- /* End of reception because it is a short packet
- * or all data are transferred */
-
- /* Before send ZLP, call intermediate callback
- * in case of data receive generate a stall */
- udd_g_ctrlreq.payload_size = udd_ctrl_payload_nb_trans;
- if (NULL != udd_g_ctrlreq.over_under_run) {
- if (!udd_g_ctrlreq.over_under_run()) {
- /* Stall ZLP */
- udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
- /* Stall all packets on IN & OUT control endpoint */
- udd_ep_set_halt(0);
- /* Ack reception of OUT to replace NAK by a STALL */
- return;
- }
- }
- /* Send IN ZLP to ACK setup request */
- udd_ctrl_send_zlp_in();
- return;
- }
-
- if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_nb_trans) {
- /* Overrun then request a new payload buffer */
- if (!udd_g_ctrlreq.over_under_run) {
- /* No callback available to request a new payload buffer
- * Stall ZLP */
- udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
- /* Stall all packets on IN & OUT control endpoint */
- udd_ep_set_halt(0);
- return;
- }
- if (!udd_g_ctrlreq.over_under_run()) {
- /* No new payload buffer delivered
- * Stall ZLP */
- udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
- /* Stall all packets on IN & OUT control endpoint */
- udd_ep_set_halt(0);
- return;
- }
- /* New payload buffer available
- * Update number of total data received */
- udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
-
- /* Reinitialize reception on payload buffer */
- udd_ctrl_payload_nb_trans = 0;
- }
- usb_device_endpoint_read_buffer_job(&usb_device, 0, udd_ctrl_buffer, USB_DEVICE_EP_CTRL_SIZE);
-}
-
-/**
- * \internal
- * \brief Endpoint 0 (control) SETUP received callback
- * \param[in] module_inst pointer to USB module instance
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void _usb_ep0_on_setup(struct usb_module *module_inst, void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
-
- if (UDD_EPCTRL_SETUP != udd_ep_control_state) {
- if (NULL != udd_g_ctrlreq.callback) {
- udd_g_ctrlreq.callback();
- }
- udd_ep_control_state = UDD_EPCTRL_SETUP;
- }
- if (8 != ep_callback_para->received_bytes) {
- udd_ctrl_stall_data();
- return;
- } else {
- udd_ctrl_fetch_ram();
- if (false == udc_process_setup()) {
- udd_ctrl_stall_data();
- return;
- } else if (Udd_setup_is_in()) {
- udd_ctrl_prev_payload_nb_trans = 0;
- udd_ctrl_payload_nb_trans = 0;
- udd_ep_control_state = UDD_EPCTRL_DATA_IN;
- usb_device_endpoint_read_buffer_job(&usb_device, 0, udd_ctrl_buffer, USB_DEVICE_EP_CTRL_SIZE);
- udd_ctrl_in_sent();
- } else {
- if (0 == udd_g_ctrlreq.req.wLength) {
- udd_ctrl_send_zlp_in();
- return;
- } else {
- udd_ctrl_prev_payload_nb_trans = 0;
- udd_ctrl_payload_nb_trans = 0;
- udd_ep_control_state = UDD_EPCTRL_DATA_OUT;
- /* Initialize buffer size and enable OUT bank */
- usb_device_endpoint_read_buffer_job(&usb_device, 0, udd_ctrl_buffer, USB_DEVICE_EP_CTRL_SIZE);
- }
- }
- }
-}
-
-/**
- * \brief Control Endpoint Process when underflow condition has occurred
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void udd_ctrl_underflow(void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
-
- if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) {
- /* Host want to stop OUT transaction
- * then stop to wait OUT data phase and wait IN ZLP handshake */
- udd_ctrl_send_zlp_in();
- } else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state) {
- /* A OUT handshake is waiting by device,
- * but host want extra IN data then stall extra IN data */
- usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
- }
-}
-
-/**
- * \brief Control Endpoint Process when overflow condition has occurred
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void udd_ctrl_overflow(void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
-
- if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) {
- /* Host want to stop IN transaction
- * then stop to wait IN data phase and wait OUT ZLP handshake */
- udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
- } else if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) {
- /* A IN handshake is waiting by device,
- * but host want extra OUT data then stall extra OUT data and following status stage */
- usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
- }
-}
-
-/**
- * \internal
- * \brief Control endpoint transfer fail callback function
- * \param[in] module_inst Pointer to USB module instance
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void _usb_ep0_on_tansfer_fail(struct usb_module *module_inst, void *pointer) {
- struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter *)pointer;
-
- if (ep_callback_para->endpoint_address & USB_EP_DIR_IN) {
- udd_ctrl_underflow(pointer);
- } else {
- udd_ctrl_overflow(pointer);
- }
-}
-
-/**
- * \internal
- * \brief Control endpoint transfer complete callback function
- * \param[in] module_inst Pointer to USB module instance
- * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
- */
-static void _usb_ep0_on_tansfer_ok(struct usb_module *module_inst, void *pointer) {
- if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) { /* handshake Out for status stage */
- udd_ctrl_out_received(pointer);
- } else if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) { /* handshake In for status stage */
- udd_ctrl_in_sent();
- } else {
- if (NULL != udd_g_ctrlreq.callback) {
- udd_g_ctrlreq.callback();
- }
- udd_ep_control_state = UDD_EPCTRL_SETUP;
- }
-}
-
-/**
- * \brief Enable Control Endpoint
- * \param[in] module_inst Pointer to USB module instance
- */
-static void udd_ctrl_ep_enable(struct usb_module *module_inst) {
- /* USB Device Endpoint0 Configuration */
- struct usb_device_endpoint_config config_ep0;
-
- usb_device_endpoint_get_config_defaults(&config_ep0);
- config_ep0.ep_size = (enum usb_endpoint_size)(32 - clz(((uint32_t)Min(Max(USB_DEVICE_EP_CTRL_SIZE, 8), 1024) << 1) - 1) - 1 - 3);
- usb_device_endpoint_set_config(module_inst, &config_ep0);
-
- usb_device_endpoint_setup_buffer_job(module_inst, udd_ctrl_buffer);
-
- usb_device_endpoint_register_callback(module_inst, 0, USB_DEVICE_ENDPOINT_CALLBACK_RXSTP, _usb_ep0_on_setup);
- usb_device_endpoint_register_callback(module_inst, 0, USB_DEVICE_ENDPOINT_CALLBACK_TRCPT, _usb_ep0_on_tansfer_ok);
- usb_device_endpoint_register_callback(module_inst, 0, USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL, _usb_ep0_on_tansfer_fail);
- usb_device_endpoint_enable_callback(module_inst, 0, USB_DEVICE_ENDPOINT_CALLBACK_RXSTP);
- usb_device_endpoint_enable_callback(module_inst, 0, USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
- usb_device_endpoint_enable_callback(module_inst, 0, USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
-
-#ifdef USB_DEVICE_LPM_SUPPORT
- // Enable LPM feature
- usb_device_set_lpm_mode(module_inst, USB_DEVICE_LPM_ACK);
-#endif
-
- udd_ep_control_state = UDD_EPCTRL_SETUP;
-}
-
-/**
- * \internal
- * \brief Control endpoint Suspend callback function
- * \param[in] module_inst Pointer to USB module instance
- * \param[in] pointer Pointer to the callback parameter from driver layer.
- */
-static void _usb_on_suspend(struct usb_module *module_inst, void *pointer) {
- usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
- udd_sleep_mode(UDD_STATE_SUSPEND);
-#ifdef UDC_SUSPEND_EVENT
- UDC_SUSPEND_EVENT();
-#endif
-}
-
-#ifdef USB_DEVICE_LPM_SUPPORT
-static void _usb_device_lpm_suspend(struct usb_module *module_inst, void *pointer) {
- dbg_print("LPM_SUSP\n");
-
- uint32_t *lpm_wakeup_enable;
- lpm_wakeup_enable = (uint32_t *)pointer;
-
- usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
- usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
-
- //#warning Here the sleep mode must be choose to have a DFLL startup time < bmAttribut.HIRD
- udd_sleep_mode(UDD_STATE_SUSPEND_LPM); // Enter in LPM SUSPEND mode
- if ((*lpm_wakeup_enable)) {
- UDC_REMOTEWAKEUP_LPM_ENABLE();
- }
- if (!(*lpm_wakeup_enable)) {
- UDC_REMOTEWAKEUP_LPM_DISABLE();
- }
- UDC_SUSPEND_LPM_EVENT();
-}
-#endif
-
-/**
- * \internal
- * \brief Control endpoint SOF callback function
- * \param[in] module_inst Pointer to USB module instance
- * \param[in] pointer Pointer to the callback parameter from driver layer.
- */
-static void _usb_on_sof_notify(struct usb_module *module_inst, void *pointer) {
- udc_sof_notify();
-#ifdef UDC_SOF_EVENT
- UDC_SOF_EVENT();
-#endif
-}
-
-/**
- * \internal
- * \brief Control endpoint Reset callback function
- * \param[in] module_inst Pointer to USB module instance
- * \param[in] pointer Pointer to the callback parameter from driver layer.
- */
-static void _usb_on_bus_reset(struct usb_module *module_inst, void *pointer) {
- // Reset USB Device Stack Core
- udc_reset();
- usb_device_set_address(module_inst, 0);
- udd_ctrl_ep_enable(module_inst);
-}
-
-/**
- * \internal
- * \brief Control endpoint Wakeup callback function
- * \param[in] module_inst Pointer to USB module instance
- * \param[in] pointer Pointer to the callback parameter from driver layer.
- */
-static void _usb_on_wakeup(struct usb_module *module_inst, void *pointer) {
- udd_wait_clock_ready();
-
- usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
-#ifdef USB_DEVICE_LPM_SUPPORT
- usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
-#endif
- udd_sleep_mode(UDD_STATE_IDLE);
-#ifdef UDC_RESUME_EVENT
- UDC_RESUME_EVENT();
-#endif
-}
-
-void udd_detach(void) {
- usb_device_detach(&usb_device);
- udd_sleep_mode(UDD_STATE_SUSPEND);
-}
-
-void udd_attach(void) {
- udd_sleep_mode(UDD_STATE_IDLE);
- usb_device_attach(&usb_device);
-
- usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND, _usb_on_suspend);
- usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SOF, _usb_on_sof_notify);
- usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_RESET, _usb_on_bus_reset);
- usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP, _usb_on_wakeup);
-
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SOF);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_RESET);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
-#ifdef USB_DEVICE_LPM_SUPPORT
- usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
- usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
-#endif
-}
-
-void udd_enable(void) {
- uint32_t irqflags;
-
- /* To avoid USB interrupt before end of initialization */
- irqflags = __get_PRIMASK();
- __disable_irq();
- __DMB();
-
- struct usb_config config_usb;
-
- /* USB Module configuration */
- usb_get_config_defaults(&config_usb);
- config_usb.source_generator = UDD_CLOCK_GEN;
- usb_init(&usb_device, USB, &config_usb);
-
- /* USB Module Enable */
- usb_enable(&usb_device);
-
- /* Check clock after enable module, request the clock */
- udd_wait_clock_ready();
-
- udd_sleep_mode(UDD_STATE_SUSPEND);
-
- // No VBus detect, assume always high
-#ifndef USB_DEVICE_ATTACH_AUTO_DISABLE
- udd_attach();
-#endif
-
- __DMB();
- __set_PRIMASK(irqflags);
-}
-
-void udd_disable(void) {
- udd_detach();
-
- udd_sleep_mode(UDD_STATE_OFF);
-}
-/** @} */
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_hub.c b/tmk_core/protocol/arm_atsam/usb/usb_hub.c
deleted file mode 100644
index 14fba799c797..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_hub.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#include "arm_atsam_protocol.h"
-#include "drivers/usb2422.h"
-#include
-
-uint8_t usb_host_port;
-
-#ifndef MD_BOOTLOADER
-
-uint8_t usb_extra_state;
-uint8_t usb_extra_manual;
-uint8_t usb_gcr_auto;
-
-#endif // MD_BOOTLOADER
-
-uint16_t adc_extra;
-
-void USB_Hub_init(void) {
- Gclk * pgclk = GCLK;
- Mclk * pmclk = MCLK;
- Port * pport = PORT;
- Oscctrl *posc = OSCCTRL;
- Usb * pusb = USB;
-
- DBGC(DC_USB2422_INIT_BEGIN);
-
- while ((v_5v = adc_get(ADC_5V)) < ADC_5V_START_LEVEL) {
- DBGC(DC_USB2422_INIT_WAIT_5V_LOW);
- }
-
- // setup peripheral and synchronous bus clocks to USB
- pgclk->PCHCTRL[10].bit.GEN = 0;
- pgclk->PCHCTRL[10].bit.CHEN = 1;
- pmclk->AHBMASK.bit.USB_ = 1;
- pmclk->APBBMASK.bit.USB_ = 1;
-
- // setup port pins for D-, D+, and SOF_1KHZ
- pport->Group[0].PMUX[12].reg = 0x77; // PA24, PA25, function column H for USB D-, D+
- pport->Group[0].PINCFG[24].bit.PMUXEN = 1;
- pport->Group[0].PINCFG[25].bit.PMUXEN = 1;
- pport->Group[1].PMUX[11].bit.PMUXE = 7; // PB22, function column H for USB SOF_1KHz output
- pport->Group[1].PINCFG[22].bit.PMUXEN = 1;
-
- // configure and enable DFLL for USB clock recovery mode at 48MHz
- posc->DFLLCTRLA.bit.ENABLE = 0;
- while (posc->DFLLSYNC.bit.ENABLE) {
- DBGC(DC_USB2422_INIT_OSC_SYNC_DISABLING);
- }
- while (posc->DFLLSYNC.bit.DFLLCTRLB) {
- DBGC(DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_1);
- }
- posc->DFLLCTRLB.bit.USBCRM = 1;
- while (posc->DFLLSYNC.bit.DFLLCTRLB) {
- DBGC(DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_2);
- }
- posc->DFLLCTRLB.bit.MODE = 1;
- while (posc->DFLLSYNC.bit.DFLLCTRLB) {
- DBGC(DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_3);
- }
- posc->DFLLCTRLB.bit.QLDIS = 0;
- while (posc->DFLLSYNC.bit.DFLLCTRLB) {
- DBGC(DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_4);
- }
- posc->DFLLCTRLB.bit.CCDIS = 1;
- posc->DFLLMUL.bit.MUL = 0xBB80; // 4800 x 1KHz
- while (posc->DFLLSYNC.bit.DFLLMUL) {
- DBGC(DC_USB2422_INIT_OSC_SYNC_DFLLMUL);
- }
- posc->DFLLCTRLA.bit.ENABLE = 1;
- while (posc->DFLLSYNC.bit.ENABLE) {
- DBGC(DC_USB2422_INIT_OSC_SYNC_ENABLING);
- }
-
- pusb->DEVICE.CTRLA.bit.SWRST = 1;
- while (pusb->DEVICE.SYNCBUSY.bit.SWRST) {
- DBGC(DC_USB2422_INIT_USB_SYNC_SWRST);
- }
- while (pusb->DEVICE.CTRLA.bit.SWRST) {
- DBGC(DC_USB2422_INIT_USB_WAIT_SWRST);
- }
- // calibration from factory presets
- pusb->DEVICE.PADCAL.bit.TRANSN = (USB_FUSES_TRANSN_ADDR >> USB_FUSES_TRANSN_Pos) & USB_FUSES_TRANSN_Msk;
- pusb->DEVICE.PADCAL.bit.TRANSP = (USB_FUSES_TRANSP_ADDR >> USB_FUSES_TRANSP_Pos) & USB_FUSES_TRANSP_Msk;
- pusb->DEVICE.PADCAL.bit.TRIM = (USB_FUSES_TRIM_ADDR >> USB_FUSES_TRIM_Pos) & USB_FUSES_TRIM_Msk;
- // device mode, enabled
- pusb->DEVICE.CTRLB.bit.SPDCONF = 0; // full speed
- pusb->DEVICE.CTRLA.bit.MODE = 0;
- pusb->DEVICE.CTRLA.bit.ENABLE = 1;
- while (pusb->DEVICE.SYNCBUSY.bit.ENABLE) {
- DBGC(DC_USB2422_INIT_USB_SYNC_ENABLING);
- }
-
- pusb->DEVICE.QOSCTRL.bit.DQOS = 2;
- pusb->DEVICE.QOSCTRL.bit.CQOS = 2;
-
- USB2422_init();
-
- sr_exp_data.bit.HUB_CONNECT = 1; // connect signal
- sr_exp_data.bit.HUB_RESET_N = 1; // reset high
- SR_EXP_WriteData();
-
- wait_us(100);
-
-#ifndef MD_BOOTLOADER
-
- usb_extra_manual = 0;
- usb_gcr_auto = 1;
-
-#endif // MD_BOOTLOADER
-
- DBGC(DC_USB2422_INIT_COMPLETE);
-}
-
-void USB_reset(void) {
- DBGC(DC_USB_RESET_BEGIN);
-
- // pulse reset for at least 1 usec
- sr_exp_data.bit.HUB_RESET_N = 0; // reset low
- SR_EXP_WriteData();
- wait_us(2);
- sr_exp_data.bit.HUB_RESET_N = 1; // reset high to run
- SR_EXP_WriteData();
-
- DBGC(DC_USB_RESET_COMPLETE);
-}
-
-void USB_configure(void) {
- DBGC(DC_USB_CONFIGURE_BEGIN);
-
- USB2422_configure();
-
- adc_extra = 0;
-
- DBGC(DC_USB_CONFIGURE_COMPLETE);
-}
-
-uint16_t USB_active(void) {
- return USB2422_active();
-}
-
-void USB_set_host_by_voltage(void) {
- // UP is upstream device (HOST)
- // DN1 is downstream device (EXTRA)
- // DN2 is keyboard (KEYB)
-
- DBGC(DC_USB_SET_HOST_BY_VOLTAGE_BEGIN);
-
- usb_host_port = USB_HOST_PORT_UNKNOWN;
-#ifndef MD_BOOTLOADER
- usb_extra_state = USB_EXTRA_STATE_UNKNOWN;
-#endif // MD_BOOTLOADER
- sr_exp_data.bit.SRC_1 = 1; // USBC-1 available for test
- sr_exp_data.bit.SRC_2 = 1; // USBC-2 available for test
- sr_exp_data.bit.E_UP_N = 1; // HOST disable
- sr_exp_data.bit.E_DN1_N = 1; // EXTRA disable
- sr_exp_data.bit.E_VBUS_1 = 0; // USBC-1 disable full power I/O
- sr_exp_data.bit.E_VBUS_2 = 0; // USBC-2 disable full power I/O
-
- SR_EXP_WriteData();
-
- wait_ms(250);
-
- while ((v_5v = adc_get(ADC_5V)) < ADC_5V_START_LEVEL) {
- DBGC(DC_USB_SET_HOST_5V_LOW_WAITING);
- }
-
- v_con_1 = adc_get(ADC_CON1);
- v_con_2 = adc_get(ADC_CON2);
-
- v_con_1_boot = v_con_1;
- v_con_2_boot = v_con_2;
-
- if (v_con_1 > v_con_2) {
- sr_exp_data.bit.S_UP = 0; // HOST to USBC-1
- sr_exp_data.bit.S_DN1 = 1; // EXTRA to USBC-2
- sr_exp_data.bit.SRC_1 = 1; // HOST on USBC-1
- sr_exp_data.bit.SRC_2 = 0; // EXTRA available on USBC-2
-
- sr_exp_data.bit.E_VBUS_1 = 1; // USBC-1 enable full power I/O
- sr_exp_data.bit.E_VBUS_2 = 0; // USBC-2 disable full power I/O
-
- SR_EXP_WriteData();
-
- sr_exp_data.bit.E_UP_N = 0; // HOST enable
-
- SR_EXP_WriteData();
-
- usb_host_port = USB_HOST_PORT_1;
- } else {
- sr_exp_data.bit.S_UP = 1; // EXTRA to USBC-1
- sr_exp_data.bit.S_DN1 = 0; // HOST to USBC-2
- sr_exp_data.bit.SRC_1 = 0; // EXTRA available on USBC-1
- sr_exp_data.bit.SRC_2 = 1; // HOST on USBC-2
-
- sr_exp_data.bit.E_VBUS_1 = 0; // USBC-1 disable full power I/O
- sr_exp_data.bit.E_VBUS_2 = 1; // USBC-2 enable full power I/O
-
- SR_EXP_WriteData();
-
- sr_exp_data.bit.E_UP_N = 0; // HOST enable
-
- SR_EXP_WriteData();
-
- usb_host_port = USB_HOST_PORT_2;
- }
-
-#ifndef MD_BOOTLOADER
- usb_extra_state = USB_EXTRA_STATE_DISABLED;
-#endif // MD_BOOTLOADER
-
- USB_reset();
- USB_configure();
-
- DBGC(DC_USB_SET_HOST_BY_VOLTAGE_COMPLETE);
-}
-
-uint8_t USB_Hub_Port_Detect_Init(void) {
- uint32_t port_detect_retry_ms;
- uint32_t tmod;
-
- DBGC(DC_PORT_DETECT_INIT_BEGIN);
-
- USB_set_host_by_voltage();
-
- port_detect_retry_ms = timer_read64() + PORT_DETECT_RETRY_INTERVAL;
-
- while (!USB_active()) {
- tmod = timer_read64() % PORT_DETECT_RETRY_INTERVAL;
-
- if (v_con_1 > v_con_2) // Values updated from USB_set_host_by_voltage();
- {
- // 1 flash for port 1 detected
- if (tmod > 500 && tmod < 600) {
- DBG_LED_ON;
- } else {
- DBG_LED_OFF;
- }
- } else if (v_con_2 > v_con_1) // Values updated from USB_set_host_by_voltage();
- {
- // 2 flash for port 2 detected
- if (tmod > 500 && tmod < 600) {
- DBG_LED_ON;
- } else if (tmod > 700 && tmod < 800) {
- DBG_LED_ON;
- } else {
- DBG_LED_OFF;
- }
- }
-
- if (timer_read64() > port_detect_retry_ms) {
- DBGC(DC_PORT_DETECT_INIT_FAILED);
- return 0;
- }
- }
-
- DBGC(DC_PORT_DETECT_INIT_COMPLETE);
-
- return 1;
-}
-
-#ifndef MD_BOOTLOADER
-
-void USB_ExtraSetState(uint8_t state) {
- uint8_t state_save = state;
-
- if (state == USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG) state = USB_EXTRA_STATE_DISABLED;
-
- if (usb_host_port == USB_HOST_PORT_1)
- sr_exp_data.bit.E_VBUS_2 = state;
- else if (usb_host_port == USB_HOST_PORT_2)
- sr_exp_data.bit.E_VBUS_1 = state;
- else
- return;
-
- sr_exp_data.bit.E_DN1_N = !state;
- SR_EXP_WriteData();
-
- usb_extra_state = state_save;
-
- if (usb_extra_state == USB_EXTRA_STATE_ENABLED)
- CDC_print("USB: Extra enabled\r\n");
- else if (usb_extra_state == USB_EXTRA_STATE_DISABLED) {
- CDC_print("USB: Extra disabled\r\n");
-# ifdef USE_MASSDROP_CONFIGURATOR
- if (led_animation_breathing) gcr_breathe = gcr_desired;
-# endif
- } else if (usb_extra_state == USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG)
- CDC_print("USB: Extra disabled until replug\r\n");
- else
- CDC_print("USB: Extra state unknown\r\n");
-}
-
-void USB_HandleExtraDevice(void) {
- uint16_t adcval;
-
- if (usb_host_port == USB_HOST_PORT_1)
- adcval = adc_get(ADC_CON2);
- else if (usb_host_port == USB_HOST_PORT_2)
- adcval = adc_get(ADC_CON1);
- else
- return;
-
- adc_extra = adc_extra * 0.9 + adcval * 0.1;
-
- // Check for a forced disable state (such as overload prevention)
- if (usb_extra_state == USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG) {
- // Detect unplug and reset state to disabled
- if (adc_extra > USB_EXTRA_ADC_THRESHOLD) usb_extra_state = USB_EXTRA_STATE_DISABLED;
-
- return; // Return even if unplug detected
- }
-
- if (usb_extra_manual) {
- if (usb_extra_state == USB_EXTRA_STATE_DISABLED) USB_ExtraSetState(USB_EXTRA_STATE_ENABLED);
-
- return;
- }
-
- // dpf("a %i %i\r\n",adcval, adc_extra);
- if (usb_extra_state == USB_EXTRA_STATE_DISABLED && adc_extra < USB_EXTRA_ADC_THRESHOLD)
- USB_ExtraSetState(USB_EXTRA_STATE_ENABLED);
- else if (usb_extra_state == USB_EXTRA_STATE_ENABLED && adc_extra > USB_EXTRA_ADC_THRESHOLD)
- USB_ExtraSetState(USB_EXTRA_STATE_DISABLED);
-}
-
-#endif // MD_BOOTLOADER
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_hub.h b/tmk_core/protocol/arm_atsam/usb/usb_hub.h
deleted file mode 100644
index d7b2e3fab445..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_hub.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
-Copyright 2018 Massdrop Inc.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
-*/
-
-#ifndef _USB2422_H_
-#define _USB2422_H_
-
-#define REV_USB2422 0x100
-
-#define PORT_DETECT_RETRY_INTERVAL 2000
-
-#define USB_EXTRA_ADC_THRESHOLD 900
-
-#define USB_EXTRA_STATE_DISABLED 0
-#define USB_EXTRA_STATE_ENABLED 1
-#define USB_EXTRA_STATE_UNKNOWN 2
-#define USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG 3
-
-#define USB_HOST_PORT_1 0
-#define USB_HOST_PORT_2 1
-#define USB_HOST_PORT_UNKNOWN 2
-
-extern uint8_t usb_host_port;
-extern uint8_t usb_extra_state;
-extern uint8_t usb_extra_manual;
-extern uint8_t usb_gcr_auto;
-
-void USB_Hub_init(void);
-uint8_t USB_Hub_Port_Detect_Init(void);
-void USB_reset(void);
-void USB_configure(void);
-uint16_t USB_active(void);
-void USB_set_host_by_voltage(void);
-uint16_t adc_get(uint8_t muxpos);
-void USB_HandleExtraDevice(void);
-void USB_ExtraSetState(uint8_t state);
-
-#endif //_USB2422_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_main.h b/tmk_core/protocol/arm_atsam/usb/usb_main.h
deleted file mode 100644
index c3b1698c594c..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_main.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- * \file
- *
- * \brief Declaration of main function used by HID keyboard example
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _MAIN_H_
-#define _MAIN_H_
-
-// Enters the application in low power mode
-// Callback called when USB host sets USB line in suspend state
-void main_suspend_action(void);
-
-// Called by UDD when the USB line exit of suspend state
-void main_resume_action(void);
-
-// Called when a start of frame is received on USB line
-void main_sof_action(void);
-
-// Called by UDC when USB Host request to enable remote wakeup
-void main_remotewakeup_enable(void);
-
-// Called by UDC when USB Host request to disable remote wakeup
-void main_remotewakeup_disable(void);
-
-extern volatile bool main_b_kbd_enable;
-bool main_kbd_enable(void);
-void main_kbd_disable(void);
-
-#ifdef NKRO_ENABLE
-extern volatile bool main_b_nkro_enable;
-bool main_nkro_enable(void);
-void main_nkro_disable(void);
-#endif // NKRO_ENABLE
-
-#ifdef EXTRAKEY_ENABLE
-extern volatile bool main_b_exk_enable;
-bool main_exk_enable(void);
-void main_exk_disable(void);
-#endif // EXTRAKEY_ENABLE
-
-#ifdef CONSOLE_ENABLE
-extern volatile bool main_b_con_enable;
-bool main_con_enable(void);
-void main_con_disable(void);
-#endif // CONSOLE_ENABLE
-
-#ifdef MOUSE_ENABLE
-extern volatile bool main_b_mou_enable;
-bool main_mou_enable(void);
-void main_mou_disable(void);
-#endif // MOUSE_ENABLE
-
-#ifdef RAW_ENABLE
-extern volatile bool main_b_raw_enable;
-bool main_raw_enable(void);
-void main_raw_disable(void);
-void main_raw_receive(uint8_t *buffer, uint8_t len);
-#endif // RAW_ENABLE
-
-#endif // _MAIN_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_protocol.h b/tmk_core/protocol/arm_atsam/usb/usb_protocol.h
deleted file mode 100644
index 639b80a80401..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_protocol.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/**
- * \file
- *
- * \brief USB protocol definitions.
- *
- * This file contains the USB definitions and data structures provided by the
- * USB 2.0 specification.
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _USB_PROTOCOL_H_
-#define _USB_PROTOCOL_H_
-
-#include "usb_atmel.h"
-
-/**
- * \ingroup usb_group
- * \defgroup usb_protocol_group USB Protocol Definitions
- *
- * This module defines constants and data structures provided by the USB
- * 2.0 specification.
- *
- * @{
- */
-
-//! Value for field bcdUSB
-#define USB_V2_0 0x0200 //!< USB Specification version 2.00
-#define USB_V2_1 0x0201 //!< USB Specification version 2.01
-
-/*! \name Generic definitions (Class, subclass and protocol)
- */
-//! @{
-#define NO_CLASS 0x00
-#define CLASS_VENDOR_SPECIFIC 0xFF
-#define NO_SUBCLASS 0x00
-#define NO_PROTOCOL 0x00
-//! @}
-
-//! \name IAD (Interface Association Descriptor) constants
-//! @{
-#define CLASS_IAD 0xEF
-#define SUB_CLASS_IAD 0x02
-#define PROTOCOL_IAD 0x01
-//! @}
-
-/**
- * \brief USB request data transfer direction (bmRequestType)
- */
-#define USB_REQ_DIR_OUT (0 << 7) //!< Host to device
-#define USB_REQ_DIR_IN (1 << 7) //!< Device to host
-#define USB_REQ_DIR_MASK (1 << 7) //!< Mask
-
-/**
- * \brief USB request types (bmRequestType)
- */
-#define USB_REQ_TYPE_STANDARD (0 << 5) //!< Standard request
-#define USB_REQ_TYPE_CLASS (1 << 5) //!< Class-specific request
-#define USB_REQ_TYPE_VENDOR (2 << 5) //!< Vendor-specific request
-#define USB_REQ_TYPE_MASK (3 << 5) //!< Mask
-
-/**
- * \brief USB recipient codes (bmRequestType)
- */
-#define USB_REQ_RECIP_DEVICE (0 << 0) //!< Recipient device
-#define USB_REQ_RECIP_INTERFACE (1 << 0) //!< Recipient interface
-#define USB_REQ_RECIP_ENDPOINT (2 << 0) //!< Recipient endpoint
-#define USB_REQ_RECIP_OTHER (3 << 0) //!< Recipient other
-#define USB_REQ_RECIP_MASK (0x1F) //!< Mask
-
-/**
- * \brief Standard USB requests (bRequest)
- */
-enum usb_reqid {
- USB_REQ_GET_STATUS = 0,
- USB_REQ_CLEAR_FEATURE = 1,
- USB_REQ_SET_FEATURE = 3,
- USB_REQ_SET_ADDRESS = 5,
- USB_REQ_GET_DESCRIPTOR = 6,
- USB_REQ_SET_DESCRIPTOR = 7,
- USB_REQ_GET_CONFIGURATION = 8,
- USB_REQ_SET_CONFIGURATION = 9,
- USB_REQ_GET_INTERFACE = 10,
- USB_REQ_SET_INTERFACE = 11,
- USB_REQ_SYNCH_FRAME = 12,
-};
-
-/**
- * \brief Standard USB device status flags
- *
- */
-enum usb_device_status { USB_DEV_STATUS_BUS_POWERED = 0, USB_DEV_STATUS_SELF_POWERED = 1, USB_DEV_STATUS_REMOTEWAKEUP = 2 };
-
-/**
- * \brief Standard USB Interface status flags
- *
- */
-enum usb_interface_status { USB_IFACE_STATUS_RESERVED = 0 };
-
-/**
- * \brief Standard USB endpoint status flags
- *
- */
-enum usb_endpoint_status {
- USB_EP_STATUS_HALTED = 1,
-};
-
-/**
- * \brief Standard USB device feature flags
- *
- * \note valid for SetFeature request.
- */
-enum usb_device_feature {
- USB_DEV_FEATURE_REMOTE_WAKEUP = 1, //!< Remote wakeup enabled
- USB_DEV_FEATURE_TEST_MODE = 2, //!< USB test mode
- USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3,
- USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4,
- USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5
-};
-
-/**
- * \brief Test Mode possible on HS USB device
- *
- * \note valid for USB_DEV_FEATURE_TEST_MODE request.
- */
-enum usb_device_hs_test_mode {
- USB_DEV_TEST_MODE_J = 1,
- USB_DEV_TEST_MODE_K = 2,
- USB_DEV_TEST_MODE_SE0_NAK = 3,
- USB_DEV_TEST_MODE_PACKET = 4,
- USB_DEV_TEST_MODE_FORCE_ENABLE = 5,
-};
-
-/**
- * \brief Standard USB endpoint feature/status flags
- */
-enum usb_endpoint_feature {
- USB_EP_FEATURE_HALT = 0,
-};
-
-/**
- * \brief Standard USB Test Mode Selectors
- */
-enum usb_test_mode_selector {
- USB_TEST_J = 0x01,
- USB_TEST_K = 0x02,
- USB_TEST_SE0_NAK = 0x03,
- USB_TEST_PACKET = 0x04,
- USB_TEST_FORCE_ENABLE = 0x05,
-};
-
-/**
- * \brief Standard USB descriptor types
- */
-enum usb_descriptor_type {
- USB_DT_DEVICE = 1,
- USB_DT_CONFIGURATION = 2,
- USB_DT_STRING = 3,
- USB_DT_INTERFACE = 4,
- USB_DT_ENDPOINT = 5,
- USB_DT_DEVICE_QUALIFIER = 6,
- USB_DT_OTHER_SPEED_CONFIGURATION = 7,
- USB_DT_INTERFACE_POWER = 8,
- USB_DT_OTG = 9,
- USB_DT_IAD = 0x0B,
- USB_DT_BOS = 0x0F,
- USB_DT_DEVICE_CAPABILITY = 0x10,
-};
-
-/**
- * \brief USB Device Capability types
- */
-enum usb_capability_type {
- USB_DC_USB20_EXTENSION = 0x02,
-};
-
-/**
- * \brief USB Device Capability - USB 2.0 Extension
- * To fill bmAttributes field of usb_capa_ext_desc_t structure.
- */
-enum usb_capability_extension_attr {
- USB_DC_EXT_LPM = 0x00000002,
-};
-
-#define HIRD_50_US 0
-#define HIRD_125_US 1
-#define HIRD_200_US 2
-#define HIRD_275_US 3
-#define HIRD_350_US 4
-#define HIRD_425_US 5
-#define HIRD_500_US 6
-#define HIRD_575_US 7
-#define HIRD_650_US 8
-#define HIRD_725_US 9
-#define HIRD_800_US 10
-#define HIRD_875_US 11
-#define HIRD_950_US 12
-#define HIRD_1025_US 13
-#define HIRD_1100_US 14
-#define HIRD_1175_US 15
-
-/** Fields definition from a LPM TOKEN */
-#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0)
-#define USB_LPM_ATTRIBUT_FIRD_MASK (0xF << 4)
-#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8)
-#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0)
-#define USB_LPM_ATTRIBUT_FIRD(value) ((value & 0xF) << 4)
-#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8)
-#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1)
-
-/**
- * \brief Standard USB endpoint transfer types
- */
-enum usb_ep_type {
- USB_EP_TYPE_CONTROL = 0x00,
- USB_EP_TYPE_ISOCHRONOUS = 0x01,
- USB_EP_TYPE_BULK = 0x02,
- USB_EP_TYPE_INTERRUPT = 0x03,
- USB_EP_TYPE_MASK = 0x03,
-};
-
-/**
- * \brief Standard USB language IDs for string descriptors
- */
-enum usb_langid {
- USB_LANGID_EN_US = 0x0409, //!< English (United States)
-};
-
-/**
- * \brief Mask selecting the index part of an endpoint address
- */
-#define USB_EP_ADDR_MASK 0x0f
-
-//! \brief USB address identifier
-typedef uint8_t usb_add_t;
-
-/**
- * \brief Endpoint transfer direction is IN
- */
-#define USB_EP_DIR_IN 0x80
-
-/**
- * \brief Endpoint transfer direction is OUT
- */
-#define USB_EP_DIR_OUT 0x00
-
-//! \brief Endpoint identifier
-typedef uint8_t usb_ep_t;
-
-/**
- * \brief Maximum length in bytes of a USB descriptor
- *
- * The maximum length of a USB descriptor is limited by the 8-bit
- * bLength field.
- */
-#define USB_MAX_DESC_LEN 255
-
-/*
- * 2-byte alignment requested for all USB structures.
- */
-COMPILER_PACK_SET(1)
-
-/**
- * \brief A USB Device SETUP request
- *
- * The data payload of SETUP packets always follows this structure.
- */
-typedef struct {
- uint8_t bmRequestType;
- uint8_t bRequest;
- le16_t wValue;
- le16_t wIndex;
- le16_t wLength;
-} usb_setup_req_t;
-
-/**
- * \brief Standard USB device descriptor structure
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- le16_t bcdUSB;
- uint8_t bDeviceClass;
- uint8_t bDeviceSubClass;
- uint8_t bDeviceProtocol;
- uint8_t bMaxPacketSize0;
- le16_t idVendor;
- le16_t idProduct;
- le16_t bcdDevice;
- uint8_t iManufacturer;
- uint8_t iProduct;
- uint8_t iSerialNumber;
- uint8_t bNumConfigurations;
-} usb_dev_desc_t;
-
-/**
- * \brief Standard USB device qualifier descriptor structure
- *
- * This descriptor contains information about the device when running at
- * the "other" speed (i.e. if the device is currently operating at high
- * speed, this descriptor can be used to determine what would change if
- * the device was operating at full speed.)
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- le16_t bcdUSB;
- uint8_t bDeviceClass;
- uint8_t bDeviceSubClass;
- uint8_t bDeviceProtocol;
- uint8_t bMaxPacketSize0;
- uint8_t bNumConfigurations;
- uint8_t bReserved;
-} usb_dev_qual_desc_t;
-
-/**
- * \brief USB Device BOS descriptor structure
- *
- * The BOS descriptor (Binary device Object Store) defines a root
- * descriptor that is similar to the configuration descriptor, and is
- * the base descriptor for accessing a family of related descriptors.
- * A host can read a BOS descriptor and learn from the wTotalLength field
- * the entire size of the device-level descriptor set, or it can read in
- * the entire BOS descriptor set of device capabilities.
- * The host accesses this descriptor using the GetDescriptor() request.
- * The descriptor type in the GetDescriptor() request is set to BOS.
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- le16_t wTotalLength;
- uint8_t bNumDeviceCaps;
-} usb_dev_bos_desc_t;
-
-/**
- * \brief USB Device Capabilities - USB 2.0 Extension Descriptor structure
- *
- * Defines the set of USB 1.1-specific device level capabilities.
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bDevCapabilityType;
- le32_t bmAttributes;
-} usb_dev_capa_ext_desc_t;
-
-/**
- * \brief USB Device LPM Descriptor structure
- *
- * The BOS descriptor and capabilities descriptors for LPM.
- */
-typedef struct {
- usb_dev_bos_desc_t bos;
- usb_dev_capa_ext_desc_t capa_ext;
-} usb_dev_lpm_desc_t;
-
-/**
- * \brief Standard USB Interface Association Descriptor structure
- */
-typedef struct {
- uint8_t bLength; //!< size of this descriptor in bytes
- uint8_t bDescriptorType; //!< INTERFACE descriptor type
- uint8_t bFirstInterface; //!< Number of interface
- uint8_t bInterfaceCount; //!< value to select alternate setting
- uint8_t bFunctionClass; //!< Class code assigned by the USB
- uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB
- uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB
- uint8_t iFunction; //!< Index of string descriptor
-} usb_association_desc_t;
-
-/**
- * \brief Standard USB configuration descriptor structure
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- le16_t wTotalLength;
- uint8_t bNumInterfaces;
- uint8_t bConfigurationValue;
- uint8_t iConfiguration;
- uint8_t bmAttributes;
- uint8_t bMaxPower;
-} usb_conf_desc_t;
-
-#define USB_CONFIG_ATTR_MUST_SET (1 << 7) //!< Must always be set
-#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) //!< Bus-powered
-#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) //!< Self-powered
-#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) //!< remote wakeup supported
-
-#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) //!< Max power in mA
-
-/**
- * \brief Standard USB association descriptor structure
- */
-typedef struct {
- uint8_t bLength; //!< Size of this descriptor in bytes
- uint8_t bDescriptorType; //!< Interface descriptor type
- uint8_t bFirstInterface; //!< Number of interface
- uint8_t bInterfaceCount; //!< value to select alternate setting
- uint8_t bFunctionClass; //!< Class code assigned by the USB
- uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB
- uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB
- uint8_t iFunction; //!< Index of string descriptor
-} usb_iad_desc_t;
-
-/**
- * \brief Standard USB interface descriptor structure
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bInterfaceNumber;
- uint8_t bAlternateSetting;
- uint8_t bNumEndpoints;
- uint8_t bInterfaceClass;
- uint8_t bInterfaceSubClass;
- uint8_t bInterfaceProtocol;
- uint8_t iInterface;
-} usb_iface_desc_t;
-
-/**
- * \brief Standard USB endpoint descriptor structure
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bEndpointAddress;
- uint8_t bmAttributes;
- le16_t wMaxPacketSize;
- uint8_t bInterval;
-} usb_ep_desc_t;
-
-/**
- * \brief A standard USB string descriptor structure
- */
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
-} usb_str_desc_t;
-
-typedef struct {
- usb_str_desc_t desc;
- le16_t string[1];
-} usb_str_lgid_desc_t;
-
-COMPILER_PACK_RESET()
-
-//! @}
-
-#endif /* _USB_PROTOCOL_H_ */
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_protocol_cdc.h b/tmk_core/protocol/arm_atsam/usb/usb_protocol_cdc.h
deleted file mode 100644
index 1d36d58dbdc0..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_protocol_cdc.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
- * \file
- *
- * \brief USB Communication Device Class (CDC) protocol definitions
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-#ifndef _USB_PROTOCOL_CDC_H_
-#define _USB_PROTOCOL_CDC_H_
-
-#include "compiler.h"
-
-#ifdef VIRTSER_ENABLE
-
-# define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class
-# define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface
-# define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface
-
-# define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model
-# define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model
-# define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model
-# define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model
-# define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model
-# define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model
-# define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model
-
-# define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands
-
-# define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI
-# define CDC_PROTOCOL_HDLC 0x31 //!< HDLC
-# define CDC_PROTOCOL_TRANS 0x32 //!< Transparent
-# define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol
-# define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol
-# define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor
-# define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures
-# define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control
-# define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN
-# define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands
-# define CDC_PROTOCOL_HOST 0xFD //!< Host based driver
-
-# define CDC_PROTOCOL_PUFD 0xFE
-
-# define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor
-# define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor
-
-# define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor
-# define CDC_SCS_CALL_MGMT 0x01 //!< Call Management
-# define CDC_SCS_ACM 0x02 //!< Abstract Control Management
-# define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor
-
-# define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00
-# define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01
-# define USB_REQ_CDC_SET_COMM_FEATURE 0x02
-# define USB_REQ_CDC_GET_COMM_FEATURE 0x03
-# define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04
-# define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10
-# define USB_REQ_CDC_SET_HOOK_STATE 0x11
-# define USB_REQ_CDC_PULSE_SETUP 0x12
-# define USB_REQ_CDC_SEND_PULSE 0x13
-# define USB_REQ_CDC_SET_PULSE_TIME 0x14
-# define USB_REQ_CDC_RING_AUX_JACK 0x15
-# define USB_REQ_CDC_SET_LINE_CODING 0x20
-# define USB_REQ_CDC_GET_LINE_CODING 0x21
-# define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22
-# define USB_REQ_CDC_SEND_BREAK 0x23
-# define USB_REQ_CDC_SET_RINGER_PARMS 0x30
-# define USB_REQ_CDC_GET_RINGER_PARMS 0x31
-# define USB_REQ_CDC_SET_OPERATION_PARMS 0x32
-# define USB_REQ_CDC_GET_OPERATION_PARMS 0x33
-# define USB_REQ_CDC_SET_LINE_PARMS 0x34
-# define USB_REQ_CDC_GET_LINE_PARMS 0x35
-# define USB_REQ_CDC_DIAL_DIGITS 0x36
-# define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37
-# define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38
-# define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39
-# define USB_REQ_CDC_GET_PROFILE 0x3A
-# define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
-# define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41
-# define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42
-# define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43
-# define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44
-# define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50
-# define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51
-# define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52
-# define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53
-// Added bNotification codes according cdc spec 1.1 chapter 6.3
-# define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09
-# define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20
-# define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28
-# define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29
-
-# define CDC_CALL_MGMT_SUPPORTED (1 << 0)
-# define CDC_CALL_MGMT_OVER_DCI (1 << 1)
-# define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0)
-# define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1)
-# define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2)
-# define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3)
-
-# pragma pack(push, 1)
-typedef struct {
- le32_t dwDTERate;
- uint8_t bCharFormat;
- uint8_t bParityType;
- uint8_t bDataBits;
-} usb_cdc_line_coding_t;
-# pragma pack(pop)
-
-enum cdc_char_format {
- CDC_STOP_BITS_1 = 0, //!< 1 stop bit
- CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits
- CDC_STOP_BITS_2 = 2, //!< 2 stop bits
-};
-
-enum cdc_parity {
- CDC_PAR_NONE = 0, //!< No parity
- CDC_PAR_ODD = 1, //!< Odd parity
- CDC_PAR_EVEN = 2, //!< Even parity
- CDC_PAR_MARK = 3, //!< Parity forced to 0 (space)
- CDC_PAR_SPACE = 4, //!< Parity forced to 1 (mark)
-};
-
-typedef struct {
- uint16_t value;
-} usb_cdc_control_signal_t;
-
-# define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1)
-# define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0)
-
-typedef struct {
- uint8_t bmRequestType;
- uint8_t bNotification;
- le16_t wValue;
- le16_t wIndex;
- le16_t wLength;
-} usb_cdc_notify_msg_t;
-
-typedef struct {
- usb_cdc_notify_msg_t header;
- le16_t value;
-} usb_cdc_notify_serial_state_t;
-
-# define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1 << 0))
-# define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1 << 1))
-# define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1 << 2))
-# define CDC_SERIAL_STATE_RING CPU_TO_LE16((1 << 3))
-# define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1 << 4))
-# define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1 << 5))
-# define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1 << 6))
-
-#endif
-
-#endif // _USB_PROTOCOL_CDC_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_protocol_hid.h b/tmk_core/protocol/arm_atsam/usb/usb_protocol_hid.h
deleted file mode 100644
index c984c0762f07..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_protocol_hid.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/**
- * \file
- *
- * \brief USB Human Interface Device (HID) protocol definitions.
- *
- * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit Atmel Support
- */
-
-#ifndef _USB_PROTOCOL_HID_H_
-#define _USB_PROTOCOL_HID_H_
-
-/**
- * \ingroup usb_protocol_group
- * \defgroup usb_hid_protocol USB Human Interface Device (HID)
- * protocol definitions
- * \brief USB Human Interface Device (HID) protocol definitions
- *
- * @{
- */
-
-//! \name Possible Class value
-//@{
-#define HID_CLASS 0x03
-//@}
-
-//! \name Possible SubClass value
-//@{
-//! Interface subclass NO support BOOT protocol
-#define HID_SUB_CLASS_NOBOOT 0x00
-//! Interface subclass support BOOT protocol
-#define HID_SUB_CLASS_BOOT 0x01
-//@}
-
-//! \name Possible protocol value
-//@{
-//! Protocol generic standard
-#define HID_PROTOCOL_GENERIC 0x00
-//! Protocol keyboard standard
-#define HID_PROTOCOL_KEYBOARD 0x01
-//! Protocol mouse standard
-#define HID_PROTOCOL_MOUSE 0x02
-//@}
-
-//! \brief Hid USB requests (bRequest)
-enum usb_reqid_hid {
- USB_REQ_HID_GET_REPORT = 0x01,
- USB_REQ_HID_GET_IDLE = 0x02,
- USB_REQ_HID_GET_PROTOCOL = 0x03,
- USB_REQ_HID_SET_REPORT = 0x09,
- USB_REQ_HID_SET_IDLE = 0x0A,
- USB_REQ_HID_SET_PROTOCOL = 0x0B,
-};
-
-//! \brief HID USB descriptor types
-enum usb_descriptor_type_hid {
- USB_DT_HID = 0x21,
- USB_DT_HID_REPORT = 0x22,
- USB_DT_HID_PHYSICAL = 0x23,
-};
-
-//! \brief HID Type for report descriptor
-enum usb_hid_item_report_type {
- USB_HID_ITEM_REPORT_TYPE_MAIN = 0,
- USB_HID_ITEM_REPORT_TYPE_GLOBAL = 1,
- USB_HID_ITEM_REPORT_TYPE_LOCAL = 2,
- USB_HID_ITEM_REPORT_TYPE_LONG = 3,
-};
-
-//! \brief HID report type
-enum usb_hid_report_type {
- USB_HID_REPORT_TYPE_INPUT = 1,
- USB_HID_REPORT_TYPE_OUTPUT = 2,
- USB_HID_REPORT_TYPE_FEATURE = 3,
-};
-
-//! \brief HID protocol
-enum usb_hid_protocol {
- USB_HID_PROCOTOL_BOOT = 0,
- USB_HID_PROCOTOL_REPORT = 1,
-};
-
-COMPILER_PACK_SET(1)
-
-//! \brief HID Descriptor
-typedef struct {
- uint8_t bLength; //!< Size of this descriptor in bytes
- uint8_t bDescriptorType; //!< HID descriptor type
- le16_t bcdHID; //!< Binary Coded Decimal Spec. release
- uint8_t bCountryCode; //!< Hardware target country
- uint8_t bNumDescriptors; //!< Number of HID class descriptors to follow
- uint8_t bRDescriptorType; //!< Report descriptor type
- le16_t wDescriptorLength; //!< Total length of Report descriptor
-} usb_hid_descriptor_t;
-
-COMPILER_PACK_RESET()
-
-//! \name HID Report type
-//! Used by SETUP_HID_GET_REPORT & SETUP_HID_SET_REPORT
-//! @{
-#define REPORT_TYPE_INPUT 0x01
-#define REPORT_TYPE_OUTPUT 0x02
-#define REPORT_TYPE_FEATURE 0x03
-//! @}
-
-//! \name Constants of field DESCRIPTOR_HID
-//! @{
-//! Numeric expression identifying the HID Class
-//! Specification release (here V1.11)
-#define USB_HID_BDC_V1_11 0x0111
-//! Numeric expression specifying the number of class descriptors
-//! Note: Always at least one i.e. Report descriptor.
-#define USB_HID_NUM_DESC 0x01
-
-//! \name Country code
-//! @{
-#define USB_HID_NO_COUNTRY_CODE 0 // Not Supported
-#define USB_HID_COUNTRY_ARABIC 1 // Arabic
-#define USB_HID_COUNTRY_BELGIAN 2 // Belgian
-#define USB_HID_COUNTRY_CANADIAN_BILINGUAL 3 // Canadian-Bilingual
-#define USB_HID_COUNTRY_CANADIAN_FRENCH 4 // Canadian-French
-#define USB_HID_COUNTRY_CZECH_REPUBLIC 5 // Czech Republic
-#define USB_HID_COUNTRY_DANISH 6 // Danish
-#define USB_HID_COUNTRY_FINNISH 7 // Finnish
-#define USB_HID_COUNTRY_FRENCH 8 // French
-#define USB_HID_COUNTRY_GERMAN 9 // German
-#define USB_HID_COUNTRY_GREEK 10 // Greek
-#define USB_HID_COUNTRY_HEBREW 11 // Hebrew
-#define USB_HID_COUNTRY_HUNGARY 12 // Hungary
-#define USB_HID_COUNTRY_INTERNATIONAL_ISO 13 // International (ISO)
-#define USB_HID_COUNTRY_ITALIAN 14 // Italian
-#define USB_HID_COUNTRY_JAPAN_KATAKANA 15 // Japan (Katakana)
-#define USB_HID_COUNTRY_KOREAN 16 // Korean
-#define USB_HID_COUNTRY_LATIN_AMERICAN 17 // Latin American
-#define USB_HID_COUNTRY_NETHERLANDS_DUTCH 18 // Netherlands/Dutch
-#define USB_HID_COUNTRY_NORWEGIAN 19 // Norwegian
-#define USB_HID_COUNTRY_PERSIAN_FARSI 20 // Persian (Farsi)
-#define USB_HID_COUNTRY_POLAND 21 // Poland
-#define USB_HID_COUNTRY_PORTUGUESE 22 // Portuguese
-#define USB_HID_COUNTRY_RUSSIA 23 // Russia
-#define USB_HID_COUNTRY_SLOVAKIA 24 // Slovakia
-#define USB_HID_COUNTRY_SPANISH 25 // Spanish
-#define USB_HID_COUNTRY_SWEDISH 26 // Swedish
-#define USB_HID_COUNTRY_SWISS_FRENCH 27 // Swiss/French
-#define USB_HID_COUNTRY_SWISS_GERMAN 28 // Swiss/German
-#define USB_HID_COUNTRY_SWITZERLAND 29 // Switzerland
-#define USB_HID_COUNTRY_TAIWAN 30 // Taiwan
-#define USB_HID_COUNTRY_TURKISH_Q 31 // Turkish-Q
-#define USB_HID_COUNTRY_UK 32 // UK
-#define USB_HID_COUNTRY_US 33 // US
-#define USB_HID_COUNTRY_YUGOSLAVIA 34 // Yugoslavia
-#define USB_HID_COUNTRY_TURKISH_F \
- 35 // Turkish-F
- //! @}
- //! @}
-//! @}
-
-//! \name HID KEYS values
-//! @{
-#define HID_A 0x04
-#define HID_B 0x05
-#define HID_C 0x06
-#define HID_D 0x07
-#define HID_E 0x08
-#define HID_F 0x09
-#define HID_G 0x0A
-#define HID_H 0x0B
-#define HID_I 0x0C
-#define HID_J 0x0D
-#define HID_K 0x0E
-#define HID_L 0x0F
-#define HID_M 0x10
-#define HID_N 0x11
-#define HID_O 0x12
-#define HID_P 0x13
-#define HID_Q 0x14
-#define HID_R 0x15
-#define HID_S 0x16
-#define HID_T 0x17
-#define HID_U 0x18
-#define HID_V 0x19
-#define HID_W 0x1A
-#define HID_X 0x1B
-#define HID_Y 0x1C
-#define HID_Z 0x1D
-#define HID_1 30
-#define HID_2 31
-#define HID_3 32
-#define HID_4 33
-#define HID_5 34
-#define HID_6 35
-#define HID_7 36
-#define HID_8 37
-#define HID_9 38
-#define HID_0 39
-#define HID_ENTER 40
-#define HID_ESCAPE 41
-#define HID_BACKSPACE 42
-#define HID_TAB 43
-#define HID_SPACEBAR 44
-#define HID_UNDERSCORE 45
-#define HID_PLUS 46
-#define HID_OPEN_BRACKET 47 // {
-#define HID_CLOSE_BRACKET 48 // }
-#define HID_BACKSLASH 49
-#define HID_ASH 50 // # ~
-#define HID_COLON 51 // ; :
-#define HID_QUOTE 52 // ' "
-#define HID_TILDE 53
-#define HID_COMMA 54
-#define HID_DOT 55
-#define HID_SLASH 56
-#define HID_CAPS_LOCK 57
-#define HID_F1 58
-#define HID_F2 59
-#define HID_F3 60
-#define HID_F4 61
-#define HID_F5 62
-#define HID_F6 63
-#define HID_F7 64
-#define HID_F8 65
-#define HID_F9 66
-#define HID_F10 67
-#define HID_F11 68
-#define HID_F12 69
-#define HID_PRINTSCREEN 70
-#define HID_SCROLL_LOCK 71
-#define HID_PAUSE 72
-#define HID_INSERT 73
-#define HID_HOME 74
-#define HID_PAGEUP 75
-#define HID_DELETE 76
-#define HID_END 77
-#define HID_PAGEDOWN 78
-#define HID_RIGHT 79
-#define HID_LEFT 80
-#define HID_DOWN 81
-#define HID_UP 82
-#define HID_KEYPAD_NUM_LOCK 83
-#define HID_KEYPAD_DIVIDE 84
-#define HID_KEYPAD_AT 85
-#define HID_KEYPAD_MULTIPLY 85
-#define HID_KEYPAD_MINUS 86
-#define HID_KEYPAD_PLUS 87
-#define HID_KEYPAD_ENTER 88
-#define HID_KEYPAD_1 89
-#define HID_KEYPAD_2 90
-#define HID_KEYPAD_3 91
-#define HID_KEYPAD_4 92
-#define HID_KEYPAD_5 93
-#define HID_KEYPAD_6 94
-#define HID_KEYPAD_7 95
-#define HID_KEYPAD_8 96
-#define HID_KEYPAD_9 97
-#define HID_KEYPAD_0 98
-
-//! \name HID modifier values
-//! @{
-#define HID_MODIFIER_NONE 0x00
-#define HID_MODIFIER_LEFT_CTRL 0x01
-#define HID_MODIFIER_LEFT_SHIFT 0x02
-#define HID_MODIFIER_LEFT_ALT 0x04
-#define HID_MODIFIER_LEFT_UI 0x08
-#define HID_MODIFIER_RIGHT_CTRL 0x10
-#define HID_MODIFIER_RIGHT_SHIFT 0x20
-#define HID_MODIFIER_RIGHT_ALT 0x40
-#define HID_MODIFIER_RIGHT_UI 0x80
-//! @}
-//! @}
-
-//! \name HID KEYS values
-//! @{
-#define HID_LED_NUM_LOCK (1 << 0)
-#define HID_LED_CAPS_LOCK (1 << 1)
-#define HID_LED_SCROLL_LOCK (1 << 2)
-#define HID_LED_COMPOSE (1 << 3)
-#define HID_LED_KANA (1 << 4)
-//! @}
-
-#endif // _USB_PROTOCOL_HID_H_
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_util.c b/tmk_core/protocol/arm_atsam/usb/usb_util.c
deleted file mode 100644
index c7555c84c671..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_util.c
+++ /dev/null
@@ -1,49 +0,0 @@
-#include "samd51j18a.h"
-#include "string.h"
-#include "usb_util.h"
-
-char digit(int d, int radix) {
- if (d < 10) {
- return d + '0';
- } else {
- return d - 10 + 'A';
- }
-}
-
-int UTIL_ltoa_radix(int64_t value, char *dest, int radix) {
- int64_t original = value; // save original value
- char buf[25] = "";
- int c = sizeof(buf) - 1;
- int last = c;
- int d;
- int size;
-
- if (value < 0) // if it's negative, take the absolute value
- value = -value;
-
- do // write least significant digit of value that's left
- {
- d = (value % radix);
- buf[--c] = digit(d, radix);
- value /= radix;
- } while (value);
-
- if (original < 0) buf[--c] = '-';
-
- size = last - c + 1; // includes null at end
- memcpy(dest, &buf[c], last - c + 1);
-
- return (size - 1); // without null termination
-}
-
-int UTIL_ltoa(int64_t value, char *dest) {
- return UTIL_ltoa_radix(value, dest, 10);
-}
-
-int UTIL_itoa(int value, char *dest) {
- return UTIL_ltoa_radix((int64_t)value, dest, 10);
-}
-
-int UTIL_utoa(uint32_t value, char *dest) {
- return UTIL_ltoa_radix((int64_t)value, dest, 10);
-}
diff --git a/tmk_core/protocol/arm_atsam/usb/usb_util.h b/tmk_core/protocol/arm_atsam/usb/usb_util.h
deleted file mode 100644
index 3e5b4fbb3245..000000000000
--- a/tmk_core/protocol/arm_atsam/usb/usb_util.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _USB_UTIL_H_
-#define _USB_UTIL_H_
-
-int UTIL_ltoa_radix(int64_t value, char *dest, int radix);
-int UTIL_ltoa(int64_t value, char *dest);
-int UTIL_itoa(int value, char *dest);
-int UTIL_utoa(uint32_t value, char *dest);
-
-#endif //_USB_UTIL_H_
diff --git a/tmk_core/protocol/arm_atsam/wait_api.h b/tmk_core/protocol/arm_atsam/wait_api.h
deleted file mode 100644
index b3918e534632..000000000000
--- a/tmk_core/protocol/arm_atsam/wait_api.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _wait_api_h_
-#define _wait_api_h_
-
-void wait_ms(uint64_t msec);
-void wait_us(uint16_t usec);
-
-#endif
diff --git a/tmk_core/protocol/chibios/chibios.c b/tmk_core/protocol/chibios/chibios.c
index b879bdac7787..cf948154f9bf 100644
--- a/tmk_core/protocol/chibios/chibios.c
+++ b/tmk_core/protocol/chibios/chibios.c
@@ -62,14 +62,13 @@
*/
/* declarations */
-uint8_t keyboard_leds(void);
-void send_keyboard(report_keyboard_t *report);
-void send_nkro(report_nkro_t *report);
-void send_mouse(report_mouse_t *report);
-void send_extra(report_extra_t *report);
+void send_keyboard(report_keyboard_t *report);
+void send_nkro(report_nkro_t *report);
+void send_mouse(report_mouse_t *report);
+void send_extra(report_extra_t *report);
/* host struct */
-host_driver_t chibios_driver = {keyboard_leds, send_keyboard, send_nkro, send_mouse, send_extra};
+host_driver_t chibios_driver = {.keyboard_leds = usb_device_state_get_leds, .send_keyboard = send_keyboard, .send_nkro = send_nkro, .send_mouse = send_mouse, .send_extra = send_extra};
#ifdef VIRTSER_ENABLE
void virtser_task(void);
diff --git a/tmk_core/protocol/chibios/usb_main.c b/tmk_core/protocol/chibios/usb_main.c
index 2024a3bc7f24..2a287e0d9890 100644
--- a/tmk_core/protocol/chibios/usb_main.c
+++ b/tmk_core/protocol/chibios/usb_main.c
@@ -54,10 +54,6 @@ extern keymap_config_t keymap_config;
extern usb_endpoint_in_t usb_endpoints_in[USB_ENDPOINT_IN_COUNT];
extern usb_endpoint_out_t usb_endpoints_out[USB_ENDPOINT_OUT_COUNT];
-uint8_t _Alignas(2) keyboard_idle = 0;
-uint8_t _Alignas(2) keyboard_protocol = 1;
-uint8_t keyboard_led_state = 0;
-
static bool __attribute__((__unused__)) send_report_buffered(usb_endpoint_in_lut_t endpoint, void *report, size_t size);
static void __attribute__((__unused__)) flush_report_buffered(usb_endpoint_in_lut_t endpoint, bool padded);
static bool __attribute__((__unused__)) receive_report(usb_endpoint_out_lut_t endpoint, void *report, size_t size);
@@ -168,6 +164,7 @@ void usb_event_queue_task(void) {
break;
case USB_EVENT_RESET:
usb_device_state_set_reset();
+ usb_device_state_set_protocol(USB_PROTOCOL_REPORT);
break;
default:
// Nothing to do, we don't handle it.
@@ -250,10 +247,10 @@ static void set_led_transfer_cb(USBDriver *usbp) {
if (setup->wLength == 2) {
uint8_t report_id = set_report_buf[0];
if ((report_id == REPORT_ID_KEYBOARD) || (report_id == REPORT_ID_NKRO)) {
- keyboard_led_state = set_report_buf[1];
+ usb_device_state_set_leds(set_report_buf[1]);
}
} else {
- keyboard_led_state = set_report_buf[0];
+ usb_device_state_set_leds(set_report_buf[0]);
}
}
@@ -269,7 +266,9 @@ static bool usb_requests_hook_cb(USBDriver *usbp) {
return usb_get_report_cb(usbp);
case HID_REQ_GetProtocol:
if (setup->wIndex == KEYBOARD_INTERFACE) {
- usbSetupTransfer(usbp, &keyboard_protocol, sizeof(uint8_t), NULL);
+ static uint8_t keyboard_protocol;
+ keyboard_protocol = usb_device_state_get_protocol();
+ usbSetupTransfer(usbp, &keyboard_protocol, sizeof(keyboard_protocol), NULL);
return true;
}
break;
@@ -292,12 +291,12 @@ static bool usb_requests_hook_cb(USBDriver *usbp) {
break;
case HID_REQ_SetProtocol:
if (setup->wIndex == KEYBOARD_INTERFACE) {
- keyboard_protocol = setup->wValue.word;
+ usb_device_state_set_protocol(setup->wValue.lbyte);
}
usbSetupTransfer(usbp, NULL, 0, NULL);
return true;
case HID_REQ_SetIdle:
- keyboard_idle = setup->wValue.hbyte;
+ usb_device_state_set_idle_rate(setup->wValue.hbyte);
return usb_set_idle_cb(usbp);
}
break;
@@ -396,11 +395,6 @@ __attribute__((weak)) void restart_usb_driver(USBDriver *usbp) {
* ---------------------------------------------------------
*/
-/* LED status */
-uint8_t keyboard_leds(void) {
- return keyboard_led_state;
-}
-
/**
* @brief Send a report to the host, the report is enqueued into an output
* queue and send once the USB endpoint becomes empty.
@@ -458,7 +452,7 @@ static bool receive_report(usb_endpoint_out_lut_t endpoint, void *report, size_t
void send_keyboard(report_keyboard_t *report) {
/* If we're in Boot Protocol, don't send any report ID or other funky fields */
- if (!keyboard_protocol) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_BOOT) {
send_report(USB_ENDPOINT_IN_KEYBOARD, &report->mods, 8);
} else {
send_report(USB_ENDPOINT_IN_KEYBOARD, report, KEYBOARD_REPORT_SIZE);
diff --git a/tmk_core/protocol/host.c b/tmk_core/protocol/host.c
index 732fbdc37d4d..df805c827c2a 100644
--- a/tmk_core/protocol/host.c
+++ b/tmk_core/protocol/host.c
@@ -193,6 +193,10 @@ void host_joystick_send(joystick_t *joystick) {
},
# endif
+# ifdef JOYSTICK_HAS_HAT
+ .hat = joystick->hat,
+# endif
+
# if JOYSTICK_BUTTON_COUNT > 0
.buttons =
{
diff --git a/tmk_core/protocol/host.h b/tmk_core/protocol/host.h
index 959753ae0255..d824fca077b3 100644
--- a/tmk_core/protocol/host.h
+++ b/tmk_core/protocol/host.h
@@ -27,9 +27,6 @@ along with this program. If not, see .
extern "C" {
#endif
-extern uint8_t keyboard_idle;
-extern uint8_t keyboard_protocol;
-
/* host driver */
void host_set_driver(host_driver_t *driver);
host_driver_t *host_get_driver(void);
diff --git a/tmk_core/protocol/lufa/lufa.c b/tmk_core/protocol/lufa/lufa.c
index b0c9758d2fd5..81da035f0c03 100644
--- a/tmk_core/protocol/lufa/lufa.c
+++ b/tmk_core/protocol/lufa/lufa.c
@@ -72,20 +72,14 @@
# define USB_WAIT_FOR_ENUMERATION
#endif
-uint8_t keyboard_idle = 0;
-/* 0: Boot Protocol, 1: Report Protocol(default) */
-uint8_t keyboard_protocol = 1;
-static uint8_t keyboard_led_state = 0;
-
static report_keyboard_t keyboard_report_sent;
/* Host driver */
-static uint8_t keyboard_leds(void);
-static void send_keyboard(report_keyboard_t *report);
-static void send_nkro(report_nkro_t *report);
-static void send_mouse(report_mouse_t *report);
-static void send_extra(report_extra_t *report);
-host_driver_t lufa_driver = {keyboard_leds, send_keyboard, send_nkro, send_mouse, send_extra};
+static void send_keyboard(report_keyboard_t *report);
+static void send_nkro(report_nkro_t *report);
+static void send_mouse(report_mouse_t *report);
+static void send_extra(report_extra_t *report);
+host_driver_t lufa_driver = {.keyboard_leds = usb_device_state_get_leds, .send_keyboard = send_keyboard, .send_nkro = send_nkro, .send_mouse = send_mouse, .send_extra = send_extra};
void send_report(uint8_t endpoint, void *report, size_t size) {
uint8_t timeout = 255;
@@ -271,6 +265,7 @@ void EVENT_USB_Device_Disconnect(void) {
void EVENT_USB_Device_Reset(void) {
print("[R]");
usb_device_state_set_reset();
+ usb_device_state_set_protocol(USB_PROTOCOL_REPORT);
}
/** \brief Event USB Device Connect
@@ -453,10 +448,10 @@ void EVENT_USB_Device_ControlRequest(void) {
uint8_t report_id = Endpoint_Read_8();
if (report_id == REPORT_ID_KEYBOARD || report_id == REPORT_ID_NKRO) {
- keyboard_led_state = Endpoint_Read_8();
+ usb_device_state_set_leds(Endpoint_Read_8());
}
} else {
- keyboard_led_state = Endpoint_Read_8();
+ usb_device_state_set_leds(Endpoint_Read_8());
}
Endpoint_ClearOUT();
@@ -473,7 +468,7 @@ void EVENT_USB_Device_ControlRequest(void) {
Endpoint_ClearSETUP();
while (!(Endpoint_IsINReady()))
;
- Endpoint_Write_8(keyboard_protocol);
+ Endpoint_Write_8(usb_device_state_get_protocol());
Endpoint_ClearIN();
Endpoint_ClearStatusStage();
}
@@ -486,7 +481,7 @@ void EVENT_USB_Device_ControlRequest(void) {
Endpoint_ClearSETUP();
Endpoint_ClearStatusStage();
- keyboard_protocol = (USB_ControlRequest.wValue & 0xFF);
+ usb_device_state_set_protocol(USB_ControlRequest.wValue & 0xFF);
clear_keyboard();
}
}
@@ -497,7 +492,7 @@ void EVENT_USB_Device_ControlRequest(void) {
Endpoint_ClearSETUP();
Endpoint_ClearStatusStage();
- keyboard_idle = ((USB_ControlRequest.wValue & 0xFF00) >> 8);
+ usb_device_state_set_idle_rate(USB_ControlRequest.wValue >> 8);
}
break;
@@ -506,7 +501,7 @@ void EVENT_USB_Device_ControlRequest(void) {
Endpoint_ClearSETUP();
while (!(Endpoint_IsINReady()))
;
- Endpoint_Write_8(keyboard_idle);
+ Endpoint_Write_8(usb_device_state_get_idle_rate());
Endpoint_ClearIN();
Endpoint_ClearStatusStage();
}
@@ -522,13 +517,6 @@ void EVENT_USB_Device_ControlRequest(void) {
/*******************************************************************************
* Host driver
******************************************************************************/
-/** \brief Keyboard LEDs
- *
- * FIXME: Needs doc
- */
-static uint8_t keyboard_leds(void) {
- return keyboard_led_state;
-}
/** \brief Send Keyboard
*
@@ -536,7 +524,7 @@ static uint8_t keyboard_leds(void) {
*/
static void send_keyboard(report_keyboard_t *report) {
/* If we're in Boot Protocol, don't send any report ID or other funky fields */
- if (!keyboard_protocol) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_BOOT) {
send_report(KEYBOARD_IN_EPNUM, &report->mods, 8);
} else {
send_report(KEYBOARD_IN_EPNUM, report, KEYBOARD_REPORT_SIZE);
diff --git a/tmk_core/protocol/report.c b/tmk_core/protocol/report.c
index 0166bf654f27..6203a3116bb7 100644
--- a/tmk_core/protocol/report.c
+++ b/tmk_core/protocol/report.c
@@ -19,19 +19,10 @@
#include "host.h"
#include "keycode_config.h"
#include "debug.h"
+#include "usb_device_state.h"
#include "util.h"
#include
-#ifdef RING_BUFFERED_6KRO_REPORT_ENABLE
-# define RO_ADD(a, b) ((a + b) % KEYBOARD_REPORT_KEYS)
-# define RO_SUB(a, b) ((a - b + KEYBOARD_REPORT_KEYS) % KEYBOARD_REPORT_KEYS)
-# define RO_INC(a) RO_ADD(a, 1)
-# define RO_DEC(a) RO_SUB(a, 1)
-static int8_t cb_head = 0;
-static int8_t cb_tail = 0;
-static int8_t cb_count = 0;
-#endif
-
/** \brief has_anykey
*
* FIXME: Needs doc
@@ -41,7 +32,7 @@ uint8_t has_anykey(void) {
uint8_t* p = keyboard_report->keys;
uint8_t lp = sizeof(keyboard_report->keys);
#ifdef NKRO_ENABLE
- if (keyboard_protocol && keymap_config.nkro) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_REPORT && keymap_config.nkro) {
p = nkro_report->bits;
lp = sizeof(nkro_report->bits);
}
@@ -58,25 +49,14 @@ uint8_t has_anykey(void) {
*/
uint8_t get_first_key(void) {
#ifdef NKRO_ENABLE
- if (keyboard_protocol && keymap_config.nkro) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_REPORT && keymap_config.nkro) {
uint8_t i = 0;
for (; i < NKRO_REPORT_BITS && !nkro_report->bits[i]; i++)
;
return i << 3 | biton(nkro_report->bits[i]);
}
#endif
-#ifdef RING_BUFFERED_6KRO_REPORT_ENABLE
- uint8_t i = cb_head;
- do {
- if (keyboard_report->keys[i] != 0) {
- break;
- }
- i = RO_INC(i);
- } while (i != cb_tail);
- return keyboard_report->keys[i];
-#else
return keyboard_report->keys[0];
-#endif
}
/** \brief Checks if a key is pressed in the report
@@ -89,7 +69,7 @@ bool is_key_pressed(uint8_t key) {
return false;
}
#ifdef NKRO_ENABLE
- if (keyboard_protocol && keymap_config.nkro) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_REPORT && keymap_config.nkro) {
if ((key >> 3) < NKRO_REPORT_BITS) {
return nkro_report->bits[key >> 3] & 1 << (key & 7);
} else {
@@ -110,50 +90,6 @@ bool is_key_pressed(uint8_t key) {
* FIXME: Needs doc
*/
void add_key_byte(report_keyboard_t* keyboard_report, uint8_t code) {
-#ifdef RING_BUFFERED_6KRO_REPORT_ENABLE
- int8_t i = cb_head;
- int8_t empty = -1;
- if (cb_count) {
- do {
- if (keyboard_report->keys[i] == code) {
- return;
- }
- if (empty == -1 && keyboard_report->keys[i] == 0) {
- empty = i;
- }
- i = RO_INC(i);
- } while (i != cb_tail);
- if (i == cb_tail) {
- if (cb_tail == cb_head) {
- // buffer is full
- if (empty == -1) {
- // pop head when has no empty space
- cb_head = RO_INC(cb_head);
- cb_count--;
- } else {
- // left shift when has empty space
- uint8_t offset = 1;
- i = RO_INC(empty);
- do {
- if (keyboard_report->keys[i] != 0) {
- keyboard_report->keys[empty] = keyboard_report->keys[i];
- keyboard_report->keys[i] = 0;
- empty = RO_INC(empty);
- } else {
- offset++;
- }
- i = RO_INC(i);
- } while (i != cb_tail);
- cb_tail = RO_SUB(cb_tail, offset);
- }
- }
- }
- }
- // add to tail
- keyboard_report->keys[cb_tail] = code;
- cb_tail = RO_INC(cb_tail);
- cb_count++;
-#else
int8_t i = 0;
int8_t empty = -1;
for (; i < KEYBOARD_REPORT_KEYS; i++) {
@@ -169,7 +105,6 @@ void add_key_byte(report_keyboard_t* keyboard_report, uint8_t code) {
keyboard_report->keys[empty] = code;
}
}
-#endif
}
/** \brief del key byte
@@ -177,38 +112,11 @@ void add_key_byte(report_keyboard_t* keyboard_report, uint8_t code) {
* FIXME: Needs doc
*/
void del_key_byte(report_keyboard_t* keyboard_report, uint8_t code) {
-#ifdef RING_BUFFERED_6KRO_REPORT_ENABLE
- uint8_t i = cb_head;
- if (cb_count) {
- do {
- if (keyboard_report->keys[i] == code) {
- keyboard_report->keys[i] = 0;
- cb_count--;
- if (cb_count == 0) {
- // reset head and tail
- cb_tail = cb_head = 0;
- }
- if (i == RO_DEC(cb_tail)) {
- // left shift when next to tail
- do {
- cb_tail = RO_DEC(cb_tail);
- if (keyboard_report->keys[RO_DEC(cb_tail)] != 0) {
- break;
- }
- } while (cb_tail != cb_head);
- }
- break;
- }
- i = RO_INC(i);
- } while (i != cb_tail);
- }
-#else
for (uint8_t i = 0; i < KEYBOARD_REPORT_KEYS; i++) {
if (keyboard_report->keys[i] == code) {
keyboard_report->keys[i] = 0;
}
}
-#endif
}
#ifdef NKRO_ENABLE
@@ -243,7 +151,7 @@ void del_key_bit(report_nkro_t* nkro_report, uint8_t code) {
*/
void add_key_to_report(uint8_t key) {
#ifdef NKRO_ENABLE
- if (keyboard_protocol && keymap_config.nkro) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_REPORT && keymap_config.nkro) {
add_key_bit(nkro_report, key);
return;
}
@@ -257,7 +165,7 @@ void add_key_to_report(uint8_t key) {
*/
void del_key_from_report(uint8_t key) {
#ifdef NKRO_ENABLE
- if (keyboard_protocol && keymap_config.nkro) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_REPORT && keymap_config.nkro) {
del_key_bit(nkro_report, key);
return;
}
@@ -272,7 +180,7 @@ void del_key_from_report(uint8_t key) {
void clear_keys_from_report(void) {
// not clear mods
#ifdef NKRO_ENABLE
- if (keyboard_protocol && keymap_config.nkro) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_REPORT && keymap_config.nkro) {
memset(nkro_report->bits, 0, sizeof(nkro_report->bits));
return;
}
diff --git a/tmk_core/protocol/report.h b/tmk_core/protocol/report.h
index 0e4f6e9defa5..d854f51d5c45 100644
--- a/tmk_core/protocol/report.h
+++ b/tmk_core/protocol/report.h
@@ -199,6 +199,12 @@ typedef int16_t mouse_xy_report_t;
typedef int8_t mouse_xy_report_t;
#endif
+#ifdef WHEEL_EXTENDED_REPORT
+typedef int16_t mouse_hv_report_t;
+#else
+typedef int8_t mouse_hv_report_t;
+#endif
+
typedef struct {
#ifdef MOUSE_SHARED_EP
uint8_t report_id;
@@ -210,8 +216,8 @@ typedef struct {
#endif
mouse_xy_report_t x;
mouse_xy_report_t y;
- int8_t v;
- int8_t h;
+ mouse_hv_report_t v;
+ mouse_hv_report_t h;
} PACKED report_mouse_t;
typedef struct {
@@ -240,6 +246,11 @@ typedef struct {
joystick_axis_t axes[JOYSTICK_AXIS_COUNT];
#endif
+#ifdef JOYSTICK_HAS_HAT
+ int8_t hat : 4;
+ uint8_t reserved : 4;
+#endif
+
#if JOYSTICK_BUTTON_COUNT > 0
uint8_t buttons[(JOYSTICK_BUTTON_COUNT - 1) / 8 + 1];
#endif
diff --git a/tmk_core/protocol/usb_descriptor.c b/tmk_core/protocol/usb_descriptor.c
index 703589b05471..c7fb660b65d6 100644
--- a/tmk_core/protocol/usb_descriptor.c
+++ b/tmk_core/protocol/usb_descriptor.c
@@ -49,6 +49,16 @@
# include "os_detection.h"
#endif
+#if defined(SERIAL_NUMBER) || (defined(SERIAL_NUMBER_USE_HARDWARE_ID) && SERIAL_NUMBER_USE_HARDWARE_ID == TRUE)
+
+# define HAS_SERIAL_NUMBER
+
+# if defined(SERIAL_NUMBER_USE_HARDWARE_ID) && SERIAL_NUMBER_USE_HARDWARE_ID == TRUE
+# include "hardware_id.h"
+# endif
+
+#endif // defined(SERIAL_NUMBER) || (defined(SERIAL_NUMBER_USE_HARDWARE_ID) && SERIAL_NUMBER_USE_HARDWARE_ID == TRUE)
+
// clang-format off
/*
@@ -155,20 +165,34 @@ const USB_Descriptor_HIDReport_Datatype_t PROGMEM SharedReport[] = {
# endif
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_RELATIVE),
- // Vertical wheel (1 byte)
- HID_RI_USAGE(8, 0x38), // Wheel
+ // Vertical wheel (1 or 2 bytes)
+ HID_RI_USAGE(8, 0x38), // Wheel
+# ifndef WHEEL_EXTENDED_REPORT
HID_RI_LOGICAL_MINIMUM(8, -127),
HID_RI_LOGICAL_MAXIMUM(8, 127),
HID_RI_REPORT_COUNT(8, 0x01),
HID_RI_REPORT_SIZE(8, 0x08),
+# else
+ HID_RI_LOGICAL_MINIMUM(16, -32767),
+ HID_RI_LOGICAL_MAXIMUM(16, 32767),
+ HID_RI_REPORT_COUNT(8, 0x01),
+ HID_RI_REPORT_SIZE(8, 0x10),
+# endif
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_RELATIVE),
- // Horizontal wheel (1 byte)
- HID_RI_USAGE_PAGE(8, 0x0C), // Consumer
- HID_RI_USAGE(16, 0x0238), // AC Pan
+ // Horizontal wheel (1 or 2 bytes)
+ HID_RI_USAGE_PAGE(8, 0x0C),// Consumer
+ HID_RI_USAGE(16, 0x0238), // AC Pan
+# ifndef WHEEL_EXTENDED_REPORT
HID_RI_LOGICAL_MINIMUM(8, -127),
HID_RI_LOGICAL_MAXIMUM(8, 127),
HID_RI_REPORT_COUNT(8, 0x01),
HID_RI_REPORT_SIZE(8, 0x08),
+# else
+ HID_RI_LOGICAL_MINIMUM(16, -32767),
+ HID_RI_LOGICAL_MAXIMUM(16, 32767),
+ HID_RI_REPORT_COUNT(8, 0x01),
+ HID_RI_REPORT_SIZE(8, 0x10),
+# endif
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_RELATIVE),
HID_RI_END_COLLECTION(0),
HID_RI_END_COLLECTION(0),
@@ -223,6 +247,23 @@ const USB_Descriptor_HIDReport_Datatype_t PROGMEM SharedReport[] = {
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE),
# endif
+# ifdef JOYSTICK_HAS_HAT
+ // Hat Switch (4 bits)
+ HID_RI_USAGE(8, 0x39), // Hat Switch
+ HID_RI_LOGICAL_MINIMUM(8, 0x00),
+ HID_RI_LOGICAL_MAXIMUM(8, 0x07),
+ HID_RI_PHYSICAL_MINIMUM(8, 0),
+ HID_RI_PHYSICAL_MAXIMUM(16, 315),
+ HID_RI_UNIT(8, 0x14), // Degree, English Rotation
+ HID_RI_REPORT_COUNT(8, 1),
+ HID_RI_REPORT_SIZE(8, 4),
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE | HID_IOF_NULLSTATE),
+ // Padding (4 bits)
+ HID_RI_REPORT_COUNT(8, 0x04),
+ HID_RI_REPORT_SIZE(8, 0x01),
+ HID_RI_INPUT(8, HID_IOF_CONSTANT),
+# endif
+
# if JOYSTICK_BUTTON_COUNT > 0
HID_RI_USAGE_PAGE(8, 0x09), // Button
HID_RI_USAGE_MINIMUM(8, 0x01),
@@ -451,11 +492,11 @@ const USB_Descriptor_Device_t PROGMEM DeviceDescriptor = {
.ReleaseNumber = DEVICE_VER,
.ManufacturerStrIndex = 0x01,
.ProductStrIndex = 0x02,
-#if defined(SERIAL_NUMBER)
+#ifdef HAS_SERIAL_NUMBER
.SerialNumStrIndex = 0x03,
-#else
+#else // HAS_SERIAL_NUMBER
.SerialNumStrIndex = 0x00,
-#endif
+#endif // HAS_SERIAL_NUMBER
.NumberOfConfigurations = FIXED_NUM_CONFIGURATIONS
};
@@ -1037,9 +1078,13 @@ const USB_Descriptor_Configuration_t PROGMEM ConfigurationDescriptor = {
/*
* String descriptors
*/
+
+#define USB_DESCRIPTOR_SIZE_LITERAL_U16STRING(str) \
+ (sizeof(USB_Descriptor_Header_t) + sizeof(str) - sizeof(wchar_t)) // include header, don't count null terminator
+
const USB_Descriptor_String_t PROGMEM LanguageString = {
.Header = {
- .Size = 4,
+ .Size = sizeof(USB_Descriptor_Header_t) + sizeof(uint16_t),
.Type = DTYPE_String
},
.UnicodeString = {LANGUAGE_ID_ENG}
@@ -1047,7 +1092,7 @@ const USB_Descriptor_String_t PROGMEM LanguageString = {
const USB_Descriptor_String_t PROGMEM ManufacturerString = {
.Header = {
- .Size = sizeof(USBSTR(MANUFACTURER)),
+ .Size = USB_DESCRIPTOR_SIZE_LITERAL_U16STRING(USBSTR(MANUFACTURER)),
.Type = DTYPE_String
},
.UnicodeString = USBSTR(MANUFACTURER)
@@ -1055,24 +1100,70 @@ const USB_Descriptor_String_t PROGMEM ManufacturerString = {
const USB_Descriptor_String_t PROGMEM ProductString = {
.Header = {
- .Size = sizeof(USBSTR(PRODUCT)),
+ .Size = USB_DESCRIPTOR_SIZE_LITERAL_U16STRING(USBSTR(PRODUCT)),
.Type = DTYPE_String
},
.UnicodeString = USBSTR(PRODUCT)
};
+// clang-format on
+
#if defined(SERIAL_NUMBER)
+// clang-format off
const USB_Descriptor_String_t PROGMEM SerialNumberString = {
.Header = {
- .Size = sizeof(USBSTR(SERIAL_NUMBER)),
+ .Size = USB_DESCRIPTOR_SIZE_LITERAL_U16STRING(USBSTR(SERIAL_NUMBER)),
.Type = DTYPE_String
},
.UnicodeString = USBSTR(SERIAL_NUMBER)
};
-#endif
-
// clang-format on
+#else // defined(SERIAL_NUMBER)
+
+# if defined(SERIAL_NUMBER_USE_HARDWARE_ID) && SERIAL_NUMBER_USE_HARDWARE_ID == TRUE
+
+# if defined(__AVR__)
+# error Dynamically setting the serial number on AVR is unsupported as LUFA requires the string to be in PROGMEM.
+# endif // defined(__AVR__)
+
+# ifndef SERIAL_NUMBER_LENGTH
+# define SERIAL_NUMBER_LENGTH (sizeof(hardware_id_t) * 2)
+# endif
+
+# define SERIAL_NUMBER_DESCRIPTOR_SIZE \
+ (sizeof(USB_Descriptor_Header_t) /* Descriptor header */ \
+ + (((SERIAL_NUMBER_LENGTH) + 1) * sizeof(wchar_t))) /* Length of serial number, with potential extra character as we're converting 2 nibbles at a time */
+
+uint8_t SerialNumberString[SERIAL_NUMBER_DESCRIPTOR_SIZE] = {0};
+
+void set_serial_number_descriptor(void) {
+ static bool is_set = false;
+ if (is_set) {
+ return;
+ }
+ is_set = true;
+
+ static const char hex_str[] = "0123456789ABCDEF";
+ hardware_id_t id = get_hardware_id();
+ USB_Descriptor_String_t* desc = (USB_Descriptor_String_t*)SerialNumberString;
+
+ // Copy across nibbles from the hardware ID as unicode hex characters
+ int length = MIN(sizeof(id) * 2, SERIAL_NUMBER_LENGTH);
+ uint8_t* p = (uint8_t*)&id;
+ for (int i = 0; i < length; i += 2) {
+ desc->UnicodeString[i + 0] = hex_str[p[i / 2] >> 4];
+ desc->UnicodeString[i + 1] = hex_str[p[i / 2] & 0xF];
+ }
+
+ desc->Header.Size = sizeof(USB_Descriptor_Header_t) + (length * sizeof(wchar_t)); // includes header, don't count null terminator
+ desc->Header.Type = DTYPE_String;
+}
+
+# endif // defined(SERIAL_NUMBER_USE_HARDWARE_ID) && SERIAL_NUMBER_USE_HARDWARE_ID == TRUE
+
+#endif // defined(SERIAL_NUMBER)
+
/**
* This function is called by the library when in device mode, and must be overridden (see library "USB Descriptors"
* documentation) by the application code so that the address and size of a requested descriptor can be given
@@ -1114,13 +1205,18 @@ uint16_t get_usb_descriptor(const uint16_t wValue, const uint16_t wIndex, const
Size = pgm_read_byte(&ProductString.Header.Size);
break;
-#if defined(SERIAL_NUMBER)
+#ifdef HAS_SERIAL_NUMBER
case 0x03:
- Address = &SerialNumberString;
- Size = pgm_read_byte(&SerialNumberString.Header.Size);
+ Address = (const USB_Descriptor_String_t*)&SerialNumberString;
+# if defined(SERIAL_NUMBER)
+ Size = pgm_read_byte(&SerialNumberString.Header.Size);
+# else
+ set_serial_number_descriptor();
+ Size = ((const USB_Descriptor_String_t*)SerialNumberString)->Header.Size;
+# endif
break;
-#endif
+#endif // HAS_SERIAL_NUMBER
}
#ifdef OS_DETECTION_ENABLE
process_wlength(wLength);
diff --git a/tmk_core/protocol/usb_descriptor.h b/tmk_core/protocol/usb_descriptor.h
index ecfb022702b4..1de8c5ec88a3 100644
--- a/tmk_core/protocol/usb_descriptor.h
+++ b/tmk_core/protocol/usb_descriptor.h
@@ -279,8 +279,6 @@ enum usb_endpoints {
# define MAX_ENDPOINTS USB_MAX_ENDPOINTS
#endif
-// TODO - ARM_ATSAM
-
#if (NEXT_EPNUM - 1) > MAX_ENDPOINTS
# error There are not enough available endpoints to support all functions. Please disable one or more of the following: Mouse Keys, Extra Keys, Console, NKRO, MIDI, Serial, Steno
#endif
diff --git a/tmk_core/protocol/usb_device_state.c b/tmk_core/protocol/usb_device_state.c
index 4cd241528d19..98ccfbc90273 100644
--- a/tmk_core/protocol/usb_device_state.c
+++ b/tmk_core/protocol/usb_device_state.c
@@ -24,15 +24,15 @@
# include "os_detection.h"
#endif
-enum usb_device_state usb_device_state = USB_DEVICE_STATE_NO_INIT;
+static struct usb_device_state usb_device_state = {.idle_rate = 0, .leds = 0, .protocol = USB_PROTOCOL_REPORT, .configure_state = USB_DEVICE_STATE_NO_INIT};
-__attribute__((weak)) void notify_usb_device_state_change_kb(enum usb_device_state usb_device_state) {
+__attribute__((weak)) void notify_usb_device_state_change_kb(struct usb_device_state usb_device_state) {
notify_usb_device_state_change_user(usb_device_state);
}
-__attribute__((weak)) void notify_usb_device_state_change_user(enum usb_device_state usb_device_state) {}
+__attribute__((weak)) void notify_usb_device_state_change_user(struct usb_device_state usb_device_state) {}
-static void notify_usb_device_state_change(enum usb_device_state usb_device_state) {
+static void notify_usb_device_state_change(struct usb_device_state usb_device_state) {
#if defined(HAPTIC_ENABLE) && HAPTIC_OFF_IN_LOW_POWER
haptic_notify_usb_device_state_change();
#endif
@@ -44,27 +44,58 @@ static void notify_usb_device_state_change(enum usb_device_state usb_device_stat
#endif
}
-void usb_device_state_set_configuration(bool isConfigured, uint8_t configurationNumber) {
- usb_device_state = isConfigured ? USB_DEVICE_STATE_CONFIGURED : USB_DEVICE_STATE_INIT;
+void usb_device_state_set_configuration(bool is_configured, uint8_t configuration_number) {
+ usb_device_state.configure_state = is_configured ? USB_DEVICE_STATE_CONFIGURED : USB_DEVICE_STATE_INIT;
notify_usb_device_state_change(usb_device_state);
}
-void usb_device_state_set_suspend(bool isConfigured, uint8_t configurationNumber) {
- usb_device_state = USB_DEVICE_STATE_SUSPEND;
+void usb_device_state_set_suspend(bool is_configured, uint8_t configuration_number) {
+ usb_device_state.configure_state = USB_DEVICE_STATE_SUSPEND;
notify_usb_device_state_change(usb_device_state);
}
-void usb_device_state_set_resume(bool isConfigured, uint8_t configurationNumber) {
- usb_device_state = isConfigured ? USB_DEVICE_STATE_CONFIGURED : USB_DEVICE_STATE_INIT;
+void usb_device_state_set_resume(bool is_configured, uint8_t configuration_number) {
+ usb_device_state.configure_state = is_configured ? USB_DEVICE_STATE_CONFIGURED : USB_DEVICE_STATE_INIT;
notify_usb_device_state_change(usb_device_state);
}
void usb_device_state_set_reset(void) {
- usb_device_state = USB_DEVICE_STATE_INIT;
+ usb_device_state.configure_state = USB_DEVICE_STATE_INIT;
notify_usb_device_state_change(usb_device_state);
}
void usb_device_state_init(void) {
- usb_device_state = USB_DEVICE_STATE_INIT;
+ usb_device_state.configure_state = USB_DEVICE_STATE_INIT;
notify_usb_device_state_change(usb_device_state);
}
+
+inline usb_configure_state_t usb_device_state_get_configure_state(void) {
+ return usb_device_state.configure_state;
+}
+
+void usb_device_state_set_protocol(usb_hid_protocol_t protocol) {
+ usb_device_state.protocol = protocol == USB_PROTOCOL_BOOT ? USB_PROTOCOL_BOOT : USB_PROTOCOL_REPORT;
+ notify_usb_device_state_change(usb_device_state);
+}
+
+inline usb_hid_protocol_t usb_device_state_get_protocol() {
+ return usb_device_state.protocol;
+}
+
+void usb_device_state_set_leds(uint8_t leds) {
+ usb_device_state.leds = leds;
+ notify_usb_device_state_change(usb_device_state);
+}
+
+inline uint8_t usb_device_state_get_leds(void) {
+ return usb_device_state.leds;
+}
+
+void usb_device_state_set_idle_rate(uint8_t idle_rate) {
+ usb_device_state.idle_rate = idle_rate;
+ notify_usb_device_state_change(usb_device_state);
+}
+
+inline uint8_t usb_device_state_get_idle_rate(void) {
+ return usb_device_state.idle_rate;
+}
diff --git a/tmk_core/protocol/usb_device_state.h b/tmk_core/protocol/usb_device_state.h
index 3be65ea7e15e..6d12f144fe3d 100644
--- a/tmk_core/protocol/usb_device_state.h
+++ b/tmk_core/protocol/usb_device_state.h
@@ -20,20 +20,41 @@
#include
#include
-void usb_device_state_set_configuration(bool isConfigured, uint8_t configurationNumber);
-void usb_device_state_set_suspend(bool isConfigured, uint8_t configurationNumber);
-void usb_device_state_set_resume(bool isConfigured, uint8_t configurationNumber);
-void usb_device_state_set_reset(void);
-void usb_device_state_init(void);
-
-enum usb_device_state {
+typedef enum {
USB_DEVICE_STATE_NO_INIT = 0, // We're in this state before calling usb_device_state_init()
USB_DEVICE_STATE_INIT = 1, // Can consume up to 100mA
USB_DEVICE_STATE_CONFIGURED = 2, // Can consume up to what is specified in configuration descriptor, typically 500mA
USB_DEVICE_STATE_SUSPEND = 3 // Can consume only suspend current
+} usb_configure_state_t;
+
+typedef enum {
+ USB_PROTOCOL_BOOT = 0,
+ USB_PROTOCOL_REPORT = 1,
+} usb_hid_protocol_t;
+
+// note: we can't typedef this struct to usb_device_state_t because it would
+// conflict with the previous definition in:
+// lib/chibios-contrib/ext/nxp-middleware-usb/device/usb_device.h
+struct usb_device_state {
+ uint8_t idle_rate;
+ uint8_t leds;
+ usb_hid_protocol_t protocol;
+ usb_configure_state_t configure_state;
};
-extern enum usb_device_state usb_device_state;
+void usb_device_state_set_configuration(bool is_configured, uint8_t configuration_number);
+void usb_device_state_set_suspend(bool is_configured, uint8_t configuration_number);
+void usb_device_state_set_resume(bool is_configured, uint8_t configuration_number);
+void usb_device_state_set_reset(void);
+void usb_device_state_init(void);
+usb_configure_state_t usb_device_state_get_configure_state(void);
+void usb_device_state_set_protocol(usb_hid_protocol_t protocol);
+usb_hid_protocol_t usb_device_state_get_protocol(void);
+void usb_device_state_set_leds(uint8_t leds);
+uint8_t usb_device_state_get_leds(void);
+void usb_device_state_set_idle_rate(uint8_t idle_rate);
+uint8_t usb_device_state_get_idle_rate(void);
+void usb_device_state_reset_hid_state(void);
-void notify_usb_device_state_change_kb(enum usb_device_state usb_device_state);
-void notify_usb_device_state_change_user(enum usb_device_state usb_device_state);
+void notify_usb_device_state_change_kb(struct usb_device_state usb_device_state);
+void notify_usb_device_state_change_user(struct usb_device_state usb_device_state);
diff --git a/tmk_core/protocol/vusb/vusb.c b/tmk_core/protocol/vusb/vusb.c
index fa14820e7254..fdbfcc17dce1 100644
--- a/tmk_core/protocol/vusb/vusb.c
+++ b/tmk_core/protocol/vusb/vusb.c
@@ -30,6 +30,7 @@ along with this program. If not, see .
#include "debug.h"
#include "wait.h"
#include "usb_descriptor_common.h"
+#include "usb_device_state.h"
#ifdef RAW_ENABLE
# include "raw_hid.h"
@@ -85,10 +86,6 @@ _Static_assert(TOTAL_INTERFACES <= MAX_INTERFACES, "There are not enough availab
# error Mouse/Extra Keys share an endpoint with Console. Please disable one of the two.
#endif
-static uint8_t keyboard_led_state = 0;
-uint8_t keyboard_idle = 0;
-uint8_t keyboard_protocol = 1;
-
static report_keyboard_t keyboard_report_sent;
static void send_report_fragment(uint8_t endpoint, void *data, size_t size) {
@@ -212,24 +209,19 @@ void console_task(void) {
/*------------------------------------------------------------------*
* Host driver
*------------------------------------------------------------------*/
-static uint8_t keyboard_leds(void);
-static void send_keyboard(report_keyboard_t *report);
-static void send_nkro(report_nkro_t *report);
-static void send_mouse(report_mouse_t *report);
-static void send_extra(report_extra_t *report);
+static void send_keyboard(report_keyboard_t *report);
+static void send_nkro(report_nkro_t *report);
+static void send_mouse(report_mouse_t *report);
+static void send_extra(report_extra_t *report);
-static host_driver_t driver = {keyboard_leds, send_keyboard, send_nkro, send_mouse, send_extra};
+static host_driver_t driver = {.keyboard_leds = usb_device_state_get_leds, .send_keyboard = send_keyboard, .send_nkro = send_nkro, .send_mouse = send_mouse, .send_extra = send_extra};
host_driver_t *vusb_driver(void) {
return &driver;
}
-static uint8_t keyboard_leds(void) {
- return keyboard_led_state;
-}
-
static void send_keyboard(report_keyboard_t *report) {
- if (!keyboard_protocol) {
+ if (usb_device_state_get_protocol() == USB_PROTOCOL_BOOT) {
send_report(1, &report->mods, 8);
} else {
send_report(1, report, sizeof(report_keyboard_t));
@@ -304,11 +296,15 @@ usbMsgLen_t usbFunctionSetup(uchar data[8]) {
break;
case USBRQ_HID_GET_IDLE:
dprint("GET_IDLE:");
- usbMsgPtr = (usbMsgPtr_t)&keyboard_idle;
+ static uint8_t keyboard_idle;
+ keyboard_idle = usb_device_state_get_idle_rate();
+ usbMsgPtr = (usbMsgPtr_t)&keyboard_idle;
return 1;
case USBRQ_HID_GET_PROTOCOL:
dprint("GET_PROTOCOL:");
- usbMsgPtr = (usbMsgPtr_t)&keyboard_protocol;
+ static uint8_t keyboard_protocol;
+ keyboard_protocol = usb_device_state_get_protocol();
+ usbMsgPtr = (usbMsgPtr_t)&keyboard_protocol;
return 1;
case USBRQ_HID_SET_REPORT:
dprint("SET_REPORT:");
@@ -320,13 +316,13 @@ usbMsgLen_t usbFunctionSetup(uchar data[8]) {
}
return USB_NO_MSG; // to get data in usbFunctionWrite
case USBRQ_HID_SET_IDLE:
- keyboard_idle = (rq->wValue.word & 0xFF00) >> 8;
- dprintf("SET_IDLE: %02X", keyboard_idle);
+ usb_device_state_set_idle_rate(rq->wValue.word >> 8);
+ dprintf("SET_IDLE: %02X", usb_device_state_get_idle_rate());
break;
case USBRQ_HID_SET_PROTOCOL:
if (rq->wIndex.word == KEYBOARD_INTERFACE) {
- keyboard_protocol = rq->wValue.word & 0xFF;
- dprintf("SET_PROTOCOL: %02X", keyboard_protocol);
+ usb_device_state_set_protocol(rq->wValue.word & 0xFF);
+ dprintf("SET_PROTOCOL: %02X", usb_device_state_get_protocol());
}
break;
default:
@@ -347,9 +343,9 @@ uchar usbFunctionWrite(uchar *data, uchar len) {
}
switch (last_req.kind) {
case SET_LED:
- dprintf("SET_LED: %02X\n", data[0]);
- keyboard_led_state = data[0];
- last_req.len = 0;
+ usb_device_state_set_leds(data[0]);
+ dprintf("SET_LED: %02X\n", usb_device_state_get_leds());
+ last_req.len = 0;
return 1;
break;
case NONE:
@@ -524,23 +520,37 @@ const PROGMEM uchar shared_hid_report[] = {
# endif
0x81, 0x06, // Input (Data, Variable, Relative)
- // Vertical wheel (1 byte)
+ // Vertical wheel (1 or 2 bytes)
0x09, 0x38, // Usage (Wheel)
+# ifndef WHEEL_EXTENDED_REPORT
0x15, 0x81, // Logical Minimum (-127)
0x25, 0x7F, // Logical Maximum (127)
0x95, 0x01, // Report Count (1)
0x75, 0x08, // Report Size (8)
+# else
+ 0x16, 0x01, 0x80, // Logical Minimum (-32767)
+ 0x26, 0xFF, 0x7F, // Logical Maximum (32767)
+ 0x95, 0x01, // Report Count (1)
+ 0x75, 0x10, // Report Size (16)
+# endif
0x81, 0x06, // Input (Data, Variable, Relative)
- // Horizontal wheel (1 byte)
+ // Horizontal wheel (1 or 2 bytes)
0x05, 0x0C, // Usage Page (Consumer)
0x0A, 0x38, 0x02, // Usage (AC Pan)
- 0x15, 0x81, // Logical Minimum (-127)
- 0x25, 0x7F, // Logical Maximum (127)
+# ifndef WHEEL_EXTENDED_REPORT
+ 0x15, 0x81, // Logical Minimum (-127)
+ 0x25, 0x7F, // Logical Maximum (127)
+ 0x95, 0x01, // Report Count (1)
+ 0x75, 0x08, // Report Size (8)
+# else
+ 0x16, 0x01, 0x80, // Logical Minimum (-32767)
+ 0x26, 0xFF, 0x7F, // Logical Maximum (32767)
0x95, 0x01, // Report Count (1)
- 0x75, 0x08, // Report Size (8)
- 0x81, 0x06, // Input (Data, Variable, Relative)
- 0xC0, // End Collection
- 0xC0, // End Collection
+ 0x75, 0x10, // Report Size (16)
+# endif
+ 0x81, 0x06, // Input (Data, Variable, Relative)
+ 0xC0, // End Collection
+ 0xC0, // End Collection
#endif
#ifdef EXTRAKEY_ENABLE
@@ -611,6 +621,23 @@ const PROGMEM uchar shared_hid_report[] = {
0x81, 0x02, // Input (Data, Variable, Absolute)
# endif
+# ifdef JOYSTICK_HAS_HAT
+ // Hat Switch (4 bits)
+ 0x09, 0x39, // Usage (Hat Switch)
+ 0x15, 0x00, // Logical Minimum (0)
+ 0x25, 0x07, // Logical Maximum (7)
+ 0x35, 0x00, // Physical Minimum (0)
+ 0x46, 0x3B, 0x01, // Physical Maximum (315)
+ 0x65, 0x14, // Unit (Degree, English Rotation)
+ 0x95, 0x01, // Report Count (1)
+ 0x75, 0x04, // Report Size (4)
+ 0x81, 0x42, // Input (Data, Variable, Absolute, Null State)
+ // Padding (4 bits)
+ 0x95, 0x04, // Report Count (4)
+ 0x75, 0x01, // Report Size (1)
+ 0x81, 0x01, // Input (Constant)
+# endif
+
# if JOYSTICK_BUTTON_COUNT > 0
0x05, 0x09, // Usage Page (Button)
0x19, 0x01, // Usage Minimum (Button 1)
diff --git a/util/polling_rate.py b/util/polling_rate.py
new file mode 100644
index 000000000000..fa3393787d4d
--- /dev/null
+++ b/util/polling_rate.py
@@ -0,0 +1,82 @@
+#!/usr/bin/env python3
+
+import usb
+
+USB_INTERFACE_CLASS_HID = 0x03
+
+def usb_device_spec(spec):
+ major = spec >> 8
+ minor = (spec >> 4) & 0xF
+ return f"{major}.{minor}"
+
+def usb_device_speed(speed):
+ if speed == 1:
+ return "Low-speed"
+ elif speed == 2:
+ return "Full-speed"
+ elif speed == 3:
+ return "High-speed"
+ elif speed == 4:
+ return "SuperSpeed"
+ elif speed == 5:
+ return "SuperSpeed+"
+
+ return "Speed unknown"
+
+def usb_hid_interface_subclass(subclass):
+ if subclass == 0x00:
+ return "None"
+ elif subclass == 0x01:
+ return "Boot"
+ else:
+ return f"Unknown (0x{subclass:02X})"
+
+def usb_hid_interface_protocol(subclass, protocol):
+ if subclass == 0x00 and protocol == 0x00:
+ return "None"
+ elif subclass == 0x01:
+ if protocol == 0x00:
+ return "None"
+ elif protocol == 0x01:
+ return "Keyboard"
+ elif protocol == 0x02:
+ return "Mouse"
+
+ return f"Unknown (0x{protocol:02X})"
+
+def usb_interface_polling_rate(speed, interval):
+ if speed >= 3:
+ return f"{interval * 125} μs ({8000 // interval} Hz)"
+ else:
+ return f"{interval} ms ({1000 // interval} Hz)"
+
+if __name__ == '__main__':
+ devices = usb.core.find(find_all=True)
+
+ for device in devices:
+ try:
+ configuration = device.get_active_configuration()
+ except NotImplementedError:
+ continue
+
+ hid_interfaces = []
+ for interface in configuration.interfaces():
+ if interface.bInterfaceClass == USB_INTERFACE_CLASS_HID:
+ hid_interfaces.append(interface)
+
+ if len(hid_interfaces) > 0:
+ print(f"{device.manufacturer} {device.product} ({device.idVendor:04X}:{device.idProduct:04X}:{device.bcdDevice:04X}), {usb_device_spec(device.bcdUSB)} {usb_device_speed(device.speed)}")
+
+ for interface in hid_interfaces:
+ print(f"└─ HID Interface {interface.bInterfaceNumber}")
+ subclass = interface.bInterfaceSubClass
+ protocol = interface.bInterfaceProtocol
+ print(f" ├─ Subclass: {usb_hid_interface_subclass(subclass)}")
+ print(f" ├─ Protocol: {usb_hid_interface_protocol(subclass, protocol)}")
+
+ for endpoint in interface.endpoints():
+ endpoint_address = endpoint.bEndpointAddress & 0xF
+ endpoint_direction = "IN" if endpoint.bEndpointAddress & 0x80 else "OUT"
+ print(f" └─ Endpoint {endpoint_address} {endpoint_direction}")
+ print(f" ├─ Endpoint Size: {endpoint.wMaxPacketSize} bytes")
+ print(f" └─ Polling Rate: {usb_interface_polling_rate(device.speed, endpoint.bInterval)}")
diff --git a/util/uf2families.json b/util/uf2families.json
index 778af4421fc6..e35bf8d4284d 100644
--- a/util/uf2families.json
+++ b/util/uf2families.json
@@ -174,11 +174,56 @@
"short_name": "ESP32H2",
"description": "ESP32-H2"
},
+ {
+ "id": "0x540ddf62",
+ "short_name": "ESP32C6",
+ "description": "ESP32-C6"
+ },
+ {
+ "id": "0x3d308e94",
+ "short_name": "ESP32P4",
+ "description": "ESP32-P4"
+ },
+ {
+ "id": "0xf71c0343",
+ "short_name": "ESP32C5",
+ "description": "ESP32-C5"
+ },
+ {
+ "id": "0x77d850c4",
+ "short_name": "ESP32C61",
+ "description": "ESP32-C61"
+ },
{
"id": "0xe48bff56",
"short_name": "RP2040",
"description": "Raspberry Pi RP2040"
},
+ {
+ "id": "0xe48bff57",
+ "short_name": "RP2XXX_ABSOLUTE",
+ "description": "Raspberry Pi Microcontrollers: Absolute (unpartitioned) download"
+ },
+ {
+ "id": "0xe48bff58",
+ "short_name": "RP2XXX_DATA",
+ "description": "Raspberry Pi Microcontrollers: Data partition download"
+ },
+ {
+ "id": "0xe48bff59",
+ "short_name": "RP2350_ARM_S",
+ "description": "Raspberry Pi RP2350, Secure Arm image"
+ },
+ {
+ "id": "0xe48bff5a",
+ "short_name": "RP2350_RISCV",
+ "description": "Raspberry Pi RP2350, RISC-V image"
+ },
+ {
+ "id": "0xe48bff5b",
+ "short_name": "RP2350_ARM_NS",
+ "description": "Raspberry Pi RP2350, Non-secure Arm image"
+ },
{
"id": "0x00ff6919",
"short_name": "STM32L4",
@@ -213,5 +258,40 @@
"id": "0x9517422f",
"short_name": "RZA1LU",
"description": "Renesas RZ/A1LU (R7S7210xx)"
+ },
+ {
+ "id": "0x2dc309c5",
+ "short_name": "STM32F411xE",
+ "description": "ST STM32F411xE"
+ },
+ {
+ "id": "0x06d1097b",
+ "short_name": "STM32F411xC",
+ "description": "ST STM32F411xC"
+ },
+ {
+ "id": "0x72721d4e",
+ "short_name": "NRF52832xxAA",
+ "description": "Nordic NRF52832xxAA"
+ },
+ {
+ "id": "0x6f752678",
+ "short_name": "NRF52832xxAB",
+ "description": "Nordic NRF52832xxAB"
+ },
+ {
+ "id": "0xa0c97b8e",
+ "short_name": "AT32F415",
+ "description": "ArteryTek AT32F415"
+ },
+ {
+ "id": "0x699b62ec",
+ "short_name": "CH32V",
+ "description": "WCH CH32V2xx and CH32V3xx"
+ },
+ {
+ "id": "0x7be8976d",
+ "short_name": "RA4M1",
+ "description": "Renesas RA4M1"
}
]