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ether4330.c
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ether4330.c
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/*
* Broadcom bcm4330 wifi (sdio interface)
*/
#ifndef __circle__
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/error.h"
#include "../port/netif.h"
#include "../port/sd.h"
#else
#include "p9compat.h"
#endif
extern int sdiocardintr(int);
#ifndef __circle__
#include "etherif.h"
#endif
#define CACHELINESZ 64 /* temp */
enum{
SDIODEBUG = 0,
SBDEBUG = 0,
EVENTDEBUG = 0,
VARDEBUG = 0,
FWDEBUG = 0,
Corescansz = 512,
Uploadsz = 2048,
Wifichan = 0, /* default channel */
Firmwarecmp = 1,
ARMcm3 = 0x82A,
ARM7tdmi = 0x825,
ARMcr4 = 0x83E,
Fn0 = 0,
Fn1 = 1,
Fn2 = 2,
Fbr1 = 0x100,
Fbr2 = 0x200,
/* CCCR */
Ioenable = 0x02,
Ioready = 0x03,
Intenable = 0x04,
Intpend = 0x05,
Ioabort = 0x06,
Busifc = 0x07,
Capability = 0x08,
Blksize = 0x10,
Highspeed = 0x13,
/* SDIOCommands */
GO_IDLE_STATE = 0,
SEND_RELATIVE_ADDR = 3,
IO_SEND_OP_COND = 5,
SELECT_CARD = 7,
VOLTAGE_SWITCH = 11,
IO_RW_DIRECT = 52,
IO_RW_EXTENDED = 53,
/* SELECT_CARD args */
Rcashift = 16,
/* SEND_OP_COND args */
Hcs = 1<<30, /* host supports SDHC & SDXC */
V3_3 = 3<<20, /* 3.2-3.4 volts */
V2_8 = 3<<15, /* 2.7-2.9 volts */
V2_0 = 1<<8, /* 2.0-2.1 volts */
S18R = 1<<24, /* switch to 1.8V request */
/* Sonics Silicon Backplane (access to cores on chip) */
Sbwsize = 0x8000,
Sb32bit = 0x8000,
Sbaddr = 0x1000a,
Enumbase = 0x18000000,
Framectl= 0x1000d,
Rfhalt = 0x01,
Wfhalt = 0x02,
Clkcsr = 0x1000e,
ForceALP = 0x01, /* active low-power clock */
ForceHT = 0x02, /* high throughput clock */
ForceILP = 0x04, /* idle low-power clock */
ReqALP = 0x08,
ReqHT = 0x10,
Nohwreq = 0x20,
ALPavail = 0x40,
HTavail = 0x80,
Pullups = 0x1000f,
Wfrmcnt = 0x10019,
Rfrmcnt = 0x1001b,
/* core control regs */
Ioctrl = 0x408,
Resetctrl = 0x800,
/* socram regs */
Coreinfo = 0x00,
Bankidx = 0x10,
Bankinfo = 0x40,
Bankpda = 0x44,
/* armcr4 regs */
Cr4Cap = 0x04,
Cr4Bankidx = 0x40,
Cr4Bankinfo = 0x44,
Cr4Cpuhalt = 0x20,
/* chipcommon regs */
Gpiopullup = 0x58,
Gpiopulldown = 0x5c,
Chipctladdr = 0x650,
Chipctldata = 0x654,
/* sdio core regs */
Intstatus = 0x20,
Fcstate = 1<<4,
Fcchange = 1<<5,
FrameInt = 1<<6,
MailboxInt = 1<<7,
Intmask = 0x24,
Sbmbox = 0x40,
Sbmboxdata = 0x48,
Hostmboxdata= 0x4c,
Fwready = 0x80,
/* wifi control commands */
GetVar = 262,
SetVar = 263,
/* status */
Disconnected= 0,
Connecting,
Connected,
};
typedef struct Ctlr Ctlr;
enum{
Wpa = 1,
Wep = 2,
Wpa2 = 3,
WNameLen = 32,
WNKeys = 4,
WKeyLen = 32,
WMinKeyLen = 5,
WMaxKeyLen = 13,
};
typedef struct WKey WKey;
struct WKey
{
ushort len;
char dat[WKeyLen];
};
struct Ctlr {
Ether* edev;
QLock cmdlock;
QLock pktlock;
QLock tlock;
QLock alock;
Lock txwinlock;
Rendez cmdr;
Rendez joinr;
int joinstatus;
int cryptotype;
int chanid;
uchar bssid[Eaddrlen];
char essid[WNameLen + 1];
WKey keys[WNKeys];
Block *rsp;
Block *scanb;
int scansecs;
int status;
int chipid;
int chiprev;
int armcore;
char *regufile;
union {
u32int i;
uchar c[4];
} resetvec;
ulong chipcommon;
ulong armctl;
ulong armregs;
ulong d11ctl;
ulong socramregs;
ulong socramctl;
ulong sdregs;
int sdiorev;
int socramrev;
ulong socramsize;
ulong rambase;
short reqid;
uchar fcmask;
uchar txwindow;
uchar txseq;
uchar rxseq;
ether_event_handler_t *evhndlr;
void *evcontext;
};
enum{
CMauth,
CMchannel,
CMcrypt,
CMessid,
CMkey1,
CMkey2,
CMkey3,
CMkey4,
CMrxkey,
CMrxkey0,
CMrxkey1,
CMrxkey2,
CMrxkey3,
CMtxkey,
CMdebug,
CMjoin,
CMdisassoc,
CMescan,
CMcountry,
CMcreate,
};
static Cmdtab cmds[] = {
{CMauth, "auth", 2},
{CMchannel, "channel", 2},
{CMcrypt, "crypt", 2},
{CMessid, "essid", 2},
{CMkey1, "key1", 2},
{CMkey2, "key2", 2},
{CMkey3, "key3", 2},
{CMkey4, "key4", 2},
{CMrxkey, "rxkey", 3},
{CMrxkey0, "rxkey0", 3},
{CMrxkey1, "rxkey1", 3},
{CMrxkey2, "rxkey2", 3},
{CMrxkey3, "rxkey3", 3},
{CMtxkey, "txkey", 3},
{CMdebug, "debug", 2},
{CMjoin, "join", 5},
{CMdisassoc, "disassoc", 2},
{CMescan, "escan", 2},
{CMcountry, "country", 2},
{CMcreate, "create", 4},
};
typedef struct Sdpcm Sdpcm;
typedef struct Cmd Cmd;
struct Sdpcm {
uchar len[2];
uchar lenck[2];
uchar seq;
uchar chanflg;
uchar nextlen;
uchar doffset;
uchar fcmask;
uchar window;
uchar version;
uchar pad;
};
struct Cmd {
uchar cmd[4];
uchar len[4];
uchar flags[2];
uchar id[2];
uchar status[4];
};
static char config40181[] = "bcmdhd.cal.40181";
static char config40183[] = "bcmdhd.cal.40183.26MHz";
static struct {
int chipid;
int chiprev;
char *fwfile;
char *cfgfile;
char *regufile;
} firmware[] = {
{ 0x4330, 3, "fw_bcm40183b1.bin", config40183, 0 },
{ 0x4330, 4, "fw_bcm40183b2.bin", config40183, 0 },
{ 43362, 0, "fw_bcm40181a0.bin", config40181, 0 },
{ 43362, 1, "fw_bcm40181a2.bin", config40181, 0 },
{ 43430, 1, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt", 0 },
{ 43430, 2, "brcmfmac43436-sdio.bin", "brcmfmac43436-sdio.txt", "brcmfmac43436-sdio.clm_blob" },
{ 0x4345, 6, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt", "brcmfmac43455-sdio.clm_blob" },
{ 0x4345, 9, "brcmfmac43456-sdio.bin", "brcmfmac43456-sdio.txt", "brcmfmac43456-sdio.clm_blob" },
};
static QLock sdiolock;
static int iodebug;
#ifndef __circle__
static void etherbcmintr(void *);
#endif
static void bcmevent(Ctlr*, uchar*, int);
static void wlscanresult(Ether*, uchar*, int);
static void wlsetvar(Ctlr*, char*, void*, int);
static void etherbcmscan(void *a, uint secs);
static void callevhndlr(Ctlr*, ether_event_type_t, const ether_event_params_t *);
static uchar*
put2(uchar *p, short v)
{
p[0] = v;
p[1] = v >> 8;
return p + 2;
}
static uchar*
put4(uchar *p, long v)
{
p[0] = v;
p[1] = v >> 8;
p[2] = v >> 16;
p[3] = v >> 24;
return p + 4;
}
#ifndef __circle__
static ushort
get2(uchar *p)
{
return p[0] | p[1]<<8;
}
#endif
static ulong
get4(uchar *p)
{
return p[0] | p[1]<<8 | p[2]<<16 | p[3]<<24;
}
static void
dump(char *s, void *a, int n)
{
#ifndef __circle__
int i;
uchar *p;
p = a;
print("%s:", s);
for(i = 0; i < n; i++)
print("%c%2.2x", i&15? ' ' : '\n', *p++);
print("\n");
#else
hexdump (a, n, s);
#endif
}
/*
* SDIO communication with dongle
*/
static ulong
sdiocmd_locked(int cmd, ulong arg)
{
u32int resp[4];
sdio.cmd(cmd, arg, resp);
return resp[0];
}
static ulong
sdiocmd(int cmd, ulong arg)
{
ulong r;
qlock(&sdiolock);
if(waserror()){
if(SDIODEBUG) print("sdiocmd error: cmd %d arg %lx\n", cmd, arg);
qunlock(&sdiolock);
nexterror();
}
r = sdiocmd_locked(cmd, arg);
qunlock(&sdiolock);
poperror();
return r;
}
static ulong
trysdiocmd(int cmd, ulong arg)
{
ulong r;
if(waserror())
return 0;
r = sdiocmd(cmd, arg);
poperror();
return r;
}
static int
sdiord(int fn, int addr)
{
int r;
r = sdiocmd(IO_RW_DIRECT, (0<<31)|((fn&7)<<28)|((addr&0x1FFFF)<<9));
if(r & 0xCF00){
print("ether4330: sdiord(%x, %x) fail: %2.2x %2.2x\n", fn, addr, (r>>8)&0xFF, r&0xFF);
error(Eio);
}
return r & 0xFF;
}
static void
sdiowr(int fn, int addr, int data)
{
int r;
int retry;
r = 0;
for(retry = 0; retry < 10; retry++){
r = sdiocmd(IO_RW_DIRECT, (1<<31)|((fn&7)<<28)|((addr&0x1FFFF)<<9)|(data&0xFF));
if((r & 0xCF00) == 0)
return;
}
print("ether4330: sdiowr(%x, %x, %x) fail: %2.2x %2.2x\n", fn, addr, data, (r>>8)&0xFF, r&0xFF);
error(Eio);
}
static void
sdiorwext(int fn, int write, void *a, int len, int addr, int incr)
{
int bsize, blk, bcount, m;
bsize = fn == Fn2? 512 : 64;
while(len > 0){
if(len >= 511*bsize){
blk = 1;
bcount = 511;
m = bcount*bsize;
}else if(len > bsize){
blk = 1;
bcount = len/bsize;
m = bcount*bsize;
}else{
blk = 0;
bcount = len;
m = bcount;
}
qlock(&sdiolock);
if(waserror()){
print("ether4330: sdiorwext fail: %s\n", up->errstr);
qunlock(&sdiolock);
nexterror();
}
if(blk)
sdio.iosetup(write, a, bsize, bcount);
else
sdio.iosetup(write, a, bcount, 1);
sdiocmd_locked(IO_RW_EXTENDED,
write<<31 | (fn&7)<<28 | blk<<27 | incr<<26 | (addr&0x1FFFF)<<9 | (bcount&0x1FF));
sdio.io(write, a, m);
qunlock(&sdiolock);
poperror();
len -= m;
a = (char*)a + m;
if(incr)
addr += m;
}
}
static void
sdioset(int fn, int addr, int bits)
{
sdiowr(fn, addr, sdiord(fn, addr) | bits);
}
static void
sdioinit(void)
{
ulong ocr, rca;
int i;
/* disconnect emmc from SD card (connect sdhost instead) */
for(i = 48; i <= 53; i++)
gpiosel(i, Alt0);
/* connect emmc to wifi */
for(i = 34; i <= 39; i++){
gpiosel(i, Alt3);
if(i == 34)
gpiopulloff(i);
else
gpiopullup(i);
}
sdio.init();
sdio.enable();
sdiocmd(GO_IDLE_STATE, 0);
ocr = trysdiocmd(IO_SEND_OP_COND, 0);
i = 0;
while((ocr & (1<<31)) == 0){
if(++i > 5){
print("ether4330: no response to sdio access: ocr = %lx\n", ocr);
error(Eio);
}
ocr = trysdiocmd(IO_SEND_OP_COND, V3_3);
tsleep(&up->sleep, return0, nil, 100);
}
rca = sdiocmd(SEND_RELATIVE_ADDR, 0) >> Rcashift;
sdiocmd(SELECT_CARD, rca << Rcashift);
sdioset(Fn0, Highspeed, 2);
sdioset(Fn0, Busifc, 2); /* bus width 4 */
sdiowr(Fn0, Fbr1+Blksize, 64);
sdiowr(Fn0, Fbr1+Blksize+1, 64>>8);
sdiowr(Fn0, Fbr2+Blksize, 512);
sdiowr(Fn0, Fbr2+Blksize+1, 512>>8);
sdioset(Fn0, Ioenable, 1<<Fn1);
sdiowr(Fn0, Intenable, 0);
for(i = 0; !(sdiord(Fn0, Ioready) & 1<<Fn1); i++){
if(i == 10){
print("ether4330: can't enable SDIO function\n");
error(Eio);
}
tsleep(&up->sleep, return0, nil, 100);
}
}
static void
sdioreset(void)
{
sdiowr(Fn0, Ioabort, 1<<3); /* reset */
}
static void
sdioabort(int fn)
{
sdiowr(Fn0, Ioabort, fn);
}
/*
* Chip register and memory access via SDIO
*/
static void
cfgw(ulong off, int val)
{
sdiowr(Fn1, off, val);
}
static int
cfgr(ulong off)
{
return sdiord(Fn1, off);
}
static ulong
cfgreadl(int fn, ulong off)
{
uchar cbuf[2*CACHELINESZ];
uchar *p;
p = (uchar*)ROUND((uintptr)cbuf, CACHELINESZ);
memset(p, 0, 4);
sdiorwext(fn, 0, p, 4, off|Sb32bit, 1);
if(SDIODEBUG) print("cfgreadl %lx: %2.2x %2.2x %2.2x %2.2x\n", off, p[0], p[1], p[2], p[3]);
return p[0] | p[1]<<8 | p[2]<<16 | p[3]<<24;
}
static void
cfgwritel(int fn, ulong off, u32int data)
{
uchar cbuf[2*CACHELINESZ];
uchar *p;
int retry;
p = (uchar*)ROUND((uintptr)cbuf, CACHELINESZ);
put4(p, data);
if(SDIODEBUG) print("cfgwritel %lx: %2.2x %2.2x %2.2x %2.2x\n", off, p[0], p[1], p[2], p[3]);
retry = 0;
while(waserror()){
print("ether4330: cfgwritel retry %lx %x\n", off, data);
sdioabort(fn);
if(++retry == 3)
nexterror();
}
sdiorwext(fn, 1, p, 4, off|Sb32bit, 1);
poperror();
}
static void
sbwindow(ulong addr)
{
addr &= ~(Sbwsize-1);
cfgw(Sbaddr, addr>>8);
cfgw(Sbaddr+1, addr>>16);
cfgw(Sbaddr+2, addr>>24);
}
static void
sbrw(int fn, int write, uchar *buf, int len, ulong off)
{
int n;
USED(fn);
if(waserror()){
print("ether4330: sbrw err off %lx len %d\n", off, len);
nexterror();
}
if(write){
if(len >= 4){
n = len;
n &= ~3;
sdiorwext(Fn1, write, buf, n, off|Sb32bit, 1);
off += n;
buf += n;
len -= n;
}
while(len > 0){
sdiowr(Fn1, off|Sb32bit, *buf);
off++;
buf++;
len--;
}
}else{
if(len >= 4){
n = len;
n &= ~3;
sdiorwext(Fn1, write, buf, n, off|Sb32bit, 1);
off += n;
buf += n;
len -= n;
}
while(len > 0){
*buf = sdiord(Fn1, off|Sb32bit);
off++;
buf++;
len--;
}
}
poperror();
}
static void
sbmem(int write, uchar *buf, int len, ulong off)
{
ulong n;
n = ROUNDUP(off, Sbwsize) - off;
if(n == 0)
n = Sbwsize;
while(len > 0){
if(n > len)
n = len;
sbwindow(off);
sbrw(Fn1, write, buf, n, off & (Sbwsize-1));
off += n;
buf += n;
len -= n;
n = Sbwsize;
}
}
static void
packetrw(int write, uchar *buf, int len)
{
int n;
int retry;
n = 2048;
while(len > 0){
if(n > len)
n = ROUND(len, 4);
retry = 0;
while(waserror()){
sdioabort(Fn2);
if(++retry == 3)
nexterror();
}
sdiorwext(Fn2, write, buf, n, Enumbase, 0);
poperror();
buf += n;
len -= n;
}
}
/*
* Configuration and control of chip cores via Silicon Backplane
*/
static void
sbdisable(ulong regs, int pre, int ioctl)
{
sbwindow(regs);
if((cfgreadl(Fn1, regs + Resetctrl) & 1) != 0){
cfgwritel(Fn1, regs + Ioctrl, 3|ioctl);
cfgreadl(Fn1, regs + Ioctrl);
return;
}
cfgwritel(Fn1, regs + Ioctrl, 3|pre);
cfgreadl(Fn1, regs + Ioctrl);
cfgwritel(Fn1, regs + Resetctrl, 1);
microdelay(10);
while((cfgreadl(Fn1, regs + Resetctrl) & 1) == 0)
;
cfgwritel(Fn1, regs + Ioctrl, 3|ioctl);
cfgreadl(Fn1, regs + Ioctrl);
}
static void
sbreset(ulong regs, int pre, int ioctl)
{
sbdisable(regs, pre, ioctl);
sbwindow(regs);
if(SBDEBUG) print("sbreset %#p %#lx %#lx ->", regs,
cfgreadl(Fn1, regs+Ioctrl), cfgreadl(Fn1, regs+Resetctrl));
while((cfgreadl(Fn1, regs + Resetctrl) & 1) != 0){
cfgwritel(Fn1, regs + Resetctrl, 0);
microdelay(40);
}
cfgwritel(Fn1, regs + Ioctrl, 1|ioctl);
cfgreadl(Fn1, regs + Ioctrl);
if(SBDEBUG) print("%#lx %#lx\n",
cfgreadl(Fn1, regs+Ioctrl), cfgreadl(Fn1, regs+Resetctrl));
}
static void
corescan(Ctlr *ctl, ulong r)
{
uchar *buf;
int i, coreid, corerev;
ulong addr;
buf = sdmalloc(Corescansz);
if(buf == nil)
error(Enomem);
sbmem(0, buf, Corescansz, r);
coreid = 0;
corerev = 0;
for(i = 0; i < Corescansz; i += 4){
switch(buf[i]&0xF){
case 0xF: /* end */
sdfree(buf);
return;
case 0x1: /* core info */
if((buf[i+4]&0xF) != 0x1)
break;
coreid = (buf[i+1] | buf[i+2]<<8) & 0xFFF;
i += 4;
corerev = buf[i+3];
break;
case 0x05: /* address */
addr = buf[i+1]<<8 | buf[i+2]<<16 | buf[i+3]<<24;
addr &= ~0xFFF;
if(SBDEBUG) print("core %x %s %#p\n", coreid, buf[i]&0xC0? "ctl" : "mem", addr);
switch(coreid){
case 0x800:
if((buf[i] & 0xC0) == 0)
ctl->chipcommon = addr;
break;
case ARMcm3:
case ARM7tdmi:
case ARMcr4:
ctl->armcore = coreid;
if(buf[i] & 0xC0){
if(ctl->armctl == 0)
ctl->armctl = addr;
}else{
if(ctl->armregs == 0)
ctl->armregs = addr;
}
break;
case 0x80E:
if(buf[i] & 0xC0)
ctl->socramctl = addr;
else if(ctl->socramregs == 0)
ctl->socramregs = addr;
ctl->socramrev = corerev;
break;
case 0x829:
if((buf[i] & 0xC0) == 0)
ctl->sdregs = addr;
ctl->sdiorev = corerev;
break;
case 0x812:
if(buf[i] & 0xC0)
ctl->d11ctl = addr;
break;
}
}
}
sdfree(buf);
}
static void
ramscan(Ctlr *ctl)
{
ulong r, n, size;
int banks, i;
if(ctl->armcore == ARMcr4){
r = ctl->armregs;
sbwindow(r);
n = cfgreadl(Fn1, r + Cr4Cap);
if(SBDEBUG) print("cr4 banks %lx\n", n);
banks = ((n>>4) & 0xF) + (n & 0xF);
size = 0;
for(i = 0; i < banks; i++){
cfgwritel(Fn1, r + Cr4Bankidx, i);
n = cfgreadl(Fn1, r + Cr4Bankinfo);
if(SBDEBUG) print("bank %d reg %lx size %ld\n", i, n, 8192 * ((n & 0x3F) + 1));
size += 8192 * ((n & 0x3F) + 1);
}
ctl->socramsize = size;
ctl->rambase = 0x198000;
return;
}
if(ctl->socramrev <= 7 || ctl->socramrev == 12){
print("ether4330: SOCRAM rev %d not supported\n", ctl->socramrev);
error(Eio);
}
sbreset(ctl->socramctl, 0, 0);
r = ctl->socramregs;
sbwindow(r);
n = cfgreadl(Fn1, r + Coreinfo);
if(SBDEBUG) print("socramrev %d coreinfo %lx\n", ctl->socramrev, n);
banks = (n>>4) & 0xF;
size = 0;
for(i = 0; i < banks; i++){
cfgwritel(Fn1, r + Bankidx, i);
n = cfgreadl(Fn1, r + Bankinfo);
if(SBDEBUG) print("bank %d reg %lx size %ld\n", i, n, 8192 * ((n & 0x3F) + 1));
size += 8192 * ((n & 0x3F) + 1);
}
ctl->socramsize = size;
ctl->rambase = 0;
if(ctl->chipid == 43430){
cfgwritel(Fn1, r + Bankidx, 3);
cfgwritel(Fn1, r + Bankpda, 0);
}
}
static void
sbinit(Ctlr *ctl)
{
ulong r;
int chipid;
char buf[16];
sbwindow(Enumbase);
r = cfgreadl(Fn1, Enumbase);
chipid = r & 0xFFFF;
sprint(buf, chipid > 43000 ? "%d" : "%#x", chipid);
print("ether4330: chip %s rev %ld type %ld\n", buf, (r>>16)&0xF, (r>>28)&0xF);
switch(chipid){
case 0x4330:
case 43362:
case 43430:
case 0x4345:
ctl->chipid = chipid;
ctl->chiprev = (r>>16)&0xF;
break;
default:
print("ether4330: chipid %#x (%d) not supported\n", chipid, chipid);
error(Eio);
}
r = cfgreadl(Fn1, Enumbase + 63*4);
corescan(ctl, r);
if(ctl->armctl == 0 || ctl->d11ctl == 0 ||
(ctl->armcore == ARMcm3 && (ctl->socramctl == 0 || ctl->socramregs == 0)))
error("corescan didn't find essential cores\n");
if(ctl->armcore == ARMcr4)
sbreset(ctl->armctl, Cr4Cpuhalt, Cr4Cpuhalt);
else
sbdisable(ctl->armctl, 0, 0);
sbreset(ctl->d11ctl, 8|4, 4);
ramscan(ctl);
if(SBDEBUG) print("ARM %#p D11 %#p SOCRAM %#p,%#p %ld bytes @ %#p\n",
ctl->armctl, ctl->d11ctl, ctl->socramctl, ctl->socramregs, ctl->socramsize, ctl->rambase);
cfgw(Clkcsr, 0);
microdelay(10);
if(SBDEBUG) print("chipclk: %x\n", cfgr(Clkcsr));
cfgw(Clkcsr, Nohwreq | ReqALP);
while((cfgr(Clkcsr) & (HTavail|ALPavail)) == 0)
microdelay(10);
cfgw(Clkcsr, Nohwreq | ForceALP);
microdelay(65);
if(SBDEBUG) print("chipclk: %x\n", cfgr(Clkcsr));
cfgw(Pullups, 0);
sbwindow(ctl->chipcommon);
cfgwritel(Fn1, ctl->chipcommon + Gpiopullup, 0);
cfgwritel(Fn1, ctl->chipcommon + Gpiopulldown, 0);
if(ctl->chipid != 0x4330 && ctl->chipid != 43362)
return;
cfgwritel(Fn1, ctl->chipcommon + Chipctladdr, 1);
if(cfgreadl(Fn1, ctl->chipcommon + Chipctladdr) != 1)
print("ether4330: can't set Chipctladdr\n");
else{
r = cfgreadl(Fn1, ctl->chipcommon + Chipctldata);
if(SBDEBUG) print("chipcommon PMU (%lx) %lx", cfgreadl(Fn1, ctl->chipcommon + Chipctladdr), r);
/* set SDIO drive strength >= 6mA */
r &= ~0x3800;
if(ctl->chipid == 0x4330)
r |= 3<<11;
else
r |= 7<<11;
cfgwritel(Fn1, ctl->chipcommon + Chipctldata, r);
if(SBDEBUG) print("-> %lx (= %lx)\n", r, cfgreadl(Fn1, ctl->chipcommon + Chipctldata));
}
}
static void
sbenable(Ctlr *ctl)
{
int i;
if(SBDEBUG) print("enabling HT clock...");
cfgw(Clkcsr, 0);
delay(1);
cfgw(Clkcsr, ReqHT);
for(i = 0; (cfgr(Clkcsr) & HTavail) == 0; i++){
if(i == 50){
print("ether4330: can't enable HT clock: csr %x\n", cfgr(Clkcsr));
error(Eio);
}
tsleep(&up->sleep, return0, nil, 100);
}
cfgw(Clkcsr, cfgr(Clkcsr) | ForceHT);
delay(10);
if(SBDEBUG) print("chipclk: %x\n", cfgr(Clkcsr));
sbwindow(ctl->sdregs);
cfgwritel(Fn1, ctl->sdregs + Sbmboxdata, 4 << 16); /* protocol version */
cfgwritel(Fn1, ctl->sdregs + Intmask, FrameInt | MailboxInt | Fcchange);
sdioset(Fn0, Ioenable, 1<<Fn2);
for(i = 0; !(sdiord(Fn0, Ioready) & 1<<Fn2); i++){
if(i == 10){
print("ether4330: can't enable SDIO function 2 - ioready %x\n", sdiord(Fn0, Ioready));
error(Eio);
}
tsleep(&up->sleep, return0, nil, 100);
}
sdiowr(Fn0, Intenable, (1<<Fn1) | (1<<Fn2) | 1);
}
/*
* Firmware and config file uploading
*/
/*
* Condense config file contents (in buffer buf with length n)
* to 'var=value\0' list for firmware:
* - remove comments (starting with '#') and blank lines
* - remove carriage returns
* - convert newlines to nulls
* - mark end with two nulls
* - pad with nulls to multiple of 4 bytes total length
*/
static int
condense(uchar *buf, int n)
{
uchar *p, *ep, *lp, *op;
int c, skipping;
skipping = 0; /* true if in a comment */
ep = buf + n; /* end of input */
op = buf; /* end of output */
lp = buf; /* start of current output line */
for(p = buf; p < ep; p++){
switch(c = *p){
case '#':
skipping = 1;
break;
case '\0':
case '\n':
skipping = 0;
if(op != lp){
*op++ = '\0';
lp = op;
}
break;
case '\r':
break;
default:
if(!skipping)
*op++ = c;
break;
}
}
if(!skipping && op != lp)
*op++ = '\0';
*op++ = '\0';
for(n = op - buf; n & 03; n++)
*op++ = '\0';
return n;
}
/*