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Pull requests: ucb-bar/chisel2-deprecated

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Pull requests list

C++ output from Chisel has been dropped
#738 opened Oct 30, 2016 by olofk Loading…
1
Invalid verilog generated with constant idx into ROM
#733 opened Sep 14, 2016 by da-steve101 Loading…
1
Allow specifying of clock for blackbox module
#731 opened Sep 12, 2016 by da-steve101 Loading…
2
fix the outputlist size
#717 opened Jul 6, 2016 by songmaotian Loading…
3
Added blocks for input, output, and input-output timing closure
#691 opened Apr 13, 2016 by hutch31 Loading…
8
Fixed AsyncFifo so reset not tied to 0
#690 opened Apr 11, 2016 by da-steve101 Loading…
4
Changed Vec cloneType
#669 opened Mar 6, 2016 by shunshou Loading…
11
Added getLit method to types for convenience when using a generating type
#572 opened Nov 3, 2015 by da-steve101 Loading…
1
Chisel SystemC update
#560 opened Oct 19, 2015 by capetry Loading…
3
Move emitRef from Verilog to backend
#487 opened Aug 10, 2015 by da-steve101 Loading…
5
Added support for successive <> operations overriding each other.
#190 opened Apr 17, 2014 by albert-magyar Loading…
2
Updated reflective finding of declared vals in Bundles.
#181 opened Apr 9, 2014 by albert-magyar Loading…
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