No .v(verilog) file generated after running Chipyard-Standalone Testing

[danielfufu]

I'm trying the Chipyard-Standalone Testing with the following command

cd chipyard/sims/vcs
make SUB_PROJECT=constellation BINARY=none CONFIG=TestConfig00 run-binary-debug

If I added run-binary-debug it would occur the above error.

Then I took it off and ran make SUB_PROJECT=constellation BINARY=none CONFIG=TestConfig00
it didn't generate the .v file and here is my log.

Running with RISCV=/home/peter997799/chipyard/.conda-env/riscv-tools
rm -rf /home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.test.Tes
vcs -full64 -CFLAGS " -O3 -std=c++17 -I/home/peter997799/chipyard/.conda-env/riscv-tools/include -I/home/daniel9856/chipyaniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral " -LDFLAGS "-L/home/pev/riscv-tools/lib -Wl,-rpath,/home/peter997799/chipyard/.conda-env/riscv-tools/lib -L/home/daniel9856/chipyard/sims/vcs -Lols/DRAMSim2" -lriscv -lfesvr -ldramsim -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -error=noZMMCM -timescales+lic+wait +vc+list -f /home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/sim_fiemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v -debug_pp +incdir+ms/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral +define+CLOCK_PERIOD=1.0 +define+RESET_DEL=TestDriver.printf_cond +define+STOP_COND=!TestDriver.reset +define+MODEL=TestHarness +define+RANDOMIZE_MEM_INIT +define+RNDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN +define+VCS +define+FSDB -o /home/daniel9856/chipyard/sims/vcs/sinfig00 -Mdir=/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/constellation.te

Warning-[DEBUG_DEP] Option will be deprecated
The option '-debug_pp' will be deprecated in a future release. Please use
'-debug_acc+pp+dmptf -debug_region+cell+encrypt' instead.

Warning-[DEBUG_DEP] Option will be deprecated
The option 'debug=4' will be deprecated in a future release. Please use
'-debug_acc+pp+f+fn+dmptf -debug_region+cell+encrypt' instead.

Lint-[SV-PIU] Package import statement in $unit scope.
/usr/cad/synopsys/vcs/2023.12/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 64-bit LHS target:
Source info: max_cycles = 0;
Expression: max_cycles

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 64-bit LHS target:
Source info: dump_start = 0;
Expression: dump_start

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 64-bit LHS target:
Source info: trace_count = 0;
Expression: trace_count

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 2048-bit LHS target:
Source info: fsdbfile = 0;
Expression: fsdbfile

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 2048-bit LHS target:
Source info: vcdplusfile = 0;
Expression: vcdplusfile

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 2048-bit LHS target:
Source info: vcdfile = 0;
Expression: vcdfile

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 8-bit wide expression is assigned to a 256-bit LHS target:
Source info: reason = "\000";
Expression: reason

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: reset = 0;
Expression: reset

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 32-bit wide expression is assigned to a 1-bit LHS target:
Source info: verbose = $test$plusargs("verbose");
Expression: verbose

Lint-[WMIA-L] Width mismatch in assignment
/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/gen-collateral/TestDriver.v,
Width mismatch between LHS and RHS is found in assignment:
The following 80-bit wide expression is assigned to a 256-bit LHS target:
Source info: reason = " (timeout)";
Expression: reason

Lint-[WMIA-L] Width mismatch in assignment
/usr/cad/synopsys/vcs/2023.12/etc/sva/rec_ltl_classes_package.svp, 2

Warning-[DRTZ] Detect delay value roundoff to 0
Delay from design or SDF file roundoff to 0 based on timescale
Please use switch -diag timescale to dump detailed information.

8 modules and 1 UDP read.
Generating code for _VCSgd_reYIK
Generating code for _VCSgd_g3tUK
Generating code for _VCSgd_kNaHg
Generating code for _VCSgd_ij5zV
Generating code for _VCSgd_LSQDD
Generating code for _VCSgd_YrSMD
Generating code for _VCSgd_TQLWP
Generating code for _VCSgd_jrwqy
Generating code for _VCSgd_qW2V4
Generating code for _VCSgd_KrGDi
make[1]: Entering directory '/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/ss.TestConfig00'
/home/peter997799/chipyard/.conda-env/bin/../lib/gcc/x86_64-conda-linux-gnu/11.4.0/../../../../x86_64-conda-linux-gnu/bin/ing .note.GNU-stack section implies executable stack
/home/peter997799/chipyard/.conda-env/bin/../lib/gcc/x86_64-conda-linux-gnu/11.4.0/../../../../x86_64-conda-linux-gnu/bin/deprecated and will be removed in a future version of the linker
make[1]: Leaving directory '/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/cs.TestConfig00'
make[1]: Entering directory '/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/ss.TestConfig00'
cc1: warning: command-line option '-std=c++17' is valid for C++/ObjC++ but not for C
/home/peter997799/chipyard/.conda-env/bin/../lib/gcc/x86_64-conda-linux-gnu/11.4.0/../../../../x86_64-conda-linux-gnu/bin/ing .note.GNU-stack section implies executable stack
/home/peter997799/chipyard/.conda-env/bin/../lib/gcc/x86_64-conda-linux-gnu/11.4.0/../../../../x86_64-conda-linux-gnu/bin/deprecated and will be removed in a future version of the linker
/home/daniel9856/chipyard/sims/vcs/simv-constellation.test-TestConfig00 up to date
make[1]: Leaving directory '/home/daniel9856/chipyard/sims/vcs/generated-src/constellation.test.TestHarness.TestConfig00/cs.TestConfig00'

What might be going wrong?
Thanks

[danielfufu]

And my vcs version is 2023.12.
Update : I've already fix the run-binary-debug issue, but it still didn't generate .v file.

[jerryz123]

Is there no verilog files generated in sims/vcs/generatd-src/constellation.test.TestHarness.TestConfig00/gen-collateral?