SPI Slave With Always Asserted CS

[xmos-jmccarthy]

Thank you for submitting an SDK feature request. Please provide as much information you can.

Describe the feature
Some SPI slave devices are used with a hardwired CS on the PCB, and the master expects to just clock data as required, never having to explicitly assert/deassert CS. The current SPI Slave device requires assertion and deassertion of CS to operate.

Will this change any current APIs? How?
Unknown, but most likely.

Who will benefit with this feature?
Anyone who wants to use xcore as a SPI slave with hardwired asserted CS.

Any Other info
This would most likely be a rewrite of the underlying HIL IO lib.