Add RISC-V Vector support. #979
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Co-authored-by: Ludovic Henry <[email protected]>
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Thanks a lot for your PR, this is awesome! I'll take the time to review it in detail over the weekend. |
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Wow. Thanks a lot for that. 🙇 |
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There is a test failure I can't reproduce locally. One of the difference is the QEMU version so I'll debug that out next week. |
JohanMabille
approved these changes
Nov 28, 2023
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Hello,
This adds support for the RISC-V architecture by using the RISC-V Vector Intrinsics [1]. I've added support for CI similarly to ARM SVE.
Thank you for your review!
Fixes #503
[1] https://github.com/riscv-non-isa/rvv-intrinsic-doc