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Add APX ISA extension #450

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Add APX ISA extension #450

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@flobernd flobernd commented Sep 12, 2023 •
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### Open Tasks
- [x] Rename ISA-set of some existing definitions to be able to distinguish between the new ones
- [x] Add APX mode
- [x] Support new registers in `ZydisRegisterGetLargestEnclosing`, etc.
- [ ] Report DFV flags in public struct

@flobernd flobernd changed the title Add AMX ISA extension Add APX ISA extension Sep 12, 2023
flobernd
flobernd commented Sep 14, 2023
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flobernd commented Sep 14, 2023
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@flobernd flobernd changed the base branch from master to ud0-compat January 22, 2024 14:01
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flobernd commented Jan 25, 2024
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Base automatically changed from ud0-compat to master January 26, 2024 19:34
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flobernd commented Oct 31, 2024
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src/Register.c
@@ -202,7 +202,7 @@ ZydisRegister ZydisRegisterGetLargestEnclosing(ZydisMachineMode mode, ZydisRegis
return static_reg;
}

static const ZyanU8 GPR8_MAPPING[20] =
static const ZyanU8 GPR8_MAPPING[36] =
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We should change semantics of all Register* APIs based on a ZyanBool apx parameter.

@flobernd flobernd marked this pull request as ready for review November 5, 2024 08:23
flobernd and others added 7 commits November 5, 2024 11:53
@flobernd
Fix vpcmp?str? definitions
0e4a87e
@flobernd
Regenerate encoder tables
0848597
@flobernd
Fix has_egpr flag
58acf3c
@flobernd
Fix xsha1 and xsha256 memory operand scaling
b8149e3
@mappzor
Fixed movdiri (APX) and compressed disp8 handling (#536)
35509e1 
* Fixed `movdiri` (APX) and compressed disp8 handling

* Fixed VSIB encoding in 16-bit mode

* Workaround for `xsha1`/`xsha256`
@flobernd
Fix montmul operand scaling
25eb33c
@mappzor
Removed xsha1/xsha256 workaround (#537)
147a375 
* Removed `xsha1`/`xsha256` workaround

* Reworked `REX2` handling
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3 participants
@flobernd @athre0z @mappzor