add CI test for generating verilog on FPGA

OSCPU · Aug 24, 2024 · ecce4b9 · ecce4b9
1 parent e79841e
commit ecce4b9
Showing 1 changed file with 9 additions and 1 deletion.
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -45,7 +45,15 @@ jobs:
             source ./env.sh
             make clean
             make verilog
-
+      - name: Generate Verilog for FPGA
+        run: |
+            cd $GITHUB_WORKSPACE/../xs-env
+            source ./env.sh
+            cd $GITHUB_WORKSPACE/../xs-env/NutShell
+            source ./env.sh
+            make clean
+            make verilog BOARD=pynq
+            
       - name: Microbench - Nutshell
         run: |
             cd $GITHUB_WORKSPACE/../xs-env