utility: use unified MemReqSource (#139)

OpenXiangShan · Aug 17, 2023 · 51b7c5f · 51b7c5f
1 parent 8f2f050
commit 51b7c5f
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Showing 12 changed files with 13 additions and 25 deletions.
diff --git a/Utility b/Utility
diff --git a/src/main/scala/huancun/Common.scala b/src/main/scala/huancun/Common.scala
@@ -23,6 +23,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.util.{BundleMap, UIntToOH1}
+import utility.MemReqSource
 
 abstract class InnerTask(implicit p: Parameters) extends HuanCunBundle {
   val sourceId = UInt(sourceIdBits.W)
@@ -235,21 +236,3 @@ class PrefetchRecv extends Bundle {
   val addr_valid = Bool()
   val l2_pf_en = Bool()
 }
-
-// indicates where the memory access request comes from
-// a dupliacte of this is in Xiangshan.package and CoupledL2.common
-object MemReqSource extends Enumeration {
-  val NoWhere = Value("NoWhere")
-
-  val CPUInst = Value("CPUInst")
-  val CPULoadData = Value("CPULoadData")
-  val CPUStoreData = Value("CPUStoreData")
-  val CPUAtomicData = Value("CPUAtomicData")
-  val L1InstPrefetch = Value("L1InstPrefetch")
-  val L1DataPrefetch = Value("L1DataPrefetch")
-  val PTW = Value("PTW")
-  val L2Prefetch = Value("L2Prefetch")
-  val ReqSourceCount = Value("ReqSourceCount")
-
-  val reqSourceBits = log2Ceil(ReqSourceCount.id)
-}
diff --git a/src/main/scala/huancun/HCCacheParameters.scala b/src/main/scala/huancun/HCCacheParameters.scala
@@ -26,8 +26,7 @@ import freechips.rocketchip.diplomacy.BufferParams
 import freechips.rocketchip.tilelink.{TLBufferParams, TLChannelBeatBytes, TLEdgeIn, TLEdgeOut}
 import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase, ControlKey}
 import huancun.prefetch.PrefetchParameters
-import MemReqSource._
-import utility.ReqSourceKey
+import utility.{MemReqSource, ReqSourceKey}
 
 case object HCCacheParamsKey extends Field[HCCacheParameters](HCCacheParameters())
 

diff --git a/src/main/scala/huancun/SinkA.scala b/src/main/scala/huancun/SinkA.scala
@@ -23,6 +23,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
+import utility.MemReqSource
 
 class SinkA(implicit p: Parameters) extends HuanCunModule {
   val io = IO(new Bundle() {

diff --git a/src/main/scala/huancun/SinkB.scala b/src/main/scala/huancun/SinkB.scala
@@ -23,6 +23,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
+import utility.MemReqSource
 
 class SinkB(edge: TLEdgeOut)(implicit p: Parameters) extends HuanCunModule {
   val io = IO(new Bundle() {

diff --git a/src/main/scala/huancun/SourceA.scala b/src/main/scala/huancun/SourceA.scala
@@ -25,6 +25,7 @@ import chisel3.util._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink._
 import huancun.utils.HoldUnless
+import utility.MemReqSource
 
 class SourceA(edge: TLEdgeOut)(implicit p: Parameters) extends HuanCunModule {
   val io = IO(new Bundle() {

diff --git a/src/main/scala/huancun/SourceC.scala b/src/main/scala/huancun/SourceC.scala
@@ -23,7 +23,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
-import utility.ReqSourceKey
+import utility.{MemReqSource, ReqSourceKey}
 
 class SourceCPipe(implicit p: Parameters) extends HuanCunBundle {
   val task = new SourceCReq

diff --git a/src/main/scala/huancun/TopDownMonitor.scala b/src/main/scala/huancun/TopDownMonitor.scala
@@ -5,6 +5,7 @@ import chisel3._
 import chisel3.util._
 import huancun.noninclusive.DirResult
 import huancun.utils.{XSPerfAccumulate, XSPerfHistogram}
+import utility.MemReqSource
 
 class TopDownMonitor()(implicit p: Parameters) extends HuanCunModule {
   val banks = 1 << bankBits

diff --git a/src/main/scala/huancun/noninclusive/MSHR.scala b/src/main/scala/huancun/noninclusive/MSHR.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.TLHints._
 import huancun._
 import huancun.utils._
 import huancun.MetaData._
-import utility.ParallelMax
+import utility.{MemReqSource, ParallelMax}
 
 class C_Status(implicit p: Parameters) extends HuanCunBundle {
   // When C nest A, A needs to know the status of C and tells C to release through to next level

diff --git a/src/main/scala/huancun/noninclusive/ProbeHelper.scala b/src/main/scala/huancun/noninclusive/ProbeHelper.scala
@@ -4,8 +4,9 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.{TLMessages, TLPermissions}
-import huancun.{HuanCunModule, MSHRRequest, MemReqSource, MetaData}
+import huancun.{HuanCunModule, MSHRRequest, MetaData}
 import huancun.utils.XSPerfAccumulate
+import utility.MemReqSource
 
 class ProbeHelper(entries: Int = 5, enqDelay: Int = 1)(implicit p: Parameters)
   extends HuanCunModule with HasClientInfo

diff --git a/src/main/scala/huancun/noninclusive/SinkC.scala b/src/main/scala/huancun/noninclusive/SinkC.scala
@@ -5,6 +5,7 @@ import chisel3.util._
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.tilelink.{TLBundleC, TLMessages}
 import huancun._
+import utility.MemReqSource
 
 class SinkC(implicit p: Parameters) extends BaseSinkC {
 

diff --git a/src/main/scala/huancun/noninclusive/SliceCtrl.scala b/src/main/scala/huancun/noninclusive/SliceCtrl.scala
@@ -4,7 +4,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import huancun._
-import utility.RegNextN
+import utility.{MemReqSource, RegNextN}
 
 class SliceCtrl()(implicit p: Parameters) extends HuanCunModule {
+1 −0		src/main/scala/utility/BitUtils.scala
+54 −5		src/main/scala/utility/ChiselDB.scala
+3 −4		src/main/scala/utility/TLUtils/BusKeyField.scala