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sram: fix formate
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xiaokamikami committed Apr 22, 2024
1 parent 22e8538 commit f025e8d
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2 changes: 1 addition & 1 deletion src/main/scala/huancun/utils/SRAMWrapper.scala
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ package huancun.utils
import chisel3._
import chisel3.util._
import freechips.rocketchip.util.Pow2ClockDivider
import utility.{ClockGate}
import utility.ClockGate

class SRAMWrapper[T <: Data]
(
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