fix(zfhmin): support flh and fsh with mmu mode

OpenXiangShan · Dec 4, 2024 · ca3baa0 · ca3baa0
1 parent e7be8a6
commit ca3baa0
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Showing 3 changed files with 18 additions and 2 deletions.
diff --git a/src/isa/riscv64/include/isa-all-instr.h b/src/isa/riscv64/include/isa-all-instr.h
@@ -200,6 +200,7 @@
 #ifdef CONFIG_RV_ZFH_MIN
 #define ZFH_MIN_INSTR_BINARY(f) \
   f(flh) f(fsh) \
+  f(flh_mmu) f(fsh_mmu) \
   f(fmv_x_h) f(fmv_h_x)  \
   f(fcvt_s_h) f(fcvt_h_s) f(fcvt_d_h) f(fcvt_h_d) 
 #else //CONFIG_RV_ZFH_MIN

diff --git a/src/isa/riscv64/instr/rvf/decode.h b/src/isa/riscv64/instr/rvf/decode.h
@@ -170,6 +170,9 @@ def_THelper(fload) {
 #ifndef CONFIG_FPU_NONE
       def_INSTR_TAB("??????? ????? ????? 010 ????? ????? ??", flw_mmu);
       def_INSTR_TAB("??????? ????? ????? 011 ????? ????? ??", fld_mmu);
+      #ifdef CONFIG_RV_ZFH_MIN
+        def_INSTR_TAB("??????? ????? ????? 001 ????? ????? ??", flh_mmu);
+      #endif
 #endif // CONFIG_FPU_NONE
     }
 
@@ -193,8 +196,8 @@ def_THelper(fstore) {
       def_INSTR_TAB("??????? ????? ????? 010 ????? ????? ??", fsw);
       def_INSTR_TAB("??????? ????? ????? 011 ????? ????? ??", fsd);
       #ifdef CONFIG_RV_ZFH_MIN
-        def_INSTR_TAB("??????? ????? ????? 001 ????? ????? ??", fsh); 
-      #endif//CONFIG_RV_ZFH
+        def_INSTR_TAB("??????? ????? ????? 001 ????? ????? ??", fsh);
+      #endif
     }
 #endif // CONFIG_FPU_NONE
 
@@ -211,6 +214,9 @@ def_THelper(fstore) {
     if (fp_enable()) {
       def_INSTR_TAB("??????? ????? ????? 010 ????? ????? ??", fsw_mmu);
       def_INSTR_TAB("??????? ????? ????? 011 ????? ????? ??", fsd_mmu);
+      #ifdef CONFIG_RV_ZFH_MIN
+        def_INSTR_TAB("??????? ????? ????? 001 ????? ????? ??", fsh_mmu);
+      #endif
     }
 #endif // CONFIG_FPU_NONE
 

diff --git a/src/isa/riscv64/instr/rvzfh/exec.h b/src/isa/riscv64/instr/rvzfh/exec.h
@@ -10,6 +10,15 @@ def_EHelper(fsh) {
   rtl_sm(s, ddest, dsrc1, id_src2->imm, 2, MMU_DIRECT);
 }
 
+def_EHelper(flh_mmu) {
+  rtl_lm(s, ddest, dsrc1, id_src2->imm, 2, MMU_TRANSLATE);
+  rtl_fsr(s, ddest, ddest, FPCALL_W16);
+}
+
+def_EHelper(fsh_mmu) {
+  rtl_sm(s, ddest, dsrc1, id_src2->imm, 2, MMU_TRANSLATE);
+}
+
 def_EHelper(fmv_x_h) {
   rtl_sext(s, ddest, dsrc1, 2);
 }