chisel: update to chisel3.6 and replace deprecated APIs

build.sc

@@ -10,13 +10,12 @@ import publish._
 import scalalib._
 
 object ivys{
-  val sv = "2.12.13"
-  val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.0"
-  val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0"
-  val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.5.2"
+  val sv = "2.13.10"
+  val chisel3 = ivy"edu.berkeley.cs::chisel3:3.6.0"
+  val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"
+  val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.6.2"
   val chiselCirct = ivy"com.sifive::chisel-circt:0.6.0"
   val scalatest = ivy"org.scalatest::scalatest:3.2.2"
-  val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
 }
 
 trait YSModule extends ScalaModule with PublishModule {
@@ -25,11 +24,9 @@ trait YSModule extends ScalaModule with PublishModule {
 
   override def scalaVersion = ivys.sv
 
-  override def compileIvyDeps = Agg(ivys.macroParadise)
+  override def scalacPluginIvyDeps = Agg(ivys.chisel3Plugin)
 
-  override def scalacPluginIvyDeps = Agg(ivys.macroParadise, ivys.chisel3Plugin)
-
-  override def scalacOptions = Seq("-Xsource:2.11")
+  override def scalacOptions = Seq("-Xsource:2.13")
 
   override def ivyDeps = (if(chiselOpt.isEmpty) Agg(ivys.chisel3) else Agg.empty[Dep]) ++ Agg(ivys.chiselCirct)
 

src/main/scala/yunsuan/util/LookupTree.scala

@@ -26,7 +26,7 @@ object LookupTree {
 
 object LookupTreeDefault {
   def apply[T <: Data](key: UInt, default: T, mapping: Iterable[(UInt, T)]): T =
-    MuxLookup(key, default, mapping.toSeq)
+    MuxLookup(key, default)(mapping.toSeq)
 }
 
 

src/main/scala/yunsuan/vector/VectorConvert/util/Rounding.scala

@@ -20,16 +20,15 @@ class RoundingUnit(val width: Int) extends Module {
   val inexact = r | s
   val r_up = MuxLookup(
     io.rm,
-    false.B,
-    Seq(
-      RNE -> ((r && s) || (r && !s && g)),
-      RTZ -> false.B,
-      RUP -> (inexact & !io.signIn),
-      RDN -> (inexact & io.signIn),
-      RMM -> r,
-      RTO -> ((r || s) && !g),
-    )
-  )
+    false.B
+  )(Seq(
+    RNE -> ((r && s) || (r && !s && g)),
+    RTZ -> false.B,
+    RUP -> (inexact & !io.signIn),
+    RDN -> (inexact & io.signIn),
+    RMM -> r,
+    RTO -> ((r || s) && !g),
+  ))
 
   io.inexact := inexact
   io.r_up := r_up

src/test/scala/top/VectorSimTop.scala

@@ -358,9 +358,7 @@ class SimTop() extends VPUTestModule {
 
 
 object SimTop extends App {
-  override def main(args: Array[String]): Unit = {
-    (new ChiselStage).execute(args, Seq(
-      ChiselGeneratorAnnotation(() => new SimTop())
-    ))
-  }
+  (new ChiselStage).execute(args, Seq(
+    ChiselGeneratorAnnotation(() => new SimTop())
+  ))
 }