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feat(core/remio): add Remote I/O infrastructure #176
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Generic comment: the namespace for this module can be shortened. I suggest rmio, remio, rm_io, rem_io
some of the comments may be a bit subjective. @josecm feel free to wage in
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This new version includes a refactor of the code following @DavidMCerdeira's suggestions.
This refactoring improves the structure and maintainability of the code. |
@josecm What are your thoughts on this? From @DavidMCerdeira's list of suggestions, |
My suggestion would be either |
Update: 01c2cbe |
The namespace change should be reflected in the function, variable names, enums, etc |
Done 00b5acd |
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I'd still like to test this before approving, but for now it looks good! 👍
You can squash the commits into a single one now
Thanks, @DavidMCerdeira ! Also, please take a look at this commit, where I temporarily resolved the issue by replacing the |
I think for now it is fine. Actually we are aware of at least two platforms that require this behavior to work with bao currently. We should eventually allow platforms to have specific code to handle this sort of platform specific quirks |
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Despite the very (!) good work, I think we still need a bit of work on this PR. This is my first pass on it. I think we will need one or two more.
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Only nitpicks
Otherwise looks good to me!
@joaopeixoto13 rebase on main and resolve conflicts please |
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Done. If everything looks good, I can proceed to merge all the fix commits into the main parent commit that introduced the feature. |
Please go ahead with that. |
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Done ✅ |
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This commit renames the first argument of the hypercall to make the code independent of the specific hypercall type. Signed-off-by: João Peixoto <[email protected]>
This commit introduces a separation of input and output conventions for hypercalls, addressing architecture-specific differences between ARM and RISC-V. On ARM, the x0 register is used to pass both the extid, fid, and the return value, while additional parameters (hypercalls arguments) are passed via registers x1 to xn. On RISC-V, while the return value is passed in a0, the extid and fid are handled by the a7 and a6 registers, respectively. This means that the hypercall input arguments on RISC-V should be passed through registers a0 to a5, while output hypercall arguments are passed via a2 and onward (because all registers except a0 and a1 must be preserved across an SBI call by the callee). To accommodate these differences and provide a uniform interface, two macros were introduced to abstract the handling of input and output hypercall arguments across architectures. Signed-off-by: João Peixoto <[email protected]>
This commit introduces two methods for setting and retrieving hypercall arguments, allowing each hypercall implementation to flexibly manage its specific arguments as needed. Signed-off-by: João Peixoto <[email protected]>
Refactored the vCPU program counter incrementation by introducing the architecture-agnostic method vcpu_writepc, aligning the implementation with the approach used in the ARM architecture. Signed-off-by: João Peixoto <[email protected]>
Implemented support for abort and exception handlers to suspend the current vCPU based on the vCPU active flag. Signed-off-by: João Peixoto <[email protected]>
This commit introduces two new methods to the objpool API. The first method, objpool_alloc_with_id, enables the allocation of an object within a pool and returns the index where the object was allocated. The second method, objpool_get_by_id, allows retrieving a previously allocated object using the index of the pool where it was initially allocated. Signed-off-by: João Peixoto <[email protected]>
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This commit introduces the foundational support for VirtIO by implementing a mechanism to forward VirtIO requests bidirectionally between the guest VM (or frontend VM) and its associated backend VM. Signed-off-by: João Peixoto <[email protected]>
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This PR introduces the foundational support for VirtIO by implementing a mechanism to forward VirtIO requests bidirectionally between the guest VM (or frontend VM) and its associated backend VM.
Validation