[update][soc/bl616] update std api for pm

drivers/soc/bl616/std/include/bl616_glb.h

@@ -1732,6 +1732,7 @@ uint32_t GLB_Get_Flash_Id_Value(void);
 BL_Err_Type GLB_Trim_Ldo18ioVoutSel(void);
 BL_Err_Type GLB_Trim_Ldo18ioBypass(void);
 BL_Err_Type GLB_Trim_Ldo18ioVoutTrim(void);
+void GLB_Power_Down_Ldo18ioVout(void);
 /*----------*/
 BL_Err_Type GLB_Set_SRAM_RET(uint32_t value);
 uint32_t GLB_Get_SRAM_RET(void);

drivers/soc/bl616/std/include/bl616_hbn.h

@@ -686,6 +686,9 @@ BL_Err_Type HBN_Out1_Callback_Install(uint8_t intType, intCallback_Type *cbFun);
 /*----------*/
 BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, uint8_t trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec);
 /*----------*/
+BL_Err_Type HBN_Set_Xtal_32K_Capbank(uint8_t value);
+BL_Err_Type HBN_Set_Xtal_32K_Inverter_Amplify_Strength(uint8_t value);
+BL_Err_Type HBN_Set_Xtal_32K_Regulator(uint8_t level);
 BL_Err_Type HBN_Power_On_Xtal_32K(void);
 BL_Err_Type HBN_Power_Off_Xtal_32K(void);
 BL_Err_Type HBN_Keep_On_RC32K(void);

drivers/soc/bl616/std/src/bl616_glb.c

@@ -3772,6 +3772,23 @@ BL_Err_Type ATTR_TCM_SECTION GLB_Trim_Ldo18ioVoutTrim(void)
     return ERROR;
 }
 
+/****************************************************************************/ /**
+ * @brief  power down LDO18IO vout
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION GLB_Power_Down_Ldo18ioVout(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18IO);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO18IO);
+    BL_WR_REG(GLB_BASE, GLB_LDO18IO, tmpVal);
+}
+
 /****************************************************************************/ /**
  * @brief  set sram_ret value
  *
@@ -3861,8 +3878,8 @@ uint32_t GLB_Get_SRAM_PARM(void)
  *
  * @param  emType: EM type, this parameter can be one of the following values:
  *           @arg GLB_WRAM160KB_EM0KB,
- *           @arg GLB_WRAM128KB_EM32KB, 
- *           @arg GLB_WRAM96KB_EM64KB, 
+ *           @arg GLB_WRAM128KB_EM32KB,
+ *           @arg GLB_WRAM96KB_EM64KB,
  *
  * @return SUCCESS or ERROR
  *

drivers/soc/bl616/std/src/bl616_hbn.c

@@ -599,11 +599,11 @@ BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, uint8_t threshold, uint8_t mode)
  * [0] : watch dog reset
  *
 *******************************************************************************/
-void HBN_Get_Reset_Event(uint8_t* event)
+void HBN_Get_Reset_Event(uint8_t *event)
 {
     uint32_t tmpVal;
     tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
-    *event = BL_GET_REG_BITS_VAL(tmpVal,HBN_RESET_EVENT);
+    *event = BL_GET_REG_BITS_VAL(tmpVal, HBN_RESET_EVENT);
 }
 /****************************************************************************/ /**
  * @brief  HBN clear reset event
@@ -613,7 +613,7 @@ void HBN_Clr_Reset_Event(void)
 {
     uint32_t tmpVal;
     tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
-    tmpVal |= (1<<13);
+    tmpVal |= (1 << 13);
     BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
 }
 
@@ -975,6 +975,63 @@ BL_Err_Type ATTR_TCM_SECTION HBN_Set_HRAM_Ret(void)
     return SUCCESS;
 }
 
+/****************************************************************************/ /**
+ * @brief  Set xtal32k_capbank
+ *
+ * @param  value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_Xtal_32K_Capbank(uint8_t value)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL32K_CAPBANK, value);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set xtal32k's inverter amplify strength
+ *
+ * @param  value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_Xtal_32K_Inverter_Amplify_Strength(uint8_t value)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL32K_INV_STRE, value);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set xtal32k_regulator
+ *
+ * @param  level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_Xtal_32K_Regulator(uint8_t level)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL32K_REG, level);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
 /****************************************************************************/ /**
  * @brief  Power on XTAL 32K
  *
@@ -2181,7 +2238,6 @@ BL_Err_Type HBN_Disable_BOD_IRQ(void)
     return SUCCESS;
 }
 
-
 /****************************************************************************/ /**
  * @brief  HBN out0 install interrupt callback
  *

drivers/soc/bl616/std/src/bl616_pds.c

@@ -754,7 +754,7 @@ BL_Err_Type PDS_Power_Off_WB(void)
     tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_ISO_EN);
     BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
 
-    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_NP_PWR_OFF);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_PWR_OFF);
     BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
 
     return SUCCESS;
@@ -773,7 +773,7 @@ BL_Err_Type PDS_Power_On_WB(void)
     uint32_t tmpVal = 0;
 
     tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
-    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_NP_PWR_OFF);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_PWR_OFF);
     BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
 
     tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_ISO_EN);

drivers/soc/bl616/std/src/bl616_pm.c

@@ -39,6 +39,10 @@
 #define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V
 #endif
 
+#ifndef PM_PDS_LDO18IO_POWER_DOWN
+#define PM_PDS_LDO18IO_POWER_DOWN  0
+#endif
+
 /* Cache Way Disable, will get from l1c register */
 uint8_t cacheWayDisable = 0;
 
@@ -605,6 +609,12 @@ void ATTR_TCM_SECTION pm_pds_mode_enter(enum pm_pds_sleep_level pds_level,
     /* To make it simple and safe*/
     __ASM volatile("csrc mstatus, 8");
 
+    /* Must Disable ADC, Otherwise, the current increase 1mA  */
+    /* adc disable */
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+
     /* get xtal type */
     HBN_Get_Xtal_Type(&xtal_type);
 
@@ -672,11 +682,16 @@ void ATTR_TCM_SECTION pm_pds_mode_enter(enum pm_pds_sleep_level pds_level,
     } else {
     }
 
-    // psram io config
-    for (uint8_t i = 35; i < 56; i++) {
-        //*((volatile uint32_t *)(0x200008C4 + i * 4)) = 0;
-    }
+    /* psram io config */
+    // for (uint8_t i = 41; i < 53; i++) {
+    //     *((volatile uint32_t *)(0x200008C4 + i * 4)) = 0;
+    // }
+#endif
 
+#if PM_PDS_LDO18IO_POWER_DOWN
+    /* must power down ldo18io, Otherwise, the current is abnormal */
+    GLB_Power_Down_Ldo18ioVout();
+    arch_delay_ms(30);
 #endif
 
 #if PM_PDS_GPIO_KEEP_EN

drivers/soc/bl616/std/src/bl616_romapi_patch.c

@@ -1942,6 +1942,23 @@ uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void)
     return 0x00000000;
 }
 
+/****************************************************************************/ /**
+ * @brief  power down LDO18IO vout
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION GLB_Power_Down_Ldo18ioVout(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18IO);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO18IO);
+    BL_WR_REG(GLB_BASE, GLB_LDO18IO, tmpVal);
+}
+
 /****************************************************************************/ /**
  * @brief  Enable PDS power on PLL
  *
@@ -3775,7 +3792,7 @@ BL_Err_Type PDS_Power_Off_WB(void)
     tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_ISO_EN);
     BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
 
-    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_NP_PWR_OFF);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_PWR_OFF);
     BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
 
     return SUCCESS;
@@ -3794,7 +3811,7 @@ BL_Err_Type PDS_Power_On_WB(void)
     uint32_t tmpVal = 0;
 
     tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
-    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_NP_PWR_OFF);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_PWR_OFF);
     BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
 
     tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_WB_ISO_EN);
@@ -4110,6 +4127,64 @@ BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg)
     return SUCCESS;
 }
 
+/****************************************************************************/ /**
+ * @brief  Set xtal32k_capbank
+ *
+ * @param  value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_Xtal_32K_Capbank(uint8_t value)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL32K_CAPBANK, value);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set xtal32k's inverter amplify strength
+ *
+ * @param  value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_Xtal_32K_Inverter_Amplify_Strength(uint8_t value)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL32K_INV_STRE, value);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set xtal32k_regulator
+ *
+ * @param  level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_Xtal_32K_Regulator(uint8_t level)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL32K_REG, level);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+
 /****************************************************************************/ /**
  * @brief  Power on XTAL 32K
  *