fix

chipsalliance · Mar 11, 2024 · 9505d87 · 9505d87
1 parent 6e1e785
commit 9505d87
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala
@@ -57,7 +57,7 @@ trait HasConfigurablePRCILocations { this: HasPRCILocations =>
   val prciClockNode = ClockAdapterNode()
   val io_clocks = Option.when(p(SubsystemDriveClockFromIO)){
     val source = ClockSourceNode(Seq(ClockSourceParameters()))
-    prciClockNode :*= source
+    prciClockNode :*= FixedClockBroadcast() := source
     InModuleBody(source.makeIOs())
   }
 }
@@ -90,7 +90,7 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
 
   val busContextName = "subsystem"
 
-  viewpointBus.clockNode := prciClockNode
+  viewpointBus.clockNode :*= prciClockNode
 
   // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding
   //       a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.

diff --git a/src/main/scala/tilelink/BusWrapper.scala b/src/main/scala/tilelink/BusWrapper.scala
@@ -36,7 +36,7 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
     with HasTLBusParams
     with CanHaveBuiltInDevices
 {
-  val clockNode = ClockAdapterNode() // device clocks attach here
+  val clockNode = ClockIdentityNode() // device clocks attach here
   val fixedClockNode = FixedClockBroadcast(fixedClockOpt)
   private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt)))
 
@@ -84,14 +84,14 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
     from(name) { gen(inwardNode :*=* TLNameNode("tl")) }
 
   def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
-    bus.clockNode := asyncMux(xType, asyncClockNode, this.clockNode)
+    bus.clockNode := asyncMux(xType, asyncClockNode, fixedClockNode)
     coupleTo(s"bus_named_${bus.busName}") {
       bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _
     }
   }
 
   def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
-    this.clockNode := asyncMux(xType, asyncClockNode, bus.clockNode)
+    this.clockNode := asyncMux(xType, asyncClockNode, bus.fixedClockNode)
     coupleFrom(s"bus_named_${bus.busName}") {
       _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType)
     }