Merge pull request #3474 from chipsalliance/dtim_addr

add WithScratchpadsBaseAddress to alter rocket core dtim address
chipsalliance · Aug 18, 2023 · eee99e8 · eee99e8
2 parents 7681e28 + 49e8e92
commit eee99e8
Showing 1 changed file with 11 additions and 0 deletions.
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -580,6 +580,17 @@ class WithNoSlavePort extends Config((site, here, up) => {
   case ExtIn => None
 })
 
+class WithScratchpadsBaseAddress(address: BigInt) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      dcache = tp.tileParams.dcache.map(
+        _.copy(scratch = Some(address))
+      )
+    ))
+    case t => t
+  }
+})
+
 class WithScratchpadsOnly extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(