Skip to content

Commit

Permalink
fix: fix PWRDWN bit
Browse files Browse the repository at this point in the history 
add: add USBD_SOF_OUT preprocessor variable fot F429 OTG FS
add: add CDC demo for NUCLEO-F429ZI

 Github issue #9
  • Loading branch information
@dmitrystu
dmitrystu committed Feb 1, 2018
1 parent eb22e60 commit 0ae2d92
Show file tree
Hide file tree
Showing 4 changed files with 145 additions and 27 deletions.
8 changes: 7 additions & 1 deletion Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -136,4 +136,10 @@ stm32l476xg 32l476rg-nucleo:
@$(MAKE) clean demo STARTUP='$(CMSISDEV)/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l476xx.s' \
LDSCRIPT='demo/stm32l476xg.ld' \
DEFINES='STM32L4 STM32L476xx USBD_SOF_DISABLED' \
CFLAGS='-mcpu=cortex-m4 -mthumb'
CFLAGS='-mcpu=cortex-m4 -mthumb'

stm32f429xi 32f429zi-nucleo:
@$(MAKE) clean demo STARTUP='$(CMSISDEV)/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s' \
LDSCRIPT='demo/stm32f429xi.ld' \
DEFINES='STM32F4 STM32F429xx USBD_SOF_DISABLED' \
CFLAGS='-mcpu=cortex-m4 -mthumb'
23 changes: 23 additions & 0 deletions demo/cdc_startup.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,29 @@ static void cdc_init_rcc (void) {
/* switch to PLL */
_BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
_WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);

#elif defined(STM32F429xx)
/* set flash latency 2WS */
_BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2WS);
/* setting up PLL 16MHz HSI, VCO=144MHz, PLLP = 72MHz PLLQ = 48MHz */
_BMD(RCC->PLLCFGR,
RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLP,
_VAL2FLD(RCC_PLLCFGR_PLLM, 8) | _VAL2FLD(RCC_PLLCFGR_PLLN, 72) | _VAL2FLD(RCC_PLLCFGR_PLLQ, 3));
/* enabling PLL */
_BST(RCC->CR, RCC_CR_PLLON);
_WBS(RCC->CR, RCC_CR_PLLRDY);
/* switching to PLL */
_BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
_WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);
/* enabling GPIOA and setting PA11 and PA12 to AF10 (USB_FS) */
_BST(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);
_BST(GPIOA->AFR[1], (0x0A << 12) | (0x0A << 16));
_BMD(GPIOA->MODER, (0x03 << 22) | (0x03 << 24), (0x02 << 22) | (0x02 << 24));

_BST(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
_BMD(GPIOC->MODER, (0x03 << 18), (0x02 << 18));
_BMD(RCC->CFGR, RCC_CFGR_MCO2, RCC_CFGR_MCO2PRE_2);

#else
#error Not supported
#endif
Expand Down
92 changes: 92 additions & 0 deletions demo/stm32f429xi.ld
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,92 @@
ENTRY(Reset_Handler)
MEMORY
{
ROM (rx): ORIGIN = 0x08000000, LENGTH = 2048K
BANK0 (rx): ORIGIN = 0x08000000, LENGTH = 1024K
BANK1 (rx): ORIGIN = 0x08100000, LENGTH = 1024K
RAM (rwx): ORIGIN = 0x20000000, LENGTH = 96K
RAM2 (rwx): ORIGIN = 0x10000000, LENGTH = 32K
}
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init)) KEEP(*(.fini))
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o).dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > ROM
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
__data_end__ = .;
} > RAM
.bss (NOLOAD) :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap (NOLOAD) :
{
__end__ = .;
*(.heap*)
__HeapLimit = .;
} > RAM
.stack_dummy (NOLOAD) :
{
*(.stack)
} > RAM

__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

PROVIDE(_estack = __stack);
PROVIDE(_sidata = __etext);
PROVIDE(_sdata = __data_start__);
PROVIDE(_edata = __data_end__);
PROVIDE(_sbss = __bss_start__);
PROVIDE(_ebss = __bss_end__);
}
49 changes: 23 additions & 26 deletions src/usbd_stm32f429_otgfs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -95,33 +95,34 @@ void enable(bool enable) {
if (enable) {
/* enabling USB_OTG in RCC */
_BST(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
/* Set Vbus enabled for USB */
// _BST(PWR->CR2, PWR_CR2_USV);
/* select Internal PHY */
OTG->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
// /* do core soft reset */
// _WBS(OTG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL);
// _BST(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
// _WBC(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
/* do core soft reset */
_WBS(OTG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL);
_BST(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
_WBC(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
/* configure OTG as device */
OTG->GUSBCFG = USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL |
_VAL2FLD(USB_OTG_GUSBCFG_TRDT, 0x06);
/* configuring Vbus sense and powerup PHY */
#if defined(USBD_VBUS_DETECT)
OTG->GCCFG = USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_PWRDWN;
// OTG->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN;
/* configuring Vbus sense and SOF output */
#if defined (USBD_VBUS_DETECT) && defined(USBD_SOF_OUT)
OTG->GCCFG = USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_SOFOUTEN;
#elif defined(USBD_VBUS_DETECT)
OTG->GCCFG = USB_OTG_GCCFG_VBUSBSEN;
#elif defined(USBD_SOF_OUT)
OTG->GCCFG = USB_OTG_GCCFG_NOVBUSSENS | USB_OTG_GCCFG_SOFOUTEN;
#else
// OTG->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
OTG->GCCFG = USB_OTG_GCCFG_NOVBUSSENS | USB_OTG_GCCFG_PWRDWN;
OTG->GCCFG = USB_OTG_GCCFG_NOVBUSSENS;
#endif

/* restart PHY*/
/* enable PHY clock */
*OTGPCTL = 0;
/* soft disconnect device */
_BST(OTGD->DCTL, USB_OTG_DCTL_SDIS);
/* Setup USB FS speed and frame interval */
_BMD(OTGD->DCFG, USB_OTG_DCFG_PERSCHIVL | USB_OTG_DCFG_DSPD,
_VAL2FLD(USB_OTG_DCFG_PERSCHIVL, 0) | _VAL2FLD(USB_OTG_DCFG_DSPD, 0x03));
/* setting max RX FIFO size */
OTG->GRXFSIZ = RX_FIFO_SZ;
/* setting up EP0 TX FIFO SZ as 64 byte */
OTG->DIEPTXF0_HNPTXFSIZ = RX_FIFO_SZ | (0x10 << 16);
/* unmask EP interrupts */
OTGD->DIEPMSK = USB_OTG_DIEPMSK_XFRCM;
/* unmask core interrupts */
Expand All @@ -134,14 +135,9 @@ void enable(bool enable) {
/* clear pending interrupts */
OTG->GINTSTS = 0xFFFFFFFF;
/* unmask global interrupt */
OTG->GAHBCFG = USB_OTG_GAHBCFG_GINT;
/* setting max RX FIFO size */
OTG->GRXFSIZ = RX_FIFO_SZ;
/* setting up EP0 TX FIFO SZ as 64 byte */
OTG->DIEPTXF0_HNPTXFSIZ = RX_FIFO_SZ | (0x10 << 16);
_BST(OTG->GAHBCFG, USB_OTG_GAHBCFG_GINT);
} else {
if (RCC->AHB2ENR & RCC_AHB2ENR_OTGFSEN) {
// _BCL(PWR->CR2, PWR_CR2_USV);
_BST(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST);
_BCL(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST);
_BCL(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
Expand All @@ -154,14 +150,15 @@ void reset (void) {
// _WBC(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
}


uint8_t connect(bool connect) {
if (connect) {
_BCL(OTG->GCCFG, USB_OTG_GCCFG_PWRDWN);
/* The ST made a strange thing again. Really i dont'understand what is the reason to name
signal as PWRDWN (Power down PHY) when it works as "Power up" */
_BST(OTG->GCCFG, USB_OTG_GCCFG_PWRDWN);
_BCL(OTGD->DCTL, USB_OTG_DCTL_SDIS);
} else {
_BST(OTGD->DCTL, USB_OTG_DCTL_SDIS);
_BST(OTG->GCCFG, USB_OTG_GCCFG_PWRDWN);
_BCL(OTG->GCCFG, USB_OTG_GCCFG_PWRDWN);
}
return usbd_lane_unk;
}
Expand Down Expand Up @@ -336,7 +333,7 @@ int32_t ep_read(uint8_t ep, void* buf, uint16_t blen) {
buf += 4;
} else {
while (blen){
*(uint8_t*)buf = 0xFF & _t;
*(uint8_t*)buf++ = 0xFF & _t;
_t >>= 8;
blen --;
}
Expand Down

0 comments on commit 0ae2d92

Please sign in to comment.