Merge branch 'main' into refac_CI

.github/workflows/user_project_ci.yml

@@ -102,7 +102,7 @@ jobs:
 
           git clone --depth=1 -b mpw-7d https://github.com/efabless/mpw_precheck.git
 
-          docker run -v "$PRECHECK_ROOT":"$PRECHECK_ROOT" -v "$INPUT_DIRECTORY":"$INPUT_DIRECTORY" -v "${{ env.PDK_ROOT }}":"${{ env.PDK_ROOT }}" -e INPUT_DIRECTORY="$INPUT_DIRECTORY" -e PDK_ROOT="${{ env.PDK_ROOT }}" -e PDKPATH="${{ env.PDKPATH }}" -u $(id -u "$USER"):$(id -g "$USER") efabless/mpw_precheck:latest bash -c "cd $PRECHECK_ROOT; python3 mpw_precheck.py --input_directory $INPUT_DIRECTORY --pdk_path ${{ env.PDKPATH }} --output_directory $OUTPUT_DIRECTORY license makefile consistency xor magic_drc klayout_beol klayout_feol klayout_met_min_ca_density klayout_offgrid klayout_pin_label_purposes_overlapping_drawing klayout_zeroarea"
+          docker run -v "$PRECHECK_ROOT":"$PRECHECK_ROOT" -v "$INPUT_DIRECTORY":"$INPUT_DIRECTORY" -v "${{ env.PDK_ROOT }}":"${{ env.PDK_ROOT }}" -e INPUT_DIRECTORY="$INPUT_DIRECTORY" -e PDK_ROOT="${{ env.PDK_ROOT }}" -e PDKPATH="${{ env.PDKPATH }}" -u $(id -u "$USER"):$(id -g "$USER") efabless/mpw_precheck:latest bash -c "cd $PRECHECK_ROOT; python3 mpw_precheck.py --input_directory $INPUT_DIRECTORY --pdk_path ${{ env.PDKPATH }} --output_directory $OUTPUT_DIRECTORY license makefile consistency xor magic_drc klayout_beol klayout_feol klayout_met_min_ca_density klayout_offgrid klayout_pin_label_purposes_overlapping_drawing klayout_zeroarea lvs"
 
           cnt=$(grep -c "All Checks Passed" "$OUTPUT")
           if ! [[ $cnt ]]; then cnt=0; fi

Makefile

@@ -28,13 +28,15 @@ export PDK?=sky130A
 #export PDK?=gf180mcuC
 export PDKPATH?=$(PDK_ROOT)/$(PDK)
 
+export DISABLE_LVS?=0
+
 
 
 ifeq ($(PDK),sky130A)
 	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
 	export OPEN_PDKS_COMMIT?=e6f9c8876da77220403014b116761b0b2d79aab4
 	export OPENLANE_TAG?=2023.02.23
-	MPW_TAG ?= mpw-9c
+	MPW_TAG ?= mpw-9d
 
 ifeq ($(CARAVEL_LITE),1)
 	CARAVEL_NAME := caravel-lite
@@ -52,7 +54,7 @@ ifeq ($(PDK),sky130B)
 	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
 	export OPEN_PDKS_COMMIT?=e6f9c8876da77220403014b116761b0b2d79aab4
 	export OPENLANE_TAG?=2023.02.23
-	MPW_TAG ?= mpw-9c
+	MPW_TAG ?= mpw-9d
 
 ifeq ($(CARAVEL_LITE),1)
 	CARAVEL_NAME := caravel-lite
@@ -219,19 +221,43 @@ precheck:
 
 .PHONY: run-precheck
 run-precheck: check-pdk check-precheck
-	$(eval INPUT_DIRECTORY := $(shell pwd))
-	cd $(PRECHECK_ROOT) && \
+	@if [ "$$DISABLE_LVS" = "1" ]; then\
+		$(eval INPUT_DIRECTORY := $(shell pwd)) \
+		cd $(PRECHECK_ROOT) && \
+		docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+		-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+		-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e PDKPATH=$(PDKPATH) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK) license makefile default documentation consistency gpio_defines xor magic_drc klayout_feol klayout_beol klayout_offgrid klayout_met_min_ca_density klayout_pin_label_purposes_overlapping_drawing klayout_zeroarea"; \
+	else \
+		$(eval INPUT_DIRECTORY := $(shell pwd)) \
+		cd $(PRECHECK_ROOT) && \
+		docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+		-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+		-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e PDKPATH=$(PDKPATH) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"; \
+	fi
+
+
+BLOCKS = $(shell cd lvs && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./lvs/%/lvs_config.json check-pdk check-precheck
+	@$(eval INPUT_DIRECTORY := $(shell pwd))
+	@cd $(PRECHECK_ROOT) && \
 	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
 	-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
 	-v $(PDK_ROOT):$(PDK_ROOT) \
-	-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
-	-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
-	-e PDK_ROOT=$(PDK_ROOT) \
-	-e PDKPATH=$(PDKPATH) \
 	-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
-	efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"
-
-
+	efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 checks/lvs_check/lvs.py --pdk_path $(PDK_ROOT)/$(PDK) --design_directory $(INPUT_DIRECTORY) --output_directory $(INPUT_DIRECTORY)/lvs --design_name $* --config_file $(INPUT_DIRECTORY)/lvs/$*/lvs_config.json"
 
 .PHONY: clean
 clean:

docs/source/index.rst

@@ -137,7 +137,7 @@ Starting your project
 
     *   You need to include your rtl/gl/gl+sdf files in ``verilog/includes/includes.<rtl/gl/gl+sdf>.caravel_user_project``
 
-        **NOTE:** You shouldn't include the files inside the verilog code
+      **NOTE:** You shouldn't include the files inside the verilog code
 
         .. code:: bash
 
@@ -174,7 +174,15 @@ Starting your project
 
             make caravel-sta
 
-        **NOTE:** To update timing scripts run ``make setup-timing-scripts``
+      **NOTE:** To update timing scripts run ``make setup-timing-scripts``
+
+#.  Run standalone LVS
+
+    .. code:: bash
+
+        make lvs-<macro_name> # macro is the name of the macro you want to run LVS on
+
+   **NOTE:** You have to create a new config file for each macro under ``lvs/<macro_name>/lvs_config.json``
 
 #.  Run the precheck locally 
 
@@ -471,6 +479,50 @@ To reproduce hardening this project, run the following:
 
 For more information on the openlane flow, check `README <https://github.com/The-OpenROAD-Project/OpenLane#readme>`__.
 
+Runing transistor level LVS
+============================
+
+For the design to pass precheck, a custom lvs configuration file for your design is needed, config file can be found under `lvs/<design_name>/lvs_config.json`
+
+The `lvs_config.json` files are a possibly hierarchical set of files to set parameters for device level LVS
+
+Required variables:
+- **TOP_SOURCE** : Top source cell name.
+- **TOP_LAYOUT** : Top layout cell name.
+- **LAYOUT_FILE** : Layout gds data file. 
+- **LVS_SPICE_FILES** : A list of spice files.
+- **LVS_VERILOG_FILES** : A list of verilog files. Note: files with child modules should be listed before parent modules. Not needed for purely analog designs.
+
+Files must be defined as a absolute path beginning with a shell variable such as `$PDK_ROOT` or `$UPRJ_ROOT`.
+
+Optional variable lists: 
+Hierarchical config files:
+- **INCLUDE_CONFIGS** : List of configuration files to read recursively.
+
+Extraction related. `*` may be used as a wild card character.
+- **EXTRACT_FLATGLOB** : List of cell names to flatten before extraction. 
+  Cells without text tend to work better if flattened.
+  Note: it is necessary to flatten all sub cells of any cells listed.
+- **EXTRACT_ABSTRACT** : List of cells to extract as abstract devices.
+  Normally, cells that do not contain any devices will be flattened during netlisting.
+  Using this variable can prevent unwanted flattening of empty cells.
+  This has no effect of cells that are flattened because of a small number of layers.
+  Internal connectivity is maintained (at least at the top level).
+
+LVS related. `*` may be used as a wild card character.
+- **LVS_FLATTEN** : List of cells to flatten before comparing,
+        Sometimes matching topologies with mismatched pins cause errors at a higher level.
+        Flattening these cells can yield a match.
+- **LVS_NOFLATTEN** : List of cells not to be flattened in case of a mismatch.
+        Lower level errors can propagate to the top of the chip resulting in long run times.
+        Specify cells here to prevent flattening. May still cause higher level problems if there are pin mismatches.
+- **LVS_IGNORE** : List of cells to ignore during LVS.
+        Cells ignored result in LVS ending with a warning.
+        Generally, should only be used when debugging and not on the final netlist.
+        Ignoring cells results in a non-zero return code.
+
+**NOTE**: Missing files and undefined variables result in fatal errors.
+
 Running MPW Precheck Locally
 =================================
 
@@ -493,6 +545,12 @@ Then, you can run the precheck by running
 
 This will run all the precheck checks on your project and will produce the logs under the ``checks`` directory.
 
+To disable running LVS/Soft/ERC connection checks:
+
+.. code:: bash
+
+   DISABLE_LVS=1 make run-precheck
+
 Running Timing Analysis on Existing Projects
 ========================================================
 

lvs/user_project_wrapper/lvs_config.json

@@ -0,0 +1,30 @@
+{
+	"TOP_SOURCE": "user_project_wrapper",
+	"TOP_LAYOUT": "$TOP_SOURCE",
+	"EXTRACT_FLATGLOB": [
+		""
+	],
+	"EXTRACT_ABSTRACT": [
+		"*__fill_*",
+		"*__fakediode_*",
+		"*__tapvpwrvgnd_*"
+	],
+	"LVS_FLATTEN": [
+		""
+	],
+	"LVS_NOFLATTEN": [
+		""
+	],
+	"LVS_IGNORE": [
+		""
+	],
+	"LVS_SPICE_FILES": [
+		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
+		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+	],
+	"LVS_VERILOG_FILES": [
+		"$UPRJ_ROOT/verilog/gl/user_proj_example.v",
+		"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
+	],
+	"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
+}

verilog/includes/includes.gl+sdf.caravel_user_project

@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
 // Caravel user project includes		
 $USER_PROJECT_VERILOG/gl/user_project_wrapper.v
 $USER_PROJECT_VERILOG/gl/user_proj_example.v

verilog/includes/includes.gl.caravel_user_project

@@ -1,3 +1,18 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
 # Caravel user project includes	     
 -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v    
 -v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v

verilog/includes/includes.rtl.caravel_user_project

@@ -1,3 +1,18 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v