core/vexriscv_smp add --hardware-breakpoints INT to allow hardware br…

…eakpoint on PC
enjoy-digital · Sep 20, 2023 · 3d956af · 3d956af
1 parent 7d73873
commit 3d956af
Showing 1 changed file with 6 additions and 1 deletion.
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -49,6 +49,7 @@ class VexRiscvSMP(CPU):
     expose_time          = False
     out_of_order_decoder = True
     privileged_debug     = False
+    hardware_breakpoints = 0
     wishbone_memory      = False
     wishbone_force_32b   = False
     with_fpu             = False
@@ -74,6 +75,7 @@ def args_fill(parser):
         cpu_group.add_argument("--without-out-of-order-decoder", action="store_true", help="Reduce area at cost of peripheral access speed")
         cpu_group.add_argument("--with-wishbone-memory",         action="store_true", help="Disable native LiteDRAM interface")
         cpu_group.add_argument("--with-privileged-debug",        action="store_true", help="Enable official RISC-V debug spec")
+        cpu_group.add_argument("--hardware-breakpoints",        default=1,           help="Number of hardware breapoints", type=int)
         cpu_group.add_argument("--wishbone-force-32b",           action="store_true", help="Force the wishbone bus to be 32 bits")
         cpu_group.add_argument("--with-fpu",                     action="store_true", help="Enable the F32/F64 FPU")
         cpu_group.add_argument("--cpu-per-fpu",                  default="4",         help="Maximal ratio between CPU count and FPU count. Will instanciate as many FPU as necessary.")
@@ -102,9 +104,10 @@ def args_read(args):
         if(args.dcache_ways):                  VexRiscvSMP.dcache_ways           = int(args.dcache_ways)
         if(args.icache_ways):                  VexRiscvSMP.icache_ways           = int(args.icache_ways)
         if(args.aes_instruction):              VexRiscvSMP.aes_instruction       = bool(args.aes_instruction)
-        if(args.expose_time):                  VexRiscvSMP.expose_time       = bool(args.expose_time)
+        if(args.expose_time):                  VexRiscvSMP.expose_time           = bool(args.expose_time)
         if(args.without_out_of_order_decoder): VexRiscvSMP.out_of_order_decoder  = False
         if(args.with_privileged_debug):        VexRiscvSMP.privileged_debug      = True
+        if(args.hardware_breakpoints):         VexRiscvSMP.hardware_breakpoints  = args.hardware_breakpoints
         if(args.with_wishbone_memory):         VexRiscvSMP.wishbone_memory       = True
         if(args.wishbone_force_32b):           VexRiscvSMP.wishbone_force_32b    = True
         if(args.with_fpu):
@@ -187,6 +190,7 @@ def generate_cluster_name():
         f"{'_Wf32' if VexRiscvSMP.wishbone_force_32b   else ''}" \
         f"{'_Fpu' + str(VexRiscvSMP.cpu_per_fpu)  if VexRiscvSMP.with_fpu else ''}" \
         f"{'_Pd'   if VexRiscvSMP.privileged_debug else ''}" \
+        f"{'_Hb' + str(VexRiscvSMP.hardware_breakpoints) if VexRiscvSMP.hardware_breakpoints > 0 else ''}" \
         f"{'_Rvc'  if VexRiscvSMP.with_rvc else ''}"
 
     # Default Configs Generation.
@@ -274,6 +278,7 @@ def generate_netlist():
         gen_args.append(f"--expose-time={VexRiscvSMP.expose_time}")
         gen_args.append(f"--out-of-order-decoder={VexRiscvSMP.out_of_order_decoder}")
         gen_args.append(f"--privileged-debug={VexRiscvSMP.privileged_debug}")
+        gen_args.append(f"--hardware-breakpoints={VexRiscvSMP.hardware_breakpoints}")
         gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}")
         if(VexRiscvSMP.wishbone_force_32b): gen_args.append(f"--wishbone-force-32b={VexRiscvSMP.wishbone_force_32b}")
         gen_args.append(f"--fpu={VexRiscvSMP.with_fpu}")