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xilinx/vivado: Fix issue with #1755.
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enjoy-digital committed Aug 31, 2023
1 parent ad924a5 commit 41357ab
Showing 1 changed file with 1 addition and 2 deletions.
3 changes: 1 addition & 2 deletions litex/build/xilinx/vivado.py
Original file line number Diff line number Diff line change
Expand Up @@ -170,9 +170,8 @@ def get_clk_type(clk):
True : "ports",
}[hasattr(clk, "port")]
for clk, [period, name] in sorted(self.clocks.items(), key=lambda x: x[0].duid):
clk_sig = self._vns.get_name(clk)
if name is None:
name = clk_sig
name = clk
self.platform.add_platform_command(
"create_clock -name {name} -period " + str(period) +
" [get_" + get_clk_type(clk) + " {clk}]", name=name, clk=clk)
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