CHANGES: Update.

enjoy-digital · Sep 1, 2023 · 57faa91 · 57faa91
1 parent f473261
commit 57faa91
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/CHANGES.md b/CHANGES.md
@@ -61,6 +61,9 @@
 	- soc/interconnect/stream      : Added pipe_valid/pipe_ready parameters to BufferizeEndpoints.
 	- soc/cores/clock              : Added initial GW5A support.
 	- build/efinix                 : Added initial EfinixDDROutput/Input and simplified IOs exclusion.
+	- soc/interconnect             : Improved DMA Bus to use the same Bus Standard than the CPU DMA Bus.
+	- liteeth/phy                  : Added Artix7 2500BASE-X PHY.
+	- liteeth/phy                  : Added Gowin Arora V RGMII PHY (GW5RGMII).
 
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