[RFC] litex_sim: move most code from main() to SimSoC() #1764
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josuah
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josuah
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Sep 3, 2023
| @@ -545,7 +542,7 @@ def pre_run_callback(vns): | |||
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| builder = Builder(soc, **parser.builder_argdict) | |||
| builder.build( | |||
| sim_config = sim_config, | |||
| sim_config = soc.sim_config, | |||
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Because sim_config needs to be passed to the builder but is not in main() anymore, SimSoC() exposes it as self.sim_config.
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This is a fix for this error:
$ xargs <overlay.config west build -p -b litex_vexriscv zephyr/samples/subsys/shell/shell_module -- -DDTC_OVERLAY_FILE="$PWD/overlay.dts"
[...]
-- Found devicetree overlay: /home/zephyr/overlay.dts
devicetree error: /home/zephyr/overlay.dts:49 (column 1): parse error: undefined node label 'sdcard_block2mem'
-- In: /home/zephyr/build/zephyr, command: /home/zephyr/.venv/bin/python3.11;/home/zephyr/zephyr/scripts/dts/gen_defines.py;--dts;/home/zephyr/build/zephyr/zephyr.dts.pre;--dtc-flags;'';--bindings-dirs;/home/zephyr/zephyr/dts/bindings;--header-out;/home/zephyr/build/zephyr/include/generated/devicetree_generated.h.new;--dts-out;/home/zephyr/build/zephyr/zephyr.dts.new;--edt-pickle-out;/home/zephyr/build/zephyr/edt.pickle;--vendor-prefixes;/home/zephyr/zephyr/dts/bindings/vendor-prefixes.txt
CMake Error at /home/zephyr/zephyr/cmake/modules/dts.cmake:276 (message):
gen_defines.py failed with return code: 1
Call Stack (most recent call first):
/home/zephyr/zephyr/cmake/modules/zephyr_default.cmake:115 (include)
/home/zephyr/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:66 (include)
/home/zephyr/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:92 (include_boilerplate)
CMakeLists.txt:4 (find_package)
-- Configuring incomplete, errors occurred!
FATAL ERROR: command exited with status 1: /usr/bin/cmake -DWEST_PYTHON=/home/zephyr/.venv/bin/python3.11 -B/home/zephyr/build -GNinja -DBOARD=litex_vexriscv -DDTC_OVERLAY_FILE=/home/zephyr/overlay.dts -DCONFIG_UART_LITEUART=y -DCONFIG_LITEX_TIMER=y -DCONFIG_ETH_LITEETH=n -DCONFIG_SPI_LITESPI=n -DCONFIG_SD_LITESD=n -DCONFIG_SD_LITESD=n -DCONFIG_SD_LITESD=n -DCONFIG_SD_LITESD=n -DCONFIG_SD_LITESD=n -DCONFIG_I2C_LITEX=n -DCONFIG_I2S_LITEX=n -DCONFIG_I2S_LITEX=n -DCONFIG_CLOCK_CONTROL_LITEX=n -DCONFIG_LITEX_CSR_DATA_WIDTH=32 -S/home/zephyr/zephyr/samples/subsys/shell/shell_module
$
This allows to execute a firmware loaded in the SPI flash. No support for partitions yet: this does not yet support cohabitating the bitstream and firmware yet, so the bitstream has to be loaded to CRAM directly for now (default for --load). This allows loading larger Zephyr examples, and was required to fit the shell on the Crosslink-NX board. See litex-hub/zephyr-on-litex-vexriscv#13
This aims to turn litex.tools.litex_sim.SimSoC into something useable as a litex_board.targets. The result is to reduce the amount of boilerplate code, and consider the simulator like a regular board, in hope to reduce hardware/simulation mismatch for Linux-on-LitexVexriscv, Zephyr-on-LitexVexriscv, etc.
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Required by litex-hub/zephyr-on-litex-vexriscv#18 I can change |
josuah
changed the title
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I am closing this to let Enjoy-Digital perform refactoring freely on the Zephyr-on-LiteX-Vexriscv, as well as Linux-on-LiteX-Vexriscv, which will might happen everywhere else before here. |
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I was on my way to bring support for the simulator on Zephyr-on-LitexVexriscv, then I saw this: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/sim.py#L70
This means that currently,
./make.pyhas nothing to do with./sim.py, and any pull request to./make.pyneeds maintainers to always update./sim.py... time-consuming for little added-value?So why not allow the simulator to be configured as a regular boards?
import litex.tools.litex_simSupersedes litex-hub/litex-boards#525