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fix: dead code warning on ARM code
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the whole cfg(not(test)) stuff on `impl Default for CacheEngine` meant
that rustc was complaining about `HostCacheEngine` and `readln_special`
were dead code when compiling unit tests. Fix this by refactoring the
code slightly to not use this cfg(not(test)) antipattern anymore.

Signed-off-by: Patrick Roy <[email protected]>
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roypat committed Dec 10, 2024
1 parent 6d145b1 commit 3009c51
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Showing 2 changed files with 41 additions and 23 deletions.
28 changes: 11 additions & 17 deletions src/vmm/src/arch/aarch64/cache_info.rs
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ pub(crate) enum CacheInfoError {
MissingOptionalAttr(String, CacheEntry),
}

struct CacheEngine {
pub struct CacheEngine {
store: Box<dyn CacheStore>,
}

Expand All @@ -49,9 +49,8 @@ struct HostCacheStore {
cache_dir: PathBuf,
}

#[cfg(not(test))]
impl Default for CacheEngine {
fn default() -> Self {
impl CacheEngine {
pub fn host() -> Self {
CacheEngine {
store: Box::new(HostCacheStore {
cache_dir: PathBuf::from("/sys/devices/system/cpu/cpu0/cache"),
Expand Down Expand Up @@ -281,16 +280,16 @@ fn append_cache_level(
pub(crate) fn read_cache_config(
cache_l1: &mut Vec<CacheEntry>,
cache_non_l1: &mut Vec<CacheEntry>,
cache_engine: CacheEngine,
) -> Result<(), CacheInfoError> {
// It is used to make sure we log warnings for missing files only for one level because
// if an attribute is missing for a level for sure it will be missing for other levels too.
// Also without this mechanism we would be logging the warnings for each level which pollutes
// a lot the logs.
let mut logged_missing_attr = false;
let engine = CacheEngine::default();

for index in 0..=MAX_CACHE_LEVEL {
match CacheEntry::from_index(index, engine.store.as_ref()) {
match CacheEntry::from_index(index, cache_engine.store.as_ref()) {
Ok(cache) => {
append_cache_level(cache_l1, cache_non_l1, cache);
}
Expand Down Expand Up @@ -326,16 +325,6 @@ mod tests {
dummy_fs: HashMap<String, String>,
}

impl Default for CacheEngine {
fn default() -> Self {
CacheEngine {
store: Box::new(MockCacheStore {
dummy_fs: create_default_store(),
}),
}
}
}

impl CacheEngine {
fn new(map: &HashMap<String, String>) -> Self {
CacheEngine {
Expand Down Expand Up @@ -570,7 +559,12 @@ mod tests {
let mut l1_caches: Vec<CacheEntry> = Vec::new();
let mut non_l1_caches: Vec<CacheEntry> = Vec::new();
// We use sysfs for extracting the cache information.
read_cache_config(&mut l1_caches, &mut non_l1_caches).unwrap();
read_cache_config(
&mut l1_caches,
&mut non_l1_caches,
CacheEngine::new(&create_default_store()),
)
.unwrap();
assert_eq!(l1_caches.len(), 2);
assert_eq!(l1_caches.len(), 2);
}
Expand Down
36 changes: 30 additions & 6 deletions src/vmm/src/arch/aarch64/fdt.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ use vm_fdt::{Error as VmFdtError, FdtWriter, FdtWriterNode};
use vm_memory::GuestMemoryError;

use super::super::{DeviceType, InitrdConfig};
use super::cache_info::{read_cache_config, CacheEntry};
use super::cache_info::{read_cache_config, CacheEngine, CacheEntry};
use super::gic::GICDevice;
use crate::devices::acpi::vmgenid::{VmGenId, VMGENID_MEM_SIZE};
use crate::vstate::memory::{Address, GuestMemory, GuestMemoryMmap};
Expand Down Expand Up @@ -116,7 +116,7 @@ fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> Result<(), FdtEr
let mut l1_caches: Vec<CacheEntry> = Vec::new();
let mut non_l1_caches: Vec<CacheEntry> = Vec::new();
// We use sysfs for extracting the cache information.
read_cache_config(&mut l1_caches, &mut non_l1_caches)
read_cache_config(&mut l1_caches, &mut non_l1_caches, CacheEngine::host())
.map_err(|err| FdtError::ReadCacheInfo(err.to_string()))?;

// See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/arm/cpus.yaml.
Expand Down Expand Up @@ -594,8 +594,20 @@ mod tests {
buf.extend_from_slice(saved_dtb_bytes);

set_size(&mut buf, pos, val);
let original_fdt = device_tree::DeviceTree::load(&buf).unwrap();
let generated_fdt = device_tree::DeviceTree::load(&current_dtb_bytes).unwrap();
let mut original_fdt = device_tree::DeviceTree::load(&buf).unwrap();
let mut generated_fdt = device_tree::DeviceTree::load(&current_dtb_bytes).unwrap();

// The cache thingies depends on the instance type, since they're read from the host.
// Explicitly ignore them
original_fdt
.root
.props
.retain(|(key, _)| !key.contains("cache"));
generated_fdt
.root
.props
.retain(|(key, _)| !key.contains("cache"));

assert_eq!(
format!("{:?}", original_fdt),
format!("{:?}", generated_fdt)
Expand Down Expand Up @@ -656,8 +668,20 @@ mod tests {
buf.extend_from_slice(saved_dtb_bytes);

set_size(&mut buf, pos, val);
let original_fdt = device_tree::DeviceTree::load(&buf).unwrap();
let generated_fdt = device_tree::DeviceTree::load(&current_dtb_bytes).unwrap();
let mut original_fdt = device_tree::DeviceTree::load(&buf).unwrap();
let mut generated_fdt = device_tree::DeviceTree::load(&current_dtb_bytes).unwrap();

// The cache thingies depends on the instance type, since they're read from the host.
// Explicitly ignore them
original_fdt
.root
.props
.retain(|(key, _)| !key.contains("cache"));
generated_fdt
.root
.props
.retain(|(key, _)| !key.contains("cache"));

assert_eq!(
format!("{:?}", original_fdt),
format!("{:?}", generated_fdt)
Expand Down

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