Overhaul "Pixel FIFO" article into "Rendering Internals"

Also avoid describing SameBoy internals, instead relying on it when
otherwise corroborated, or on schematics and/or test ROMs when possible.

Restructure the article to describe behavior more than components, especially
in a way that is more friendly to someone not knowing what all the components
are about.

Add a diagram, too, and move the mode timing diagram to the STAT article, where
it belongs just as well, but where it will be more visible and thus more useful.

custom/style.css

@@ -21,9 +21,9 @@ html {
 
 body {
   font-family: "Inter";
-  /* Enable some font features for Inter (https://rsms.me/inter/#features/calt) */
+  /* Enable some font features for Inter (https://rsms.me/inter/#features) */
   font-feature-settings: "ss01", /* Alternate (Open) digits */ "ss02",
-    /* Disambiguation gliphs */ "case";
+    /* Disambiguation glyphs */ "case", /* No contextual alternatives (e.g. 3x9 → 3×9) */ "calt" 0;
   /* Case alternates */
   letter-spacing: -0.005em;
   /* equals -0.5% */
@@ -100,6 +100,13 @@ code {
   margin: 25px 0px 25px 0px;
 }
 
+/* Classes for custom table styling */
+
+table.compact th {
+    padding: 3px 5px;
+}
+
+
 /* Global CSS variables */
 
 :root {

src/Power_Up_Sequence.md

@@ -106,7 +106,7 @@ It is speculated that this may be debug remnants.
 
 The boot ROM is responsible for the automatic colorization of monochrome-only games when run on a GBC.
 
-When in DMG compatibility mode, the [CGB palettes](<#LCD Color Palettes (CGB only)>) are still being used: the background uses BG palette 0 (likely because the entire [attribute map](<#BG Map Attributes (CGB Mode only)>) is set to all zeros), and objects use OBJ palette 0 or 1 depending on bit 4 of [their attribute](<#Byte 3 — Attributes/Flags>).
+When in DMG compatibility mode, the [CGB palettes](<#LCD Color Palettes (CGB only)>) are still being used: the background uses BG palette 0 (likely because the entire [attribute map](<#BG Map attributes (CGB Mode only)>) is set to all zeros), and objects use OBJ palette 0 or 1 depending on bit 4 of [their attribute](<#Byte 3 — Attributes/Flags>).
 [`BGP`, `OBP0`, and `OBP1`](<#LCD Monochrome Palettes>) actually index into the CGB palettes instead of the DMG's shades of grey.
 
 The boot ROM picks a compatibility palette using an ID computed using the following algorithm:

src/STAT.md

@@ -2,7 +2,7 @@
 
 ::: tip TERMINOLOGY
 
-A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-state on DMG or on CGB single-speed mode or 2 T-states on CGB double-speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Pixel FIFO>).
+A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-state on DMG or on CGB single-speed mode or 2 T-states on CGB double-speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Rendering Internals>).
 
 :::
 
@@ -49,12 +49,7 @@ every 456 dots. Scanlines 144 through 153 are mode 1.
 
 The following sequence is typical when the display is enabled:
 
-```
-Mode 2  2_____2_____2_____2_____2_____2___________________2____
-Mode 3  _33____33____33____33____33____33__________________3___
-Mode 0  ___000___000___000___000___000___000________________000
-Mode 1  ____________________________________11111111111111_____
-```
+{{#include imgs/ppu_modes_timing.svg:2:}}
 
 When the PPU is accessing some video-related memory, that memory is inaccessible
 to the CPU: writes are ignored, and reads return garbage values (usually $FF).
@@ -70,11 +65,11 @@ Mode | Action                                                      | Duration
   0  | Nothing (HBlank)                                            | 85 to 208 dots, depending on previous mode 3 duration | VRAM, OAM, CGB palettes
   1  | Nothing (VBlank)                                            | 4560 dots (10 scanlines)                              | VRAM, OAM, CGB palettes
 
-## Properties of STAT modes
+## STAT modes
 
 Unlike most game consoles, the Game Boy can pause the dot clock briefly,
 making Mode 3 longer and Mode 0 shorter. It routinely takes a 6 to 11 dot
-break to fetch an OBJ's tile between background tile pattern fetches.
+break to fetch an OBJ's tile between background tile fetches.
 On DMG and GBC in DMG mode, mid-scanline writes to [`BGP`](<#FF47 — BGP (Non-CGB Mode only): BG palette data>)
 allow observing this behavior, as the delay from drawing an OBJ shifts the
 write's effect to the left by that many dots.

src/SUMMARY.md

@@ -24,7 +24,7 @@
   - [LCD Status Registers](./STAT.md)
   - [Scrolling](./Scrolling.md)
   - [Palettes](./Palettes.md)
-  - [Pixel FIFO](./pixel_fifo.md)
+  - [Rendering internals](./Rendering_Internals.md)
 - [Audio](./Audio.md)
   - [Audio Registers](./Audio_Registers.md)
   - [Audio Details](./Audio_details.md)

src/Scrolling.md

@@ -33,7 +33,7 @@ scanline.
 
 ### Scrolling
 
-The scroll registers are re-read on each [tile fetch](<#Get Tile>), except for the low 3 bits of SCX, which are only read at the beginning of the scanline (for the initial shifting of pixels).
+The scroll registers are re-read on each [tile fetch](<#Get tile ID>), except for the low 3 bits of SCX, which are only read at the beginning of the scanline (for the initial shifting of pixels).
 
 All models before the CGB-D read the Y coordinate once for each bitplane (so a very precisely timed SCY write allows "desyncing" them), but CGB-D and later use the same Y coordinate for both no matter what.
 

src/Tile_Maps.md

@@ -5,10 +5,9 @@ The Game Boy contains two 32×32 tile maps in VRAM at
 the memory areas `$9800-$9BFF` and `$9C00-$9FFF`. Any of these maps can be used to
 display the Background or the Window.
 
-## Tile Indexes
+## Tile indices
 
-Each tile map contains the 1-byte indexes of the
-tiles to be displayed.
+Each tile map contains the 1-byte indices of the tiles to be displayed.
 
 Tiles are obtained from the Tile Data Table using either of the two
 addressing modes (described in [VRAM Tile Data](<#VRAM Tile Data>)), which
@@ -17,7 +16,7 @@ can be selected via [the LCDC register](<#FF40 — LCDC: LCD control>).
 Since one tile has 8×8 pixels, each map holds a 256×256 pixels picture.
 Only 160×144 of those pixels are displayed on the LCD at any given time.
 
-## BG Map Attributes (CGB Mode only)
+## BG Map attributes (CGB Mode only)
 
 In CGB Mode, an additional map of 32×32 bytes is stored in VRAM Bank 1
 (each byte defines attributes for the corresponding tile-number map