Fix SPI async busy wait

[andelf]

See-also #33

only async write is fixed.

To get END irq work:

• DMA Bust must 1 for SPI
• DMA transize must be actual_size + 1 for SPI

UPDATE

After some investigation:

• Only special values trigger this bug
• SPI END interrupt state is marked (INTRST.ENDINT is set), SPI interrupt is enabled(both peripheral and PLIC). But irq handler is never reached

[andelf]

To use Async SPI:

bind_interrupts!(struct Irqs {
    SPI1 => hal::spi::InterruptHandler<peripherals::SPI1>;
});

let mut config = hal::spi::Config::default();
config.frequency = Hertz::mhz(2);
let spi = hal::spi::Spi::new_txonly(r.spi1, r.sclk, r.mosi, Irqs, r.dma_ch0, config);