Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Switch to hpm-riscv-rt #41

Merged
merged 4 commits into from
Nov 24, 2024
Merged

Switch to hpm-riscv-rt #41

merged 4 commits into from
Nov 24, 2024

Conversation

andelf
Copy link
Collaborator

@andelf andelf commented Nov 24, 2024

As planned. The hpm-riscv-rt crate is now ready for use: https://github.com/hpmicro-rs/hpm-riscv-rt

Major differences vs riscv-rt:

  • Use Andes V5's vectored interrupt
  • Fits for HPMicro's 32-bit RISC-V cores: memory split, etc.
  • Work with hpm-metapac (interrupt tables)

@andelf andelf force-pushed the refactor/use-hpm-riscv-rt branch from d939f0c to 5537789 Compare November 24, 2024 16:07
@andelf andelf merged commit 7b46c3d into master Nov 24, 2024
1 check passed
@andelf andelf deleted the refactor/use-hpm-riscv-rt branch November 24, 2024 18:00
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant