Push 2023 09 23

doc/ENVVAR_README.md

@@ -9,3 +9,5 @@
 `PCM_PRINT_TOPOLOGY=1` : print detailed CPU topology
 
 `PCM_KEEP_NMI_WATCHDOG=1` : don't disable NMI watchdog (reducing the core metrics set)
+
+`PCM_NO_MAIN_EXCEPTION_HANDLER=1` :  don't catch exceptions in the main function of pcm tools (a debugging option)

doc/PCM_RAW_README.md

@@ -77,6 +77,35 @@ pcicfg/config=0xe20,config1=0x180,config2=0x0,width=32,name=CHANERR_INT
 ```
 From: https://www.intel.la/content/dam/www/public/us/en/documents/datasheets/xeon-e7-v2-datasheet-vol-2.pdf
 
+MMIO Registers:
+
+```
+mmio/config=<device_id>,config1=<offset>,config2=<static_or_freerun>,config3=<membar_bits1>[,config4=<membar_bits2>],width=<width>[,name=<NAME>]
+```
+
+The MEMBAR is computed by logically ORing the result of membar_bits1 and membar_bits1 computation described below (PCICFG read + bit extraction and shift). The final MMIO register address = MEMBAR + offset.
+
+* width: register width in bits (16,32,64) 
+* dev_id: Intel PCI device id where the membar address registers are located
+* membar_bits1: mmioBase register bits to compute membar (base address)
+  - bits 0-15 : PCICFG register offset to read membar1 bits
+  - bits 16-23: source position of membar bits in the PCICFG register 
+  - bits 24-31: number of bits
+  - bits 32-39: destination bit position in the membar
+* membar_bits2: mmioBase register bits to compute membar (base address), can be zero if only membar_bits1 is sufficient for locating the register.
+  - bits 0-15 : PCICFG register offset to read membar2 bits
+  - bits 16-23: source position of membar bits in the PCICFG register 
+  - bits 24-31: number of bits
+  - bits 32-39: destination bit position in the membar
+* offset: offset of the MMIO register relative to the membar
+* static_or_freerun: same syntax as for MSR registers
+
+Example (Icelake server iMC PMON MMIO register read):
+
+```
+mmio/config=0x3451,config1=0x22808,config2=1,config3=0x171D0000D0,config4=0x0c0b0000d8,width=64
+```
+
 --------------------------------------------------------------------------------
 Collecting Events By Names From Event Lists (https://github.com/intel/perfmon/)
 --------------------------------------------------------------------------------

src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json

@@ -64,7 +64,11 @@
             "Threshold":   {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0},
             "Filter0":     {"Config": 1, "Position": 0, "Width": 64, "DefaultValue": 0},
             "TID":         {"Config": 1, "Position": 0,  "Width": 6, "DefaultValue": 0},
-            "Filter1":     {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59}
+            "State":       {"Config": 1, "Position": 17, "Width": 7, "DefaultValue": 0},
+            "Filter1":     {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59},
+            "OPC":         {"Config": 2, "Position": 20, "Width": 9, "DefaultValue": 0},
+            "NC":          {"Config": 2, "Position": 30, "Width": 1, "DefaultValue": 0},
+            "ISOC":        {"Config": 2, "Position": 31, "Width": 1, "DefaultValue": 0}
         }
     },
     "imc" : {
@@ -75,6 +79,21 @@
             "Threshold":   {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}
         }
     },
+    "ha" : {
+        "programmable" : {
+            "EventCode":   {"Config": 0, "Position": 0, "Width": 8},
+            "UMask":       {"Config": 0, "Position": 8, "Width": 8},
+            "EdgeDetect":  {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0},
+            "Threshold":   {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}
+        }
+    },
+    "pcu" : {
+        "programmable" : {
+            "EventCode":   {"Config": 0, "Position": 0, "Width": 8},
+            "UMask":       {"Config": 0, "Position": 8, "Width": 8},
+            "EdgeDetect":  {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}
+        }
+    },
     "xpi" : {
         "__comment" :  "this is for UPI LL and QPI LL uncore PMUs",
         "programmable" : {

src/PMURegisterDeclarations/GenuineIntel-6-55-4.json

@@ -100,6 +100,13 @@
             "Threshold":   {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}
         }
     },
+    "pcu" : {
+        "programmable" : {
+            "EventCode":   {"Config": 0, "Position": 0, "Width": 8},
+            "UMask":       {"Config": 0, "Position": 8, "Width": 8},
+            "EdgeDetect":  {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}
+        }
+    },
     "irp" : {
         "programmable" : {
             "EventCode":   {"Config": 0, "Position": 0, "Width": 8},

src/PMURegisterDeclarations/GenuineIntel-6-55-7.json

@@ -100,6 +100,13 @@
             "Threshold":   {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}
         }
     },
+    "pcu" : {
+        "programmable" : {
+            "EventCode":   {"Config": 0, "Position": 0, "Width": 8},
+            "UMask":       {"Config": 0, "Position": 8, "Width": 8},
+            "EdgeDetect":  {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}
+        }
+    },
     "irp" : {
         "programmable" : {
             "EventCode":   {"Config": 0, "Position": 0, "Width": 8},

src/PMURegisterDeclarations/GenuineIntel-6-55-B.json

@@ -100,6 +100,13 @@
             "Threshold":   {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}
         }
     },
+    "pcu" : {
+        "programmable" : {
+            "EventCode":   {"Config": 0, "Position": 0, "Width": 8},
+            "UMask":       {"Config": 0, "Position": 8, "Width": 8},
+            "EdgeDetect":  {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}
+        }
+    },
     "irp" : {
         "programmable" : {
             "EventCode":   {"Config": 0, "Position": 0, "Width": 8},

src/cpucounters.cpp

@@ -5435,6 +5435,7 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile
     threadMSRConfig = RawPMUConfig{};
     packageMSRConfig = RawPMUConfig{};
     pcicfgConfig = RawPMUConfig{};
+    mmioConfig = RawPMUConfig{};
     RawPMUConfigs curPMUConfigs = curPMUConfigs_;
     constexpr auto globalRegPos = 0ULL;
     PCM::ExtendedCustomCoreEventDescription conf;
@@ -5540,9 +5541,9 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile
         {
             continue;
         }
-        if (events.programmable.size() > ServerUncoreCounterState::maxCounters)
+        if (events.programmable.size() > ServerUncoreCounterState::maxCounters && isRegisterEvent(type) == false)
         {
-            std::cerr << "ERROR: trying to program " << events.programmable.size() << " core PMU counters, which exceeds the max num possible (" << ServerUncoreCounterState::maxCounters << ").";
+            std::cerr << "ERROR: trying to program " << events.programmable.size() << " uncore PMU counters, which exceeds the max num possible (" << ServerUncoreCounterState::maxCounters << ").";
             return PCM::UnknownError;
         }
         uint32 events32[ServerUncoreCounterState::maxCounters] = { 0,0,0,0,0,0,0,0 };
@@ -5573,6 +5574,13 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile
                 uncore->programIMC(events32);
             }
         }
+        else if (type == "ha")
+        {
+            for (auto& uncore : serverUncorePMUs)
+            {
+                uncore->programHA(events32);
+            }
+        }
         else if (type == "m2m")
         {
             for (auto& uncore : serverUncorePMUs)
@@ -5649,6 +5657,54 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile
             addLocations(pcicfgConfig.programmable);
             addLocations(pcicfgConfig.fixed);
         }
+        else if (type == "mmio")
+        {
+            mmioConfig = pmuConfig.second;
+            auto addLocations = [this](const std::vector<RawEventConfig>& configs) {
+                for (const auto& c : configs)
+                {
+                    if (MMIORegisterLocations.find(c.first) == MMIORegisterLocations.end())
+                    {
+                        // add locations
+                        std::vector<MMIORegisterEncoding> locations;
+                        const auto deviceID = c.first[MMIOEventPosition::deviceID];
+                        forAllIntelDevices([&locations, &deviceID, &c](const uint32 group, const uint32 bus, const uint32 device, const uint32 function, const uint32 device_id)
+                            {
+                                if (deviceID == device_id && PciHandleType::exists(group, bus, device, function))
+                                {
+                                    PciHandleType pciHandle(group, bus, device, function);
+                                    auto computeBarOffset = [&pciHandle](uint64 membarBits) -> size_t
+                                    {
+                                        if (membarBits)
+                                        {
+                                            const auto destPos = extract_bits(membarBits, 32, 39);
+                                            const auto numBits = extract_bits(membarBits, 24, 31);
+                                            const auto srcPos = extract_bits(membarBits, 16, 23);
+                                            const auto pcicfgOffset = extract_bits(membarBits, 0, 15);
+                                            uint32 memBarOffset = 0;
+                                            pciHandle.read32(pcicfgOffset, &memBarOffset);
+                                            return size_t(extract_bits_ui(memBarOffset, srcPos, srcPos + numBits - 1)) << destPos;
+                                        }
+                                        return 0;
+                                    };
+
+                                    size_t memBar = computeBarOffset(c.first[MMIOEventPosition::membar_bits1])
+                                        | computeBarOffset(c.first[MMIOEventPosition::membar_bits2]);
+
+                                    assert(memBar);
+
+                                    const size_t addr = memBar + c.first[MMIOEventPosition::offset];
+                                    // MMIORange shared ptr (handle), offset
+                                    locations.push_back(MMIORegisterEncoding{ std::make_shared<MMIORange>(addr & ~4095ULL, 4096), (uint32) (addr & 4095ULL) });
+                                }
+                            });
+                        MMIORegisterLocations[c.first] = locations;
+                    }
+                }
+            };
+            addLocations(mmioConfig.programmable);
+            addLocations(mmioConfig.fixed);
+        }
         else if (type == "cxlcm")
         {
             programCXLCM(events64);
@@ -6070,6 +6126,50 @@ void PCM::readPCICFGRegisters(SystemCounterState& systemState)
     }
 }
 
+void PCM::readMMIORegisters(SystemCounterState& systemState)
+{
+    auto read = [this, &systemState](const RawEventConfig& cfg) {
+        const RawEventEncoding& reEnc = cfg.first;
+        systemState.MMIOValues[reEnc].clear();
+        for (auto& reg : MMIORegisterLocations[reEnc])
+        {
+            const auto width = reEnc[MMIOEventPosition::width];
+            auto& h = reg.first;
+            const auto& offset = reg.second;
+            if (h.get())
+            {
+                uint64 value = ~0ULL;
+                uint32 value32 = 0;
+                switch (width)
+                {
+                case 16:
+                    value32 = h->read32(offset);
+                    value = (uint64)extract_bits_ui(value32, 0, 15);
+                    break;
+                case 32:
+                    value32 = h->read32(offset);
+                    value = (uint64)value32;
+                    break;
+                case 64:
+                    value = h->read64(offset);
+                    break;
+                default:
+                    std::cerr << "ERROR: Unsupported width " << width << " for mmio register " << cfg.second << "\n";
+                }
+                systemState.MMIOValues[reEnc].push_back(value);
+            }
+        }
+    };
+    for (const auto& cfg : mmioConfig.programmable)
+    {
+        read(cfg);
+    }
+    for (const auto& cfg : mmioConfig.fixed)
+    {
+        read(cfg);
+    }
+}
+
 void PCM::readQPICounters(SystemCounterState & result)
 {
         // read QPI counters
@@ -6274,6 +6374,7 @@ void PCM::getAllCounterStates(SystemCounterState & systemState, std::vector<Sock
     {
         readQPICounters(systemState);
         readPCICFGRegisters(systemState);
+        readMMIORegisters(systemState);
     }
 
     for (auto & ar : asyncCoreResults)
@@ -6438,6 +6539,9 @@ ServerUncoreCounterState PCM::getServerUncoreCounterState(uint32 socket)
       assert(controller < result.M2MCounter.size());
       for (uint32 cnt = 0; cnt < ServerUncoreCounterState::maxCounters; ++cnt)
           result.M2MCounter[controller][cnt] = serverUncorePMUs[socket]->getM2MCounter(controller, cnt);
+      assert(controller < result.HACounter.size());
+      for (uint32 cnt = 0; cnt < ServerUncoreCounterState::maxCounters; ++cnt)
+          result.HACounter[controller][cnt] = serverUncorePMUs[socket]->getHACounter(controller, cnt);
     }
         serverUncorePMUs[socket]->unfreezeCounters();
     }
@@ -8489,6 +8593,11 @@ uint64 ServerUncorePMUs::getPMUCounter(std::vector<UncorePMU> & pmu, const uint3
     return result;
 }
 
+uint64 ServerUncorePMUs::getHACounter(uint32 id, uint32 counter)
+{
+    return getPMUCounter(haPMUs, id, counter);
+}
+
 uint64 ServerUncorePMUs::getMCCounter(uint32 channel, uint32 counter)
 {
     return getPMUCounter(imcPMUs, channel, counter);
@@ -8907,7 +9016,7 @@ uint32 PCM::getMaxNumOfCBoxes() const
     switch (cpu_model)
     {
     case SPR:
-        {
+        try {
             PciHandleType * h = getDeviceHandle(PCM_INTEL_PCI_VENDOR_ID, 0x325b);
             if (h)
             {
@@ -8919,6 +9028,10 @@ uint32 PCM::getMaxNumOfCBoxes() const
                 delete h;
             }
         }
+        catch (std::exception& e)
+        {
+            std::cerr << "Warning: reading the number of CHA from PCICFG register has failed: " << e.what() << "\n";
+        }
         break;
     case KNL:
     case SKX: