Add tests for using the read request function.

- Resolve bit order in read/write requests and responses
- Add the embedded-hal-mock library

drivers/Cargo.toml

@@ -27,5 +27,12 @@ allegro-motor-derive = { version = "0.1.0", path = "../derive" }
 # It has a bug in v1.0.0, but bilge permissively allows v1.0.0 as the minimum dependency.
 # The statement here is to restrict proc-macro-error to v1.0.4 at minimum.
 proc-macro-error = "1.0.4"
-embedded-hal = "1.0.0-rc.1"
+
+# TODO: update embedded-hal to 1.0.0-rc.1
+# embedded-hal-mock is currently unstable on its 1-alpha branch.
+# That branch currently has an out-of-date dependency on embedded-hal 1.0.0-alpha.10.
+embedded-hal = "1.0.0-alpha.10"
 arbitrary-int = "1.2.6"
+
+[dev-dependencies]
+embedded-hal-mock = { git = "https://github.com/dbrgn/embedded-hal-mock", branch = "1-alpha" }

drivers/src/a4910/driver.rs

@@ -25,11 +25,11 @@ where
     }
 
     fn read_request(&self, reg: Register) -> u16 {
-        ReadRequest::new(reg.into(), false).into()
+        ReadRequest::new(false, reg.into()).into()
     }
 
     fn write_request(&self, reg: Register) -> u16 {
-        WriteRequest::new(reg.into(), true, self.regs[reg].value().into()).into()
+        WriteRequest::new(self.regs[reg].value().into(), true, reg.into()).into()
     }
 
     fn read_response(&mut self, reg: Register, msg: u16) {
@@ -41,3 +41,30 @@ where
         self.status = WriteResponse::from(msg);
     }
 }
+
+
+mod tests {
+    #[test]
+    fn test_spi_derive() {
+        use super::*;
+        use embedded_hal_mock::spi::{Mock, Transaction};
+
+        let expected_transfers = [
+            Transaction::transfer(vec![1, 2], vec![3, 4])
+        ];
+        let spi_device = Mock::new(&expected_transfers);
+
+        let a4910 = A4910::new(spi_device);
+
+        assert_eq!(a4910.read_request(Register::Config0), 0b00_0_0000000000000);
+        assert_eq!(a4910.read_request(Register::Config1), 0b01_0_0000000000000);
+
+        // assert_eq!(c1.write_request(), 0b01_1_1_1_00_0_0_0100000);
+
+        // assert_eq!(c1.read_request(), 0b01_0_0000000000000);
+
+        // c1.read_response(0b00_0_0_0_11_1_1_1011111);
+        // assert_eq!(c1.vt(), u7::new(0b1011111).into());
+    }
+
+}

drivers/src/a4910/io.rs

@@ -7,25 +7,25 @@ use super::regs::diagnostic::{DiagnosticData, DiagnosticHeader};
 #[bitsize(16)]
 #[derive(DebugBits, DefaultBits, PartialEq, FromBits)]
 pub struct ReadRequest {
-    addr: u2,
-    write_read: bool,
     reserved: u13,
+    write_read: bool,
+    addr: u2,
 }
 
 #[bitsize(16)]
 #[derive(DebugBits, DefaultBits, PartialEq, FromBits)]
 pub struct ReadResponse {
-    pub status: DiagnosticHeader,
-    write_read: bool,
     pub register: u13,
+    write_read: bool,
+    pub status: DiagnosticHeader,
 }
 
 #[bitsize(16)]
 #[derive(DebugBits, DefaultBits, PartialEq, FromBits)]
 pub struct WriteRequest {
-    addr: u2,
-    write_read: bool,
     register: u13,
+    write_read: bool,
+    addr: u2,
 }
 
 #[bitsize(16)]

drivers/src/lib.rs

@@ -1,6 +1,6 @@
 //! Host-side drivers for Allegro Microsystems motor controller integrated circuits
 
-#![no_std]
+#![cfg_attr(not(test), no_std)]
 #![feature(trait_alias)]
 
 pub mod a4910;