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selftests/powerpc: Fixup clobbers for TM tests
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commit a02cbc7 upstream.

Some of our TM (Transactional Memory) tests, list "r1" (the stack
pointer) as a clobbered register.

GCC >= 9 doesn't accept this, and the build breaks:

  ptrace-tm-spd-tar.c: In function 'tm_spd_tar':
  ptrace-tm-spd-tar.c:31:2: error: listing the stack pointer register 'r1' in a clobber list is deprecated [-Werror=deprecated]
     31 |  asm __volatile__(
        |  ^~~
  ptrace-tm-spd-tar.c:31:2: note: the value of the stack pointer after an 'asm' statement must be the same as it was before the statement

We do have some fairly large inline asm blocks in these tests, and
some of them do change the value of r1. However they should all return
to C with the value in r1 restored, so I think it's legitimate to say
r1 is not clobbered.

As Segher points out, the r1 clobbers may have been added because of
the use of `or 1,1,1`, however that doesn't actually clobber r1.

Segher also points out that some of these tests do clobber LR, because
they call functions, and that is not listed in the clobbers, so add
that where appropriate.

Signed-off-by: Michael Ellerman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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mpe committed Sep 17, 2024
1 parent f4c9e14 commit 8bac5fe
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Showing 4 changed files with 6 additions and 6 deletions.
2 changes: 1 addition & 1 deletion tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ void tm_spd_tar(void)
[sprn_texasr]"i"(SPRN_TEXASR), [tar_1]"i"(TAR_1),
[dscr_1]"i"(DSCR_1), [tar_2]"i"(TAR_2), [dscr_2]"i"(DSCR_2),
[tar_3]"i"(TAR_3), [dscr_3]"i"(DSCR_3)
: "memory", "r0", "r1", "r3", "r4", "r5", "r6"
: "memory", "r0", "r3", "r4", "r5", "r6", "lr"
);

/* TM failed, analyse */
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4 changes: 2 additions & 2 deletions tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
Original file line number Diff line number Diff line change
Expand Up @@ -78,8 +78,8 @@ void tm_spd_vsx(void)
"3: ;"
: [res] "=r" (result), [texasr] "=r" (texasr)
: [sprn_texasr] "i" (SPRN_TEXASR)
: "memory", "r0", "r1", "r3", "r4",
"r7", "r8", "r9", "r10", "r11"
: "memory", "r0", "r3", "r4",
"r7", "r8", "r9", "r10", "r11", "lr"
);

if (result) {
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2 changes: 1 addition & 1 deletion tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ void tm_tar(void)
[sprn_ppr]"i"(SPRN_PPR), [sprn_texasr]"i"(SPRN_TEXASR),
[tar_1]"i"(TAR_1), [dscr_1]"i"(DSCR_1), [tar_2]"i"(TAR_2),
[dscr_2]"i"(DSCR_2), [cptr1] "b" (&cptr[1])
: "memory", "r0", "r1", "r3", "r4", "r5", "r6"
: "memory", "r0", "r3", "r4", "r5", "r6"
);

/* TM failed, analyse */
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4 changes: 2 additions & 2 deletions tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
Original file line number Diff line number Diff line change
Expand Up @@ -66,8 +66,8 @@ void tm_vsx(void)
"3: ;"
: [res] "=r" (result), [texasr] "=r" (texasr)
: [sprn_texasr] "i" (SPRN_TEXASR), [cptr1] "b" (&cptr[1])
: "memory", "r0", "r1", "r3", "r4",
"r7", "r8", "r9", "r10", "r11"
: "memory", "r0", "r3", "r4",
"r7", "r8", "r9", "r10", "r11", "lr"
);

if (result) {
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