First version of an FPGA binary oscilloscope

.gitignore

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+*~
+.*.swp
+work/
+_xmsgs/
+iseconfig/

Makefile

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+# Device 0: XC3S100E - FPGA (Device ID: f5045093)
+# Device 1: XCF02S - PROM (Device ID: 11c10093)
+DEVICE_NUM=0
+
+bit/oscilloscope.bit:
+	cp work/oscilloscope.bit bit/
+
+up: bit/oscilloscope.bit
+	djtgcfg prog \
+		-d Basys2 \
+		-i $(DEVICE_NUM) \
+		--file bit/oscilloscope.bit
+

README

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+An FPGA-based binary oscilloscope for 1280x1024 @ 60hz VGA monitor.
+
+Target device: Basys2, Spartan3E 100K
+
+In order to upload programming file to Basys2 device:
+  o make up

ipcore_dir/blk_mem_gen_readme.txt

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+                    Core name: Xilinx LogiCORE Block Memory Generator
+                    Version: 6.1
+                    Release Date: March 01 2011
+
+
+================================================================================
+
+This document contains the following sections: 
+
+1. Introduction
+2. New Features
+3. Supported Devices
+4. Resolved Issues
+5. Known Issues
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+1. INTRODUCTION
+
+For the IP installation instructions for this core,please go to:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory 
+Generator v6.1 solution. For the latest core updates, see the product page at:
+
+  http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
+
+
+2. NEW FEATURES  
+
+   - ISE 13.1 Software support
+   - Virtex-7 and Kintex-7 device support
+   - AXI4/AXI4-Lite interface support for Virtex-6 and Spartan-6 devices
+
+3. SUPPORTED DEVICES
+
+   The following device families are supported by the core for this release.
+
+   - Virtex-7
+   - Kintex-7
+
+   - Virtex-6 XC CXT/LXT/SXT/HXT
+   - Virtex-6 XQ LXT/SXT                                                       
+   - Virtex-6 -1L XC LXT/SXT 
+
+   - Spartan-6 XC LX/LXT 
+   - Spartan-6 XA 
+   - Spartan-6 XQ LX/LXT       
+   - Spartan-6 -1L XC LX
+
+   - Virtex-5 XC LX/LXT/SXT/TXT/FXT
+   - Virtex-5 XQ LX/ LXT/SXT/FXT                                                
+
+   - Virtex-4 XC LX/SX/FX
+   - Virtex-4 XQ LX/SX/FX
+   - Virtex-4 XQR LX/SX/FX                                                  
+
+   - Spartan-3 XC
+   - Spartan-3 XA                                                                      
+   - Spartan-3A XC 3A / 3A DSP / 3AN DSP                                      
+   - Spartan-3A XA 3A / 3A DSP                                                    
+   - Spartan-3E XC                                        
+   - Spartan-3E XA 
+
+4. RESOLVED ISSUES 
+   The following issues are resolved in Block Memory Generator v6.1: 
+
+   a. "Fill remaining memory locations" - option disabled in GUI
+
+      - Version fixed : 6.1
+      1.Core does not allow the customer to use the "remaining memory locations" option.
+        Solution: "Fill remaining memory locations" - option enbaled in GUI
+      - CR 575015
+      - AR 37944
+
+5. KNOWN ISSUES 
+
+   The following are known issues for v6.1 of this core at time of release:
+
+   a. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
+      Workaround: Generate two shallower FIFOs and pass the appropriate address 
+      lines to implement the FIFO of the required depth
+      - CR587481
+      - AR 39718
+
+   b. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
+      Solution: The user must review the possible scenarios that causes the collission and revise 
+      their design to avoid those situations.
+      - CR588505
+
+      Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with 
+            Write Mode = Read First in conjunction with asynchronous clocking
+
+   c. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+
+   d. Core does not generate for large memories. Depending on the
+      machine the ISE CORE Generator software runs on, the maximum size of the memory that
+      can be generated will vary.  For example, a Dual Pentium-4 server 
+      with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+      - CR 415768
+      - AR 24034
+
+   e. Out-of-range address input can cause the core to generate X's on the DOUT bus
+      - AR 23744
+
+   f. When the IP core is generated for Spartan-6 devices, the core does not combine 
+      two adjacent 9k BRAMs into one 18K BRAM.
+      - CR 526429
+
+   The most recent information, including known issues, workarounds, and resolutions for 
+   this version is provided in the IP Release Notes User Guide located at
+
+        www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+6. TECHNICAL SUPPORT 
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+10/29/2010  Xilinx, Inc.  5.2          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
+07/30/2010  Xilinx, Inc.  5.1          ISE 13.0.1 support
+07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
+03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
+12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
+                                       Device support; Automotive Spartan 3A
+                                       DSP device support
+09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
+06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
+04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
+09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
+03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
+10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
+07/2007     Xilinx, Inc.  2.5          Revised to v2.5
+04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
+02/2007     Xilinx, Inc.  2.4          Revised to v2.4
+11/2006     Xilinx, Inc.  2.3          Revised to v2.3
+09/2006     Xilinx, Inc.  2.2          Revised to v2.2
+06/2006     Xilinx, Inc.  2.1          Revised to v2.1
+01/2006     Xilinx, Inc.  1.1          Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+ (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
+
+ This file contains confidential and proprietary information
+ of Xilinx, Inc. and is protected under U.S. and
+ international copyright and other intellectual property
+ laws.
+
+ DISCLAIMER
+ This disclaimer is not a license and does not grant any
+ rights to the materials distributed herewith. Except as
+ otherwise provided in a valid license issued to you by
+ Xilinx, and to the maximum extent permitted by applicable
+ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ (2) Xilinx shall not be liable (whether in contract or tort,
+ including negligence, or under any other theory of
+ liability) for any loss or damage of any kind or nature
+ related to, arising under or in connection with these
+ materials, including for any direct, or any indirect,
+ special, incidental, or consequential loss or damage
+ (including loss of data, profits, goodwill, or any type of
+ loss or damage suffered as a result of any action brought
+ by a third party) even if such damage or loss was
+ reasonably foreseeable or Xilinx had been advised of the
+ possibility of the same.
+
+ CRITICAL APPLICATIONS
+ Xilinx products are not designed or intended to be fail-
+ safe, or for use in any application requiring fail-safe
+ performance, such as life-support or safety devices or
+ systems, Class III medical devices, nuclear facilities,
+ applications related to the deployment of airbags, or any
+ other applications that could lead to death, personal
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+ (individually and collectively, "Critical
+ Applications"). Customer assumes the sole risk and
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+ regulations governing limitations on product liability.
+
+ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ PART OF THIS FILE AT ALL TIMES.
+

ipcore_dir/char_rom_memory.asy

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+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 char_rom_memory
+RECTANGLE Normal 32 32 544 1376
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName addra[13:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName clka
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName douta[0:0]
+PINATTR Polarity OUT
+

ipcore_dir/char_rom_memory.gise

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+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="char_rom_memory.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="char_rom_memory.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="char_rom_memory.vho" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>