- 👋 Hi, I’m @namnguyen269
- 👀 I’m interested in ...
- 🌱 I’m currently learning ...
- 💞️ I’m looking to collaborate on ...
- 📫 How to reach me ...
🎯
Focusing
-
HUST
- Ha Noi. Viet Nam
-
05:44
(UTC +07:00)
Popular repositories Loading
-
-
-
edabk_SoC_SNN
edabk_SoC_SNN PublicIntegrate IP neural network into RISCV SoC based on Litex framework
Verilog
-
-
OpenLane
OpenLane PublicForked from The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Python
-
caravel_user_project
caravel_user_project Public templateForked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io
Verilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.