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* Readme: file update * Remove master example - tet implementation * Readme Update * REFACTOR: added atribute week to master data interface functionsa * HW_tests: remove compilation errors * HW_test: queue functionality improved due the integration test fail Queue was overritten it's objects in some cases. Pointers in queue was not cleared after poping object from queue Two main issues listed above was fixed + unit test was adopted to new functionality. additionally queue can hold same ammount of objects as queue lenght * HW_test: enable systic irq * Modbus: added week atrubute to modbus data interface * HW_test: -> added interface for update modbus timout timer, fix compilation errors (arm gcc compiler) add reset of resp msg len when sending or repeating req changes in checking modbus_ms buffer to send (new queue implementation) * HW_test: GREEN * Examples: added master app example * REFACTOR: modbus data interface refactor * GREEN: added new test -> GivenTimeoutTimerSetToSomeValueWhenUpdateModbusTimeoutTimerCalledThenModbusMasterTimeoutTimerDecBy1 * GREEN: added new test -> GivenTimeoutTimerSetTo0WhenUpdateModbusTimeoutTimerCalledThenModbusMasterTimeoutTimerEqual0 * GREEN: added new test -> GivenModbusMasterInRTUmodeInitAndAnyRequestTransmitingWhenWhloeRequestIsTransmittedThenResponseTimeoutIsEnabled * example implementation: modbus_driver update * clang-frmat check * Readme Update * Readme update
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Original file line number | Diff line number | Diff line change |
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@@ -1 +1,9 @@ | ||
#include "stm32g070xx.h" | ||
#include "stm32g070xx.h" | ||
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#define SLAVE_ADDRES_EXAMPLE_NODE 0x01 | ||
#define READ_COIL_ADR 1 | ||
#define READ_HREG_ADR 1 | ||
#define WRITE_COIL_ADR 0 | ||
#define WRITE_HREG_ADR 0 | ||
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#define UPDATE_INTERVAL_MS 300 |
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84 changes: 84 additions & 0 deletions
84
examples/STM32G070RB_MODBUS_MASTER/Core/Src/modbus_master_data_interface.c
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/** | ||
* @file modbus_master_data_interface.c | ||
* @author niwciu ([email protected]) | ||
* @brief | ||
* @version 0.0.1 | ||
* @date 2024-08-04 | ||
* | ||
* @copyright Copyright (c) 2024 | ||
* | ||
*/ | ||
#include "modbus_master_data_interface.h" | ||
#include "main.h" | ||
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extern modbus_coil_disin_t readed_coil; | ||
extern modbus_reg_t readed_hreg; | ||
extern modbus_coil_disin_t prev_coil_val; | ||
extern modbus_reg_t prev_hreg_val; | ||
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void modbus_master_coil_read(modbus_device_ID_t slave_adr, modbus_adr_t data_adr, modbus_coil_disin_t disin_val) | ||
{ | ||
if( SLAVE_ADDRES_EXAMPLE_NODE == slave_adr) | ||
{ | ||
if(READ_COIL_ADR == data_adr) | ||
{ | ||
readed_coil= disin_val; | ||
} | ||
} | ||
} | ||
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void modbus_master_hreg_read(modbus_device_ID_t slave_adr, modbus_adr_t data_adr, modbus_reg_t inreg_val) | ||
{ | ||
if (SLAVE_ADDRES_EXAMPLE_NODE == slave_adr) | ||
{ | ||
if (READ_HREG_ADR == data_adr) | ||
{ | ||
readed_hreg = inreg_val; | ||
} | ||
} | ||
} | ||
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// void modbus_master_coil_write(modbus_device_ID_t slave_adr, modbus_adr_t data_adr, modbus_data_qty_t coil_qty) | ||
// { | ||
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// } | ||
void modbus_master_coil_exception(const modbus_read_data_t *resp_data) | ||
{ | ||
prev_coil_val = 0; | ||
} | ||
// void modbus_master_disin_read(modbus_device_ID_t slave_adr, modbus_adr_t data_adr, modbus_coil_disin_t disin_val) | ||
// { | ||
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// } | ||
// void modbus_master_disin_exception(const modbus_read_data_t *resp_data) | ||
// { | ||
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// } | ||
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// void modbus_master_hreg_write(modbus_device_ID_t slave_adr, modbus_adr_t data_adr, modbus_data_qty_t reg_qty) | ||
// { | ||
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// } | ||
void modbus_master_hreg_exception(const modbus_read_data_t *resp_data) | ||
{ | ||
prev_hreg_val = 0; | ||
} | ||
void modbus_master_inreg_read(modbus_device_ID_t slave_adr, modbus_adr_t data_adr, modbus_reg_t inreg_val) | ||
{ | ||
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} | ||
// void modbus_master_inreg_exception(const modbus_read_data_t *resp_data) | ||
// { | ||
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// } | ||
void modbus_master_data_timeout_error(const modbus_master_error_report_t *timeout_error_rep) | ||
{ | ||
prev_coil_val = 0; | ||
prev_hreg_val = 666; | ||
} | ||
void modbus_master_communication_error(const modbus_master_error_report_t *communication_error_rep) | ||
{ | ||
prev_coil_val = 0; | ||
prev_hreg_val = 777; | ||
} |
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