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Merge tag 'pull-aspeed-20240709' of https://github.com/legoater/qemu …
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…into staging

aspeed queue:

* support AST2700 network

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# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
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# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20240709' of https://github.com/legoater/qemu:
  machine_aspeed.py: update to test network for AST2700
  machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for AST2700
  hw/block: m25p80: support quad mode for w25q01jvq
  aspeed/soc: set dma64 property for AST2700 ftgmac100
  hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits
  hw/net:ftgmac100: introduce TX and RX ring base address high registers to support 64 bits
  hw/net:ftgmac100: update ring base address to 64 bits
  hw/net:ftgmac100: update memory region size to 64KB

Signed-off-by: Richard Henderson <[email protected]>
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@rth7680
rth7680 committed Jul 9, 2024
2 parents 4a3eceb + d847ea7 commit 59084fe
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Showing 5 changed files with 162 additions and 33 deletions.
3 changes: 3 additions & 0 deletions hw/arm/aspeed_ast27x0.c
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Original file line number Diff line number Diff line change
Expand Up @@ -552,9 +552,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}

/* Net */
for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
&error_abort);
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true,
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
return;
}
Expand Down
16 changes: 16 additions & 0 deletions hw/block/m25p80.c
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Original file line number Diff line number Diff line change
Expand Up @@ -416,6 +416,7 @@ typedef enum {
/*
* Micron: 0x35 - enable QPI
* Spansion: 0x35 - read control register
* Winbond: 0x35 - quad enable
*/
RDCR_EQIO = 0x35,
RSTQIO = 0xf5,
Expand Down Expand Up @@ -798,6 +799,11 @@ static void complete_collecting_data(Flash *s)
s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
}
break;
case MAN_WINBOND:
if (s->len > 1) {
s->quad_enable = !!(s->data[1] & 0x02);
}
break;
default:
break;
}
Expand Down Expand Up @@ -1254,6 +1260,10 @@ static void decode_new_cmd(Flash *s, uint32_t value)
s->needed_bytes = 2;
s->state = STATE_COLLECTING_VAR_LEN_DATA;
break;
case MAN_WINBOND:
s->needed_bytes = 2;
s->state = STATE_COLLECTING_VAR_LEN_DATA;
break;
default:
s->needed_bytes = 1;
s->state = STATE_COLLECTING_DATA;
Expand Down Expand Up @@ -1431,6 +1441,12 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case MAN_MACRONIX:
s->quad_enable = true;
break;
case MAN_WINBOND:
s->data[0] = (!!s->quad_enable) << 1;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
default:
break;
}
Expand Down
147 changes: 124 additions & 23 deletions hw/net/ftgmac100.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,16 @@
#define FTGMAC100_PHYDATA 0x64
#define FTGMAC100_FCR 0x68

/*
* FTGMAC100 registers high
*
* values below are offset by - FTGMAC100_REG_HIGH_OFFSET from datasheet
* because its memory region is start at FTGMAC100_REG_HIGH_OFFSET
*/
#define FTGMAC100_NPTXR_BADR_HIGH (0x17C - FTGMAC100_REG_HIGH_OFFSET)
#define FTGMAC100_HPTXR_BADR_HIGH (0x184 - FTGMAC100_REG_HIGH_OFFSET)
#define FTGMAC100_RXR_BADR_HIGH (0x18C - FTGMAC100_REG_HIGH_OFFSET)

/*
* Interrupt status register & interrupt enable register
*/
Expand Down Expand Up @@ -165,6 +175,8 @@
#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
#define FTGMAC100_TXDES1_TXIC (1 << 31)

#define FTGMAC100_TXDES2_TXBUF_BADR_HI(x) (((x) >> 16) & 0x7)

/*
* Receive descriptor
*/
Expand Down Expand Up @@ -198,13 +210,15 @@
#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)

#define FTGMAC100_RXDES2_RXBUF_BADR_HI(x) (((x) >> 16) & 0x7)

/*
* Receive and transmit Buffer Descriptor
*/
typedef struct {
uint32_t des0;
uint32_t des1;
uint32_t des2; /* not used by HW */
uint32_t des2; /* used by HW 64 bits DMA */
uint32_t des3;
} FTGMAC100Desc;

Expand Down Expand Up @@ -515,12 +529,13 @@ static int ftgmac100_insert_vlan(FTGMAC100State *s, int frame_size,
return frame_size;
}

static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
uint32_t tx_descriptor)
static void ftgmac100_do_tx(FTGMAC100State *s, uint64_t tx_ring,
uint64_t tx_descriptor)
{
int frame_size = 0;
uint8_t *ptr = s->frame;
uint32_t addr = tx_descriptor;
uint64_t addr = tx_descriptor;
uint64_t buf_addr = 0;
uint32_t flags = 0;

while (1) {
Expand Down Expand Up @@ -559,7 +574,12 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
len = sizeof(s->frame) - frame_size;
}

if (dma_memory_read(&address_space_memory, bd.des3,
buf_addr = bd.des3;
if (s->dma64) {
buf_addr = deposit64(buf_addr, 32, 32,
FTGMAC100_TXDES2_TXBUF_BADR_HI(bd.des2));
}
if (dma_memory_read(&address_space_memory, buf_addr,
ptr, len, MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
__func__, bd.des3);
Expand Down Expand Up @@ -726,9 +746,9 @@ static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
case FTGMAC100_MATH1:
return s->math[1];
case FTGMAC100_RXR_BADR:
return s->rx_ring;
return extract64(s->rx_ring, 0, 32);
case FTGMAC100_NPTXR_BADR:
return s->tx_ring;
return extract64(s->tx_ring, 0, 32);
case FTGMAC100_ITC:
return s->itc;
case FTGMAC100_DBLAC:
Expand Down Expand Up @@ -799,9 +819,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
HWADDR_PRIx "\n", __func__, value);
return;
}

s->rx_ring = value;
s->rx_descriptor = s->rx_ring;
s->rx_ring = deposit64(s->rx_ring, 0, 32, value);
s->rx_descriptor = deposit64(s->rx_descriptor, 0, 32, value);
break;

case FTGMAC100_RBSR: /* DMA buffer size */
Expand All @@ -814,8 +833,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
HWADDR_PRIx "\n", __func__, value);
return;
}
s->tx_ring = value;
s->tx_descriptor = s->tx_ring;
s->tx_ring = deposit64(s->tx_ring, 0, 32, value);
s->tx_descriptor = deposit64(s->tx_descriptor, 0, 32, value);
break;

case FTGMAC100_NPTXPD: /* Trigger transmit */
Expand Down Expand Up @@ -914,6 +933,60 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
ftgmac100_update_irq(s);
}

static uint64_t ftgmac100_high_read(void *opaque, hwaddr addr, unsigned size)
{
FTGMAC100State *s = FTGMAC100(opaque);
uint64_t val = 0;

switch (addr) {
case FTGMAC100_NPTXR_BADR_HIGH:
val = extract64(s->tx_ring, 32, 32);
break;
case FTGMAC100_HPTXR_BADR_HIGH:
/* High Priority Transmit Ring Base High Address */
qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
case FTGMAC100_RXR_BADR_HIGH:
val = extract64(s->rx_ring, 32, 32);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
}

return val;
}

static void ftgmac100_high_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
FTGMAC100State *s = FTGMAC100(opaque);

switch (addr) {
case FTGMAC100_NPTXR_BADR_HIGH:
s->tx_ring = deposit64(s->tx_ring, 32, 32, value);
s->tx_descriptor = deposit64(s->tx_descriptor, 32, 32, value);
break;
case FTGMAC100_HPTXR_BADR_HIGH:
/* High Priority Transmit Ring Base High Address */
qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
case FTGMAC100_RXR_BADR_HIGH:
s->rx_ring = deposit64(s->rx_ring, 32, 32, value);
s->rx_descriptor = deposit64(s->rx_descriptor, 32, 32, value);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
}

ftgmac100_update_irq(s);
}

static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
{
unsigned mcast_idx;
Expand Down Expand Up @@ -957,9 +1030,9 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
FTGMAC100Desc bd;
uint32_t flags = 0;
uint32_t addr;
uint64_t addr;
uint32_t crc;
uint32_t buf_addr;
uint64_t buf_addr = 0;
uint8_t *crc_ptr;
uint32_t buf_len;
size_t size = len;
Expand Down Expand Up @@ -1024,7 +1097,12 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
if (size < 4) {
buf_len += size - 4;
}

buf_addr = bd.des3;
if (s->dma64) {
buf_addr = deposit64(buf_addr, 32, 32,
FTGMAC100_RXDES2_RXBUF_BADR_HI(bd.des2));
}
if (first && proto == ETH_P_VLAN && buf_len >= 18) {
bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;

Expand Down Expand Up @@ -1078,6 +1156,14 @@ static const MemoryRegionOps ftgmac100_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};

static const MemoryRegionOps ftgmac100_high_ops = {
.read = ftgmac100_high_read,
.write = ftgmac100_high_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
.endianness = DEVICE_LITTLE_ENDIAN,
};

static void ftgmac100_cleanup(NetClientState *nc)
{
FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
Expand Down Expand Up @@ -1107,9 +1193,23 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
}

memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
TYPE_FTGMAC100, 0x2000);
sysbus_init_mmio(sbd, &s->iomem);
memory_region_init(&s->iomem_container, OBJECT(s),
TYPE_FTGMAC100 ".container", FTGMAC100_MEM_SIZE);
sysbus_init_mmio(sbd, &s->iomem_container);

memory_region_init_io(&s->iomem, OBJECT(s), &ftgmac100_ops, s,
TYPE_FTGMAC100 ".regs", FTGMAC100_REG_MEM_SIZE);
memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);

if (s->dma64) {
memory_region_init_io(&s->iomem_high, OBJECT(s), &ftgmac100_high_ops,
s, TYPE_FTGMAC100 ".regs.high",
FTGMAC100_REG_HIGH_MEM_SIZE);
memory_region_add_subregion(&s->iomem_container,
FTGMAC100_REG_HIGH_OFFSET,
&s->iomem_high);
}

sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);

Expand All @@ -1121,18 +1221,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)

static const VMStateDescription vmstate_ftgmac100 = {
.name = TYPE_FTGMAC100,
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(irq_state, FTGMAC100State),
VMSTATE_UINT32(isr, FTGMAC100State),
VMSTATE_UINT32(ier, FTGMAC100State),
VMSTATE_UINT32(rx_enabled, FTGMAC100State),
VMSTATE_UINT32(rx_ring, FTGMAC100State),
VMSTATE_UINT32(rbsr, FTGMAC100State),
VMSTATE_UINT32(tx_ring, FTGMAC100State),
VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
VMSTATE_UINT32(itc, FTGMAC100State),
VMSTATE_UINT32(aptcr, FTGMAC100State),
Expand All @@ -1151,13 +1247,18 @@ static const VMStateDescription vmstate_ftgmac100 = {
VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
VMSTATE_UINT64(rx_ring, FTGMAC100State),
VMSTATE_UINT64(tx_ring, FTGMAC100State),
VMSTATE_UINT64(rx_descriptor, FTGMAC100State),
VMSTATE_UINT64(tx_descriptor, FTGMAC100State),
VMSTATE_END_OF_LIST()
}
};

static Property ftgmac100_properties[] = {
DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
DEFINE_PROP_BOOL("dma64", FTGMAC100State, dma64, false),
DEFINE_PROP_END_OF_LIST(),
};

Expand Down
17 changes: 12 additions & 5 deletions include/hw/net/ftgmac100.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,11 @@
#define TYPE_FTGMAC100 "ftgmac100"
OBJECT_DECLARE_SIMPLE_TYPE(FTGMAC100State, FTGMAC100)

#define FTGMAC100_MEM_SIZE 0x1000
#define FTGMAC100_REG_MEM_SIZE 0x100
#define FTGMAC100_REG_HIGH_MEM_SIZE 0x100
#define FTGMAC100_REG_HIGH_OFFSET 0x100

#include "hw/sysbus.h"
#include "net/net.h"

Expand All @@ -30,18 +35,16 @@ struct FTGMAC100State {
NICState *nic;
NICConf conf;
qemu_irq irq;
MemoryRegion iomem_container;
MemoryRegion iomem;
MemoryRegion iomem_high;

uint8_t frame[FTGMAC100_MAX_FRAME_SIZE];

uint32_t irq_state;
uint32_t isr;
uint32_t ier;
uint32_t rx_enabled;
uint32_t rx_ring;
uint32_t rx_descriptor;
uint32_t tx_ring;
uint32_t tx_descriptor;
uint32_t math[2];
uint32_t rbsr;
uint32_t itc;
Expand All @@ -54,7 +57,10 @@ struct FTGMAC100State {
uint32_t phycr;
uint32_t phydata;
uint32_t fcr;

uint64_t rx_ring;
uint64_t rx_descriptor;
uint64_t tx_ring;
uint64_t tx_descriptor;

uint32_t phy_status;
uint32_t phy_control;
Expand All @@ -65,6 +71,7 @@ struct FTGMAC100State {
bool aspeed;
uint32_t txdes0_edotr;
uint32_t rxdes0_edorr;
bool dma64;
};

#define TYPE_ASPEED_MII "aspeed-mmi"
Expand Down
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