Multicluster MemPool

.clang-format-ignore

@@ -4,6 +4,7 @@
 
 # Exclude files from formatting requirement
 # External dependencies
+*/software/runtime/control_registers.h
 */software/runtime/encoding.h
 */software/riscv-tests
 */toolchain

.github/workflows/ci.yml

@@ -239,6 +239,20 @@ jobs:
         make -C hardware src/bootrom.sv
         git diff --exit-code
 
+  check-control-registers:
+    runs-on: ubuntu-20.04
+    steps:
+    - uses: actions/checkout@v4
+    - name: Install Python requirements
+      run: pip install -r python-requirements.txt
+    - name: Build Control Registers
+      run: |
+        git submodule update --init --recursive -- hardware/deps/register_interface
+        git apply hardware/deps/patches/register_interface.patch
+        make -C hardware/src/control_registers clean
+        make -C hardware/src/control_registers all
+        git diff --ignore-submodules=dirty --exit-code
+
   check-opcodes:
     runs-on: ubuntu-20.04
     steps:

.gitlab/.gitlab-ci.yml

@@ -128,6 +128,13 @@ check-bootrom:
     - make -C hardware src/bootrom.sv
     - git diff --exit-code
 
+check-control-registers:
+  stage: test
+  script:
+    - make -C hardware/src/control_registers clean
+    - make -C hardware/src/control_registers all
+    - git diff --exit-code
+
 check-opcodes:
   stage: test
   script:

Bender.yml

@@ -35,6 +35,8 @@ sources:
   - hardware/src/address_scrambler.sv
   - hardware/src/axi2mem.sv
   - hardware/src/bootrom.sv
+  - hardware/src/control_registers/control_registers_reg_pkg.sv
+  - hardware/src/control_registers/control_registers_reg_top.sv
   # Level 1
   - hardware/src/mempool_tile.sv
   # Level 2

CHANGELOG.md

@@ -11,6 +11,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Add `apb` dependency of version 0.2.4
 - Add support for the `FENCE` instruction
 - Add support for DRAMsys5.0 co-simulation
+- Add support for atomics in L2
+- Add support for a multi-cluster MemPool
 
 ### Changes
 - Add physical feasible TeraPool configuration with SubGroup hierarchy.
@@ -34,6 +36,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Update `register_interface` to 0.4.3
 - Updated Halide to version 15
 - Move instruction cache into its own dependency
+- Use automatically generated control registers
 
 ### Fixed
 - Fix type issue in `snitch_addr_demux`

config/config.mk

@@ -21,6 +21,9 @@ ifndef config
 endif
 include $(MEMPOOL_DIR)/config/$(config).mk
 
+# Number of clusters
+num_clusters ?= 1
+
 #############################
 ##  Address configuration  ##
 #############################

config/mempool.mk

@@ -30,9 +30,12 @@ axi_hier_radix ?= 17
 # Number of AXI masters per group
 axi_masters_per_group ?= 1
 
+# Numer of AXI masters for all clusters
+axi_masters_all_clusters ?= 4
+
 # Number of DMA backends in each group
 dmas_per_group ?= 1 # Brust Length = 16
 
 # L2 Banks/Channels
 l2_size  ?= 4194304  # 400000
-l2_banks ?= 4
+l2_banks ?= 4

config/minpool.mk

@@ -39,9 +39,12 @@ axi_hier_radix ?= 2
 # Number of AXI masters per group
 axi_masters_per_group ?= 1
 
+# Numer of AXI masters for all clusters
+axi_masters_all_clusters ?= 4
+
 # Number of DMA backends in each group
 dmas_per_group ?= 1 # Brust Length = 16
 
 # L2 Banks/Channels
 l2_size  ?= 4194304  # 400000
-l2_banks ?= 4
+l2_banks ?= 4

config/multipool.mk

@@ -0,0 +1,49 @@
+# Copyright 2021 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Author: Samuel Riedel, ETH Zurich
+
+###############
+##  MemPool  ##
+###############
+
+# Number of cores
+num_cores ?= 64
+
+# Number of groups
+num_groups ?= 16
+
+# Number of clusters
+num_clusters ?= 4
+
+# Number of cores per MemPool tile
+num_cores_per_tile ?= 4
+
+# L1 scratchpad banking factor
+banking_factor ?= 4
+
+# Radix for hierarchical AXI interconnect
+axi_hier_radix ?= 20
+
+# Number of AXI masters per group
+axi_masters_per_group ?= 1
+
+
+#########################
+##  AXI configuration  ##
+#########################
+# AXI bus data width (in bits)
+axi_data_width ?= 512
+
+# Read-only cache line width in AXI interconnect (in bits)
+ro_line_width ?= 512
+
+# Number of DMA backends in each group
+dmas_per_group ?= 1
+
+# Radix for hierarchical AXI interconnect
+axi_hier_radix ?= 2
+
+# Number of AXI masters per group
+axi_masters_per_group ?= 1

config/systolic.mk

@@ -28,6 +28,9 @@ axi_hier_radix ?= 20
 # Number of AXI masters per group
 axi_masters_per_group ?= 1
 
+# Numer of AXI masters for all clusters
+axi_masters_all_clusters ?= 4
+
 # Size of sequential memory per core (in bytes)
 # (must be a power of two)
 seq_mem_size ?= 1024

config/terapool.mk

@@ -40,9 +40,12 @@ axi_hier_radix ?= 9
 # Number of AXI masters per group
 axi_masters_per_group ?= 4
 
+# Numer of AXI masters for all clusters
+axi_masters_all_clusters ?= 16
+
 # Number of DMA backends in each group
 dmas_per_group ?= 4 # Brust Length = 16
 
 # L2 Banks/Channels
 l2_banks = 16
-l2_size  ?= 16777216 # 1000000
+l2_size  ?= 16777216 # 1000000

hardware/Makefile

@@ -113,6 +113,7 @@ vlog_defs += -DNUM_CORES=$(num_cores)
 vlog_defs += -DNUM_CORES_PER_TILE=$(num_cores_per_tile)
 vlog_defs += -DNUM_DIVSQRT_PER_TILE=$(num_divsqrt_per_tile)
 vlog_defs += -DNUM_GROUPS=$(num_groups)
+vlog_defs += -DNUM_CLUSTERS=$(num_clusters)
 vlog_defs += -DBANKING_FACTOR=$(banking_factor)
 vlog_defs += -DL2_BASE=32\'d$(l2_base)
 vlog_defs += -DL2_SIZE=32\'d$(l2_size)
@@ -131,6 +132,7 @@ vlog_defs += -DRO_LINE_WIDTH=$(ro_line_width)
 vlog_defs += -DDMAS_PER_GROUP=$(dmas_per_group)
 vlog_defs += -DAXI_HIER_RADIX=$(axi_hier_radix)
 vlog_defs += -DAXI_MASTERS_PER_GROUP=$(axi_masters_per_group)
+vlog_defs += -DAXI_MASTERS_ALL_CLUSTERS=$(axi_masters_all_clusters)
 # Systolic configurations
 vlog_defs += -DSEQ_MEM_SIZE=$(seq_mem_size)
 vlog_defs += -DXQUEUE_SIZE=$(xqueue_size)
@@ -413,6 +415,10 @@ src/bootrom.sv: $(MEMPOOL_DIR)/software/runtime/bootrom.img $(config_mk) Makefil
 $(MEMPOOL_DIR)/software/runtime/bootrom.img:
 	make -C $(MEMPOOL_DIR)/software runtime/bootrom.img
 
+# Control Registers
+src/control_registers/control_registers_reg_top.sv: src/control_registers/control_registers.hjson
+	make -C src/control_registers all
+
 # Clean targets
 .PHONY: clean clean-dasm clean-trace update_opcodes
 

hardware/deps/idma/src/frontends/mempool/mempool_dma.sv

@@ -11,6 +11,7 @@ module mempool_dma #(
   parameter int unsigned AddrWidth   = 32,
   parameter int unsigned DataWidth   = 32,
   parameter int unsigned NumBackends = 1,
+  parameter int unsigned DmaReportID = 0,
   /// AXI4+ATOP request struct definition.
   parameter type         axi_lite_req_t = logic,
   /// AXI4+ATOP response struct definition.
@@ -137,13 +138,35 @@ module mempool_dma #(
   assign dma_id_o = '0;
 
   // pragma translate_off
+  integer poll;
   integer cycle;
   integer transfer;
   integer size;
   integer f;
   string str;
 
   /* verilator lint_off BLKSEQ */
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      poll = 0;
+    end else begin
+      if (valid_o && ready_i) begin
+        $timeformat(-9, 0, " ns", 0);
+        $display("[DMA %d] Launch %t", DmaReportID, $time);
+        poll = 0;
+      end
+      if (trans_complete_i) begin
+        $timeformat(-9, 0, " ns", 0);
+        $display("[DMA %d] Complete %t", DmaReportID, $time);
+      end
+      if (config_req_i.ar_valid && config_res_o.ar_ready && poll == 0) begin
+        $timeformat(-9, 0, " ns", 0);
+        $display("[DMA %d] Poll %t", DmaReportID, $time);
+        poll = 1;
+      end
+    end
+  end
+
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       cycle = 0;

hardware/deps/patches/register_interface.patch

@@ -0,0 +1,98 @@
+diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl
+index 1c5520a..77619d9 100644
+--- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl
++++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl
+@@ -1,6 +1,6 @@
+-// Copyright lowRISC contributors.
+-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+-// SPDX-License-Identifier: Apache-2.0
++// Copyright 2024 ETH Zurich and University of Bologna.
++// Solderpad Hardware License, Version 0.51, see LICENSE for details.
++// SPDX-License-Identifier: SHL-0.51
+ //
+ // Register Package auto-generated by `reggen` containing data structure
+ <%
+@@ -344,4 +344,3 @@ ${reg_data_for_iface(iface_name, iface_desc, for_iface, rb)}\
+ % endfor
+
+ endpackage
+-
+diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
+index bfab87f..2b2764e 100644
+--- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
++++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
+@@ -1,6 +1,6 @@
+-// Copyright lowRISC contributors.
+-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+-// SPDX-License-Identifier: Apache-2.0
++// Copyright 2024 ETH Zurich and University of Bologna.
++// Solderpad Hardware License, Version 0.51, see LICENSE for details.
++// SPDX-License-Identifier: SHL-0.51
+ //
+ // Register Top module auto-generated by `reggen`
+ <%
+@@ -534,6 +534,7 @@ ${rdata_gen(f, r.name.lower() + "_" + f.name.lower())}\
+ endmodule
+
+ % if use_reg_iface:
++/* verilator lint_off DECLFILENAME */
+ module ${mod_name}_intf
+ #(
+   parameter int AW = ${addr_width},
+@@ -568,7 +569,7 @@ module ${mod_name}_intf
+
+   reg_bus_req_t s_reg_req;
+   reg_bus_rsp_t s_reg_rsp;
+-  
++
+   // Assign SV interface to structs
+   `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
+   `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
+@@ -580,9 +581,9 @@ module ${mod_name}_intf
+     `REG_BUS_ASSIGN_TO_REQ(s_reg_win_req[i], regbus_win_mst[i])
+     `REG_BUS_ASSIGN_FROM_RSP(regbus_win_mst[i], s_reg_win_rsp[i])
+   end
+-  
++
+ % endif
+-  
++
+
+   ${mod_name} #(
+     .reg_req_t(reg_bus_req_t),
+@@ -605,11 +606,10 @@ module ${mod_name}_intf
+ % endif
+     .devmode_i
+   );
+-  
+-endmodule
+
++endmodule
++/* verilator lint_on DECLFILENAME */
+ % endif
+-
+ <%def name="str_bits_sv(bits)">\
+ % if bits.msb != bits.lsb:
+ ${bits.msb}:${bits.lsb}\
+diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py
+index f7e117a..767c839 100755
+--- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py
++++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py
+@@ -210,7 +210,7 @@ def main():
+         found_lunder = None
+         copy = re.compile(r'.*(copyright.*)|(.*\(c\).*)', re.IGNORECASE)
+         spdx = re.compile(r'.*(SPDX-License-Identifier:.+)')
+-        lunder = re.compile(r'.*(Licensed under.+)', re.IGNORECASE)
++        lunder = re.compile(r'.*(Solderpad.*)|(Apache.*)', re.IGNORECASE)
+         for line in srcfull.splitlines():
+             mat = copy.match(line)
+             if mat is not None:
+@@ -225,7 +225,7 @@ def main():
+             src_lic = found_lunder
+         if found_spdx:
+             if src_lic is None:
+-                src_lic = '\n' + found_spdx
++                src_lic = found_spdx
+             else:
+                 src_lic += '\n' + found_spdx
+

hardware/deps/snitch/Bender.yml

@@ -29,5 +29,3 @@ sources:
     - src/snitch_fp_divsqrt.sv
     - src/snitch_fpu.sv
     - src/snitch_shared_muldiv.sv
-    - src/snitch_demux.sv
-    - src/snitch_axi_adapter.sv