add default register type

lib/rggen/veryl.rb

@@ -42,6 +42,8 @@
     'veryl/bit_field/type/wo_wo1_wotrg',
     'veryl/bit_field/type/wrc_wrs',
     'veryl/bit_field/veryl_top',
+    'veryl/register/type',
+    'veryl/register/type/external',
     'veryl/register/veryl_top',
     'veryl/register_file/veryl_top',
     'veryl/register_block/veryl_top'

lib/rggen/veryl/register/type.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register, :type) do
+  veryl do
+    base_feature do
+      include RgGen::SystemVerilog::RTL::RegisterType
+
+      private
+
+      def register_if
+        register_block.register_if[register.index]
+      end
+
+      def bit_field_if
+        register.bit_field_if
+      end
+    end
+
+    default_feature do
+      template = File.join(__dir__, 'type', 'default.erb')
+      main_code :register, from_template: template
+    end
+
+    factory do
+      def target_feature_key(_configuration, register)
+        type = register.type
+        return type if [:default, *target_features.keys].any? { type == _1 }
+
+        error "code generator for #{type} register type " \
+              'is not implemented'
+      end
+    end
+  end
+end

lib/rggen/veryl/register/type/default.erb

@@ -0,0 +1,15 @@
+inst u_register: rggen_default_register #(
+  READABLE:       <%= readable %>,
+  WRITABLE:       <%= writable %>,
+  ADDRESS_WIDTH:  <%= address_width %>,
+  OFFSET_ADDRESS: <%= offset_address %>,
+  BUS_WIDTH:      <%= bus_width %>,
+  DATA_WIDTH:     <%= width %>,
+  VALUE_WIDTH:    <%= value_width %>,
+  VALID_BITS:     <%= valid_bits %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  register_if:  <%= register_if %>,
+  bit_field_if: <%= bit_field_if %>
+);

lib/rggen/veryl/register/type/external.rb

@@ -0,0 +1,6 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :external) do
+  veryl do
+  end
+end

lib/rggen/veryl/register_block/veryl_top.rb

@@ -12,6 +12,14 @@
       }
     end
 
+    export def value_width
+      register_block.registers.max_by(&:width)&.width
+    end
+
+    export def total_registers
+      register_block.files_and_registers.sum(&:count)
+    end
+
     private
 
     def param_values
@@ -25,13 +33,5 @@ def address_width
     def bus_width
       configuration.bus_width
     end
-
-    def value_width
-      register_block.registers.max_by(&:width)&.width
-    end
-
-    def total_registers
-      register_block.files_and_registers.sum(&:count)
-    end
   end
 end