Merge branch 'master' into ch-compare-id

.ci/Memora.yml

@@ -149,6 +149,32 @@ artifacts:
     outputs:
       - build/axi_iw_converter-%.tested
 
+  axi_lite_dw_converter-%:
+    inputs:
+      - Bender.yml
+      - include
+      - scripts/run_vsim.sh
+      - src/axi_pkg.sv
+      - src/axi_intf.sv
+      - src/axi_test.sv
+      - src/axi_lite_dw_converter.sv
+      - test/tb_axi_lite_dw_converter.sv
+    outputs:
+      - build/axi_lite_dw_converter-%.tested
+
+  axi_lite_mailbox-%:
+    inputs:
+      - Bender.yml
+      - include
+      - scripts/run_vsim.sh
+      - src/axi_pkg.sv
+      - src/axi_intf.sv
+      - src/axi_test.sv
+      - src/axi_lite_mailbox.sv
+      - test/tb_axi_lite_mailbox.sv
+    outputs:
+      - build/axi_lite_mailbox-%.tested
+
   axi_lite_regs-%:
     inputs:
       - Bender.yml
@@ -188,19 +214,6 @@ artifacts:
     outputs:
       - build/axi_lite_to_axi-%.tested
 
-  axi_lite_mailbox-%:
-    inputs:
-      - Bender.yml
-      - include
-      - scripts/run_vsim.sh
-      - src/axi_pkg.sv
-      - src/axi_intf.sv
-      - src/axi_test.sv
-      - src/axi_lite_mailbox.sv
-      - test/tb_axi_lite_mailbox.sv
-    outputs:
-      - build/axi_lite_mailbox-%.tested
-
   axi_lite_xbar-%:
     inputs:
       - Bender.yml

.gitignore

@@ -6,3 +6,4 @@
 /Bender.lock
 /Bender.local
 *.log
+*.wlf

.gitlab-ci.yml

@@ -118,6 +118,16 @@ axi_iw_converter:
   variables:
     TEST_MODULE: axi_iw_converter
 
+axi_lite_dw_converter:
+  <<: *run_vsim
+  variables:
+    TEST_MODULE: axi_lite_dw_converter
+
+axi_lite_mailbox:
+  <<: *run_vsim
+  variables:
+    TEST_MODULE: axi_lite_mailbox
+
 axi_lite_regs:
   <<: *run_vsim
   variables:
@@ -133,11 +143,6 @@ axi_lite_to_axi:
   variables:
     TEST_MODULE: axi_lite_to_axi
 
-axi_lite_mailbox:
-  <<: *run_vsim
-  variables:
-    TEST_MODULE: axi_lite_mailbox
-
 axi_lite_xbar:
   <<: *run_vsim
   variables:

Bender.yml

@@ -49,6 +49,7 @@ sources:
   - src/axi_isolate.sv
   - src/axi_join.sv
   - src/axi_lite_demux.sv
+  - src/axi_lite_dw_converter.sv
   - src/axi_lite_from_mem.sv
   - src/axi_lite_join.sv
   - src/axi_lite_lfsr.sv
@@ -110,6 +111,7 @@ sources:
       - test/tb_axi_dw_upsizer.sv
       - test/tb_axi_fifo.sv
       - test/tb_axi_isolate.sv
+      - test/tb_axi_lite_dw_converter.sv
       - test/tb_axi_lite_mailbox.sv
       - test/tb_axi_lite_regs.sv
       - test/tb_axi_iw_converter.sv

CHANGELOG.md

@@ -14,6 +14,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Add `axi_lite_from_mem` and `axi_from_mem` acting like SRAMs making AXI4 requests downstream.
 - Add `axi_rw_join` and `axi_rw_split` to split/join AXI buses.
 - Add `#_width` functions returning the width of the AXI channels.
+- Add `axi_lite_dw_converter`: Convert the data width of AXI4-Lite transactions. Emmits the
+  appropriate amount of downstream transactions to perform the whole requested access.
+
 
 ### Changed
 - `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter.  This prevents
@@ -25,6 +28,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Move `mem_to_banks` to `common_cells`.
 - Update `common_cells` from version `v1.26.0` to `v1.27.0`.
 - `axi_pkg`: Define `localparams` to define AXI type widths.
+- `axi_test:axi_rand_lite_slave`: R response field is now random.
 
 ### Fixed
 

scripts/run_vsim.sh

@@ -225,6 +225,13 @@ exec_test() {
                 done
             done
             ;;
+        axi_lite_dw_converter)
+            for DWSLV in 32 64 128; do
+                for DWMST in 16 32 64; do
+                    call_vsim tb_axi_lite_dw_converter -gTbAxiDataWidthSlv=$DWSLV -gTbAxiDataWidthMst=$DWMST
+                done
+            done
+            ;;
         *)
             call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx"
             ;;

src/axi_dw_downsizer.sv

@@ -397,11 +397,12 @@ module axi_dw_downsizer #(
               r_state_d = R_PASSTHROUGH;
 
               // Save beat
-              r_req_d.ar           = slv_req_i.ar     ;
-              r_req_d.ar_valid     = 1'b1             ;
-              r_req_d.burst_len    = slv_req_i.ar.len ;
-              r_req_d.orig_ar_size = slv_req_i.ar.size;
-              r_req_d.injected_aw  = 1'b0             ;
+              r_req_d.ar           = slv_req_i.ar        ;
+              r_req_d.ar_valid     = 1'b1                ;
+              r_req_d.burst_len    = slv_req_i.ar.len    ;
+              r_req_d.orig_ar_size = slv_req_i.ar.size   ;
+              r_req_d.injected_aw  = 1'b0                ;
+              r_req_d.r.resp       = axi_pkg::RESP_EXOKAY;
 
               case (r_req_d.ar.burst)
                 axi_pkg::BURST_INCR : begin
@@ -476,6 +477,7 @@ module axi_dw_downsizer #(
           r_req_d.burst_len    = w_req_q.orig_aw_len  ;
           r_req_d.orig_ar_size = w_req_q.orig_aw_size ;
           r_req_d.injected_aw  = 1'b1                 ;
+          r_req_d.r.resp       = axi_pkg::RESP_EXOKAY ;
 
           // Default state
           r_state_d = R_PASSTHROUGH;
@@ -794,10 +796,10 @@ module axi_dw_downsizer #(
     // Can start a new request as soon as w_state_d is W_IDLE
     if (w_state_d == W_IDLE) begin
       // Reset channels
-      w_req_d.aw             = '0                ;
-      w_req_d.aw_valid       = 1'b0              ;
-      w_req_d.aw_throw_error = 1'b0              ;
-      w_req_d.burst_resp     = axi_pkg::RESP_OKAY;
+      w_req_d.aw             = '0                  ;
+      w_req_d.aw_valid       = 1'b0                ;
+      w_req_d.aw_throw_error = 1'b0                ;
+      w_req_d.burst_resp     = axi_pkg::RESP_EXOKAY;
 
       if (!forward_b_beat_full) begin
         if (slv_req_i.aw_valid && slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response