Add assertions, use split module in axi_to_mem_split

src/axi_rw_join.sv

@@ -13,6 +13,7 @@
 // - Tobias Senti <[email protected]>
 
 `include "axi/assign.svh"
+`include "common_cells/assertions.svh"
 
 /// Joins a read and a write slave into one single read / write master
 ///
@@ -22,6 +23,8 @@ module axi_rw_join #(
   parameter type axi_req_t  = logic,
   parameter type axi_resp_t = logic
 ) (
+  input  logic      clk_i,
+  input  logic      rst_ni,
   // Read Slave
   input  axi_req_t  slv_read_req_i,
   output axi_resp_t slv_read_resp_o,
@@ -44,7 +47,7 @@ module axi_rw_join #(
   `AXI_ASSIGN_R_STRUCT  ( slv_read_resp_o.r  , mst_resp_i.r       )
 
   // Read B channel data
-  assign slv_read_resp_o.b         = 'b0;
+  assign slv_read_resp_o.b         = '0;
 
 
   //--------------------------------------
@@ -64,6 +67,10 @@ module axi_rw_join #(
   assign slv_read_resp_o.w_ready   = 1'b0;
   assign slv_read_resp_o.b_valid   = 1'b0;
 
+  // check for AW and W never to be valid
+  `ASSERT_NEVER(slv_read_req_aw_valid, slv_read_req_i.aw_valid, clk_i, !rst_ni)
+  `ASSERT_NEVER(slv_read_req_w_valid,  slv_read_req_i.w_valid,  clk_i, !rst_ni)
+
   //--------------------------------------
   // Write channel data
   //--------------------------------------
@@ -85,6 +92,9 @@ module axi_rw_join #(
   assign slv_write_resp_o.ar_ready = 1'b0;
   assign slv_write_resp_o.r_valid  = 1'b0;
 
+  // check for AR to never be valid
+  `ASSERT_NEVER(slv_write_req_ar_valid, slv_write_req_i.ar_valid, clk_i, !rst_ni)
+
   // Write AW channel handshake
   assign mst_req_o.aw_valid        = slv_write_req_i.aw_valid;
   assign slv_write_resp_o.aw_ready = mst_resp_i.aw_ready;

src/axi_rw_split.sv

@@ -13,6 +13,7 @@
 // - Tobias Senti <[email protected]>
 
 `include "axi/assign.svh"
+`include "common_cells/assertions.svh"
 
 /// Splits a single read / write slave into one read and one write master
 ///
@@ -22,6 +23,8 @@ module axi_rw_split #(
   parameter type axi_req_t  = logic,
   parameter type axi_resp_t = logic
 ) (
+  input  logic      clk_i,
+  input  logic      rst_ni,
   // Read / Write Slave
   input  axi_req_t  slv_req_i,
   output axi_resp_t slv_resp_o,
@@ -65,6 +68,9 @@ module axi_rw_split #(
   assign mst_read_req_o.w_valid   = 1'b0;
   assign mst_read_req_o.b_ready   = 1'b0;
 
+  // check for B never to be valid
+  `ASSERT_NEVER(mst_read_resp_b_valid, mst_read_resp_i.b_valid, clk_i, !rst_ni)
+
 
   //--------------------------------------
   // Write channel data
@@ -76,7 +82,7 @@ module axi_rw_split #(
   `AXI_ASSIGN_B_STRUCT  ( slv_resp_o.b       , mst_write_resp_i.b )
 
   // Write AR channel data
-  assign mst_write_req_o.ar       = 'b0;
+  assign mst_write_req_o.ar       = '0;
 
 
   //--------------------------------------
@@ -87,6 +93,9 @@ module axi_rw_split #(
   assign mst_write_req_o.ar_valid = 1'b0;
   assign mst_write_req_o.r_ready  = 1'b0;
 
+  // check for R never to be valid
+  `ASSERT_NEVER(mst_read_resp_r_valid, mst_read_resp_i.r_valid, clk_i, !rst_ni)
+
   // Write AW channel handshake
   assign mst_write_req_o.aw_valid = slv_req_i.aw_valid;
   assign slv_resp_o.aw_ready      = mst_write_resp_i.aw_ready;

src/axi_to_mem_split.sv

@@ -81,27 +81,19 @@ module axi_to_mem_split #(
 
   logic read_busy, write_busy;
 
-  always_comb begin: proc_axi_rw_split
-    `AXI_SET_R_STRUCT(axi_resp_o.r, axi_read_resp.r)
-    axi_resp_o.r_valid     = axi_read_resp.r_valid;
-    axi_resp_o.ar_ready    = axi_read_resp.ar_ready;
-    `AXI_SET_B_STRUCT(axi_resp_o.b, axi_write_resp.b)
-    axi_resp_o.b_valid     = axi_write_resp.b_valid;
-    axi_resp_o.aw_ready    = axi_write_resp.aw_ready;
-    axi_resp_o.w_ready     = axi_write_resp.w_ready;
-
-    axi_write_req = '0;
-    `AXI_SET_AW_STRUCT(axi_write_req.aw, axi_req_i.aw)
-    axi_write_req.aw_valid = axi_req_i.aw_valid;
-    `AXI_SET_W_STRUCT(axi_write_req.w, axi_req_i.w)
-    axi_write_req.w_valid = axi_req_i.w_valid;
-    axi_write_req.b_ready = axi_req_i.b_ready;
-
-    axi_read_req = '0;
-    `AXI_SET_AR_STRUCT(axi_read_req.ar, axi_req_i.ar)
-    axi_read_req.ar_valid = axi_req_i.ar_valid;
-    axi_read_req.r_ready  = axi_req_i.r_ready;
-  end
+  axi_rw_split #(
+    .axi_req_t  ( axi_req_t  ),
+    .axi_resp_t ( axi_resp_t )
+  ) i_axi_rw_split (
+    .clk_i,
+    .rst_ni,
+    .slv_req_i        ( axi_req_i        ),
+    .slv_resp_o       ( axi_resp_o       ),
+    .mst_read_req_o   ( axi_read_req     ),
+    .mst_read_resp_i  ( axi_read_resp    ),
+    .mst_write_req_o  ( axi_write_req    ),
+    .mst_write_resp_i ( axi_write_resp   )
+  );
 
   assign busy_o = read_busy || write_busy;