Implementation of a Tensor Processing Unit for embedded systems and the IoT.

An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。

DisplayPort IP-core

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface

Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.

Synthesizable SystemVerilog IP-Core of the I2S Receiver

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

A Python-based IP Core Management Infrastructure.

Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)

Python-based IP-XACT parser

IP-XACT based CLI-tools

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation

RGB PWM LED Demo project running on ARTY Z7-20 hardware

The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

LaTeX Class for IP Core Documentation

UART IP-core for FPGA.

Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC