Last Branch Record Performance Monitoring Capabilties

CMakeLists.txt

@@ -49,7 +49,7 @@ set(CMAKE_EXECUTABLE_SUFFIX            ".elf")
 set(ARCH                "rv64imafd")
 set(ABI                 "lp64d")
 set(CMODEL              "medany")
-set(ARCH_FLAGS          --verbose -march=${ARCH} -mabi=${ABI} -mcmodel=${CMODEL})
+set(ARCH_FLAGS          -march=${ARCH} -mabi=${ABI} -mcmodel=${CMODEL})
 
 # spec
 set(SPECS               "nosys.specs")

driver/rocket-chip/rocketcore/riscv_encoding.h

@@ -1012,6 +1012,25 @@
 #define CSR_MHPMCOUNTER29H          0xb9d
 #define CSR_MHPMCOUNTER30H          0xb9e
 #define CSR_MHPMCOUNTER31H          0xb9f
+// custom csr for LBR functionalities
+#define CSR_LBR_CTRL 0x401
+#define CSR_LBR_NUM  0x402
+#define CSR_LBR_SRC0 0x403
+#define CSR_LBR_SRC1 0x404
+#define CSR_LBR_SRC2 0x405
+#define CSR_LBR_SRC3 0x406
+#define CSR_LBR_SRC4 0x407
+#define CSR_LBR_SRC5 0x408
+#define CSR_LBR_SRC6 0x409
+#define CSR_LBR_SRC7 0x40a
+#define CSR_LBR_DST0 0x40b
+#define CSR_LBR_DST1 0x40c
+#define CSR_LBR_DST2 0x40d
+#define CSR_LBR_DST3 0x40e
+#define CSR_LBR_DST4 0x40f
+#define CSR_LBR_DST5 0x410
+#define CSR_LBR_DST6 0x411
+#define CSR_LBR_DST7 0x412
 #define CAUSE_MISALIGNED_FETCH      0x0
 #define CAUSE_FAULT_FETCH           0x1
 #define CAUSE_ILLEGAL_INSTRUCTION   0x2
@@ -1024,6 +1043,7 @@
 #define CAUSE_SUPERVISOR_ECALL      0x9
 #define CAUSE_HYPERVISOR_ECALL      0xa
 #define CAUSE_MACHINE_ECALL         0xb
+
 #endif /* __RV_ENCODING_H */
 
 #ifdef DECLARE_INSN
@@ -1454,6 +1474,24 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+DECLARE_CSR(lbr_ctrl, CSR_LBR_CTRL)
+DECLARE_CSR(lbr_num, CSR_LBR_NUM)
+DECLARE_CSR(lbr_src0, CSR_LBR_SRC0)
+DECLARE_CSR(lbr_src1, CSR_LBR_SRC1)
+DECLARE_CSR(lbr_src2, CSR_LBR_SRC2)
+DECLARE_CSR(lbr_src3, CSR_LBR_SRC3)
+DECLARE_CSR(lbr_src4, CSR_LBR_SRC4)
+DECLARE_CSR(lbr_src5, CSR_LBR_SRC5)
+DECLARE_CSR(lbr_src6, CSR_LBR_SRC6)
+DECLARE_CSR(lbr_src7, CSR_LBR_SRC7)
+DECLARE_CSR(lbr_dst0, CSR_LBR_DST0)
+DECLARE_CSR(lbr_dst1, CSR_LBR_DST1)
+DECLARE_CSR(lbr_dst2, CSR_LBR_DST2)
+DECLARE_CSR(lbr_dst3, CSR_LBR_DST3)
+DECLARE_CSR(lbr_dst4, CSR_LBR_DST4)
+DECLARE_CSR(lbr_dst5, CSR_LBR_DST5)
+DECLARE_CSR(lbr_dst6, CSR_LBR_DST6)
+DECLARE_CSR(lbr_dst7, CSR_LBR_DST7)
 #endif
 
 #ifdef DECLARE_CAUSE

examples/pmu-tests/CMakeLists.txt

@@ -2,6 +2,7 @@ set (TESTS
   pmu-test-load
   pmu-test-store
   pmu-test-inhibit
+  lbr-test
 )
 
 foreach(test ${TESTS})

examples/pmu-tests/src/lbr-test.c

@@ -0,0 +1,57 @@
+#include <stdint.h>
+#include "riscv.h"
+#include "riscv_encoding.h"
+#include "pmu.h"
+#define NUM_ITERS 4
+#define LBR_NUM 8
+
+int main(int argc, char **argv) {
+  // enable LBR
+  asm volatile ("csrw %0, %1" :: "n"(CSR_LBR_CTRL), "i"(1));
+  volatile int c;
+  // do some dummy loops
+  for (int i = 0; i < NUM_ITERS; i++) {
+    c += i;
+  }
+  // do some different loops
+  for (int i = 0; i < NUM_ITERS; i++) {
+    c -= i;
+  }
+  // do a jump calling a dummy function
+  volatile int d = dummy_function(c);
+  // disable LBR
+  asm volatile ("csrw %0, %1" :: "n"(CSR_LBR_CTRL), "i"(0));
+  // read LBR0
+  uint64_t src, dst;
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC0));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST0));
+  printf("LBR[0]: src = %lx, dst = %lx\n", src, dst);
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC1));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST1));
+  printf("LBR[1]: src = %lx, dst = %lx\n", src, dst); 
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC2));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST2));
+  printf("LBR[2]: src = %lx, dst = %lx\n", src, dst);
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC3));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST3));
+  printf("LBR[3]: src = %lx, dst = %lx\n", src, dst);
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC4));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST4));
+  printf("LBR[4]: src = %lx, dst = %lx\n", src, dst);
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC5));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST5));
+  printf("LBR[5]: src = %lx, dst = %lx\n", src, dst);
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC6));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST6));
+  printf("LBR[6]: src = %lx, dst = %lx\n", src, dst);
+  asm volatile ("csrr %0, %1" : "=r"(src) : "n"(CSR_LBR_SRC7));
+  asm volatile ("csrr %0, %1" : "=r"(dst) : "n"(CSR_LBR_DST7));
+  printf("LBR[7]: src = %lx, dst = %lx\n", src, dst);
+  return 0;
+}
+
+__attribute__((noinline))
+int dummy_function(int i) {
+  int j = i + 1;
+  return j;
+}