Force zero tail for risc-v vcompress

Fix #1060
xtensor-stack · Oct 29, 2024 · 03f3d93 · 03f3d93
1 parent e384105
commit 03f3d93
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/include/xsimd/arch/xsimd_rvv.hpp b/include/xsimd/arch/xsimd_rvv.hpp
@@ -1129,13 +1129,14 @@ namespace xsimd
          *************/
         namespace detail
         {
-            XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress), , vec(vec, bvec))
+            XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress XSIMD_RVV_M), , vec(vec, bvec, vec))
         }
         // compress
         template <class A, class T>
         XSIMD_INLINE batch<T, A> compress(batch<T, A> const& x, batch_bool<T, A> const& mask, requires_arch<rvv>) noexcept
         {
-            return detail::rvvcompress(x, mask);
+            const auto zero = broadcast<A>(U(0), rvv {});
+            return detail::rvvcompress(x, mask, zero);
         }
 
         /***************