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serge-sans-paille committed Oct 15, 2024
1 parent 53c49c3 commit 6eb6043
Showing 1 changed file with 9 additions and 23 deletions.
32 changes: 9 additions & 23 deletions include/xsimd/types/xsimd_rvv_register.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,14 @@ namespace xsimd
const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words); \
} \
};
};\
template <>\
XSIMD_INLINE rvv_type_info<scalar, rvv_width_m1 * vmul>::type\
rvv_type_info<scalar, rvv_width_m1 * type>::bitcast<__rvv_uint8m8_t>(\
__rvv_uint8m8_t x) noexcept\
{\
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(x);\
}

#define XSIMD_RVV_MAKE_TYPES(vmul) \
XSIMD_RVV_MAKE_TYPE(int8_t, i, 8, vmul) \
Expand All @@ -127,28 +134,7 @@ namespace xsimd
#undef XSIMD_RVV_MAKE_TYPES
#undef XSIMD_RVV_MAKE_TYPE

// Specialization needed for #1058
template <>
XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 8>::type
rvv_type_info<int8_t, rvv_width_m1 * 8>::bitcast<__rvv_uint8m8_t>(
__rvv_uint8m8_t x) noexcept
{
return __riscv_vreinterpret_i8m8(x);
}
template <>
XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 1>::type
rvv_type_info<int8_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
__rvv_uint8m1_t x) noexcept
{
return __riscv_vreinterpret_i8m1(x);
}
template <>
XSIMD_INLINE rvv_type_info<uint32_t, rvv_width_m1 * 1>::type
rvv_type_info<uint32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
__rvv_uint8m1_t x) noexcept
{
return __riscv_vreinterpret_u32m1(x);
}
// Specialization of as_bytes needed for #1058
template <>
XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 8>::byte_type
rvv_type_info<int8_t, rvv_width_m1 * 8>::as_bytes<__rvv_int8m8_t>(__rvv_int8m8_t x) noexcept
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