[WIP] Fix clang-17 miscompilation of __riscv_vreinterpret_u8m8

xtensor-stack · Oct 15, 2024 · e9ca664 · e9ca664
1 parent e4e871c
commit e9ca664
Showing 1 changed file with 7 additions and 2 deletions.
diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -90,14 +90,18 @@ namespace xsimd
         template <class U>                                                                \
         static XSIMD_INLINE type bitcast(U x) noexcept                                    \
         {                                                                                 \
-            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
+            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_,, s, m, vmul)(x); \
             return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(words);         \
         }                                                                                 \
         template <>                                                                       \
         XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; }                    \
+        template <>                                                                       \
+        XSIMD_INLINE type bitcast<byte_type>(byte_type x) noexcept {                      \
+          return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(words);           \
+        }                                                                                 \
         static XSIMD_INLINE byte_type as_bytes(type x) noexcept                           \
         {                                                                                 \
-            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
+            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_,, s, m, vmul)(x); \
             return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words);         \
         }                                                                                 \
     };
@@ -125,6 +129,7 @@ namespace xsimd
 #undef XSIMD_RVV_MAKE_TYPES
 #undef XSIMD_RVV_MAKE_TYPE
 
+
             // rvv_blob is storage-type abstraction for a vector register.
             template <class T, size_t Width>
             struct rvv_blob : public rvv_type_info<T, Width>