diff memcpy COW optimization #5

tastynoob · 2023-12-14T10:12:27Z

No description provided.

Moved to catiss repo.

Migrate the original code from OpenXiangShan and re-write it with C++ style classes for the upstream riscv-isa-sim.

Rocket-chip restricts the values of MSTATUS.FS.

rocket-chip sets the xtval to instruction values when exceptions. However, XiangShan and NutShell simply clear it, which is also compatible with the RISC-V ISA.

It seems sim_t::addr_to_mem allocates the memory of only PGSIZE bytes at every time. Therefore, we need to separate memcpy operations.

Different DUTs may have different physical address bits.

Both rocket-chip and NutShell do not implement ASIDs.

We add diff_trace_t class to record Spike's actions including * instructions executed * store requests * load requests * page-table walker requests With the above information, we add support for the store commit diff.

Rocket-chip sets the value to zero.

Load operations may cause exceptions. The is_amo flag must be set just before the store is processed.

This commit adds the Sdtrig ISA string for the RISC-V Triggers extension with permission check for the related CSRs.

This CSR only exists if Sdtrig is enabled.

* misa * satp * mimpid * marchid

Practical hardware designs would have reservation sets of 64B. However, Spike seems to have only byte-level reservation sets. I'm not sure whether it would violate the ISA.

If virtual memory has not been enabled, the CPU is not expected to cache any PTEs and should not behave differently with Spike.

There was a macro MAX_INSN_LENGTH, but it seems not to be used anywhere. We use it to decode the maximum insn_length.

When skipping instructions, minstret should be incremented.

poemonsense added 30 commits April 19, 2023 14:34

Ignore vscode project files

70663dc

Add fuzz harness

ca2b07c

Add test interface to main

9f2036b

Update Makefile to support libafl

58e9299

Makefile: fix dependency on spike generated files

2f570c6

Disable default signal handlers.

ceab357

Close file descriptors in destructor of syscall_t

a15ba93

fuzz: remove catiss dependencies

bf483df

Moved to catiss repo.

Merge remote-tracking branch 'origin/master' into fuzz

1f1c62f

fuzz: use macros to switch code blocks

7713507

Rewrite difftest support for Spike as a REF

b95048e

Migrate the original code from OpenXiangShan and re-write it with C++ style classes for the upstream riscv-isa-sim.

csrs: set mstatus.fs to 0 or 3 for CPU_ROCKET_CHIP

c6f503a

Rocket-chip restricts the values of MSTATUS.FS.

trap: make the tval values on insn_trap configurable

ee71b0d

rocket-chip sets the xtval to instruction values when exceptions. However, XiangShan and NutShell simply clear it, which is also compatible with the RISC-V ISA.

Add support for an optional flash region

e4e7314

difftest: fix the memcpy for n > PGSIZE

8eee588

It seems sim_t::addr_to_mem allocates the memory of only PGSIZE bytes at every time. Therefore, we need to separate memcpy operations.

mmu: update the physical address for DUTs

3d0823e

Different DUTs may have different physical address bits.

Update ASID configs for different DUTs.

ba31db1

Both rocket-chip and NutShell do not implement ASIDs.

Update misa write mask for rocket-chip

695a596

Update medeleg write mask for rocket-chip

6520266

Change the default mmu capability to Sv39 for DUTs

652cfa2

Add support for difftest logs and traces

5f771d3

We add diff_trace_t class to record Spike's actions including * instructions executed * store requests * load requests * page-table walker requests With the above information, we add support for the store commit diff.

Add zicntr extension for rocket-chip

b605d97

Move macro definitions to a separated header file

90679be

Add support for disabling AMO store diff

b73fe6f

Set tval to zero on instruction misaligned exceptions

a7ff4a2

Rocket-chip sets the value to zero.

Fix the missing AMO store condition for SC

9e88039

Fix the display for FPR

45243be

mmu: set is_amo before store operations

a490da9

Load operations may cause exceptions. The is_amo flag must be set just before the store is processed.

difftest: use rom_device_t for the read-only flash

14886a2

Add Sdtrig isa string with permission checkers for CSRs

5be2b5f

This commit adds the Sdtrig ISA string for the RISC-V Triggers extension with permission check for the related CSRs.

poemonsense and others added 28 commits July 14, 2023 20:49

Update marchid for rocket-chip

ebfdc67

Disable time CSR in difftest mode

17ca299

csrs: fix the permissions of mcontext

8a882b4

This CSR only exists if Sdtrig is enabled.

processor: fix the mimpid for rocket-chip

2e64f66

sim: disable routine timer update for DiffTest

32516bd

mmu: fix the order of bytes on instruction fetch

552126d

Update default CSR values and masks for NutShell

619bc48

* misa * satp * mimpid * marchid

csrs: mstatus.fs is always zero in NutShell

7d4aac7

Add support for sanitizer coverage instrumentation

2017630

Add the difftest_display interface

3c2b4bb

Allow the memory size to be overrided at run-time

437777c

Allow the mhartid to be overrided at run-time

bbd5213

mmu: change the size of reservation sets for DIFFTEST

7e7d660

Practical hardware designs would have reservation sets of 64B. However, Spike seems to have only byte-level reservation sets. I'm not sure whether it would violate the ISA.

sfence_vma: fix the missing flush_tlb_on_sfence_vma

6abfa14

difftrace: set satp_written only if vm enabled previously

08ec9c4

If virtual memory has not been enabled, the CPU is not expected to cache any PTEs and should not behave differently with Spike.

decode: disable 48- and 64-bit instructions if needed

31aa3be

There was a macro MAX_INSN_LENGTH, but it seems not to be used anywhere. We use it to decode the maximum insn_length.

Add support for the ref_skip_one interface

63d1b1e

When skipping instructions, minstret should be incremented.

Update PMP configs for XIANGSHAN

57a8870

debug,dummy: return false on out-of-range accesses

dc253dd

Create README.md

f857851

Update README.md

fe255a0

proc: avoid initializing PMP entries at reset with DIFFTEST

549e4e9

Show PMP registers on reg_display

c8036d7

Update writable mask for misa of XiangShan

80a3c81

Update mimpid and marchid for XiangShan

9297021

Add support for RISC-V vector extension difftest (#3)

71de241

difftest: fix init of mstatus (#4)

b333b1d

Update diff memcpy with COW optimization

145445f

tastynoob force-pushed the cow-optim branch from 2897120 to 145445f Compare December 14, 2023 10:15

lewislzh force-pushed the difftest branch from 62a29dc to e11aaec Compare December 4, 2024 03:34

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diff memcpy COW optimization #5

diff memcpy COW optimization #5

tastynoob commented Dec 14, 2023

diff memcpy COW optimization #5

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diff memcpy COW optimization #5

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tastynoob commented Dec 14, 2023