Migrate rocketchip utils to standalone library

build.sc

@@ -6,6 +6,7 @@ import $file.dependencies.hardfloat.common
 import $file.dependencies.cde.common
 import $file.dependencies.diplomacy.common
 import $file.dependencies.chisel.build
+import $file.rocketutils.{common => utilsCommon}
 import $file.common
 
 object v {
@@ -25,6 +26,29 @@ object v {
   )
 }
 
+object rocketutils extends Module {
+
+  object rocketutils extends Cross[rocketutils](v.chiselCrossVersions.view.filterKeys(_ != "source").keys.toSeq)
+
+  trait rocketutils extends utilsCommon.ChiselCrossModule with RocketChipPublishModule{
+    def scalaVersion = T(v.scala)
+
+    def moduleDeps = super.moduleDeps ++ Seq(cde, diplomacy(crossValue))
+    def ivyDeps = T(super.ivyDeps() ++ Agg(v.json4sJackson))
+  }
+
+  object rocketutilsSourceMod extends utilsCommon.ChiselSourceModule with RocketChipPublishModule {
+    def millSourcePath = millOuterCtx.millSourcePath / "rocketutils"
+
+    def scalaVersion = T(v.scala)
+
+    def chiselModule = chisel
+    def chiselPluginJar = T(chiselModule.pluginModule.jar())
+
+    def moduleDeps = super.moduleDeps ++ Seq(cde, diplomacy("source"))
+  }
+}
+
 // Build form source only for dev
 object chisel extends Chisel
 
@@ -131,6 +155,14 @@ trait RocketChip
 
   def cdeModule = cde
 
+  def rocketUtilsModule = {
+    if (crossValue == "source") {
+      rocketutils.rocketutilsSourceMod
+    } else {
+      rocketutils.rocketutils(crossValue)
+    }
+  }
+
   def diplomacyModule = diplomacy(crossValue)
 
   def diplomacyIvy = None

common.sc

@@ -38,6 +38,8 @@ trait RocketChipModule
   override def mainClass = T(Some("freechips.rocketchip.diplomacy.Main"))
 
   def macrosModule: MacrosModule
+
+  def rocketUtilsModule: ScalaModule
 
   // should be hardfloat/common.sc#HardfloatModule
   def hardfloatModule: ScalaModule
@@ -48,7 +50,7 @@ trait RocketChipModule
 
   def json4sJacksonIvy: Dep
 
-  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, diplomacyModule)
+  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, diplomacyModule, rocketUtilsModule)
 
   override def ivyDeps = T(
     super.ivyDeps() ++ Agg(

rocketutils/build.sc

@@ -0,0 +1,36 @@
+import mill._
+import mill.scalalib._
+
+import $file.common
+
+val scala = "2.13.12"
+val chisel = "6.3.0"
+
+val json4sJackson = ivy"org.json4s::json4s-jackson:4.0.5"
+val sourcecode = ivy"com.lihaoyi::sourcecode:0.3.1"
+
+object dependencies extends Module {
+  object cde extends ScalaModule {
+    def scalaVersion: T[String] = T(scala)
+    def millSourcePath = super.millSourcePath / "cde"
+  }
+
+  object diplomacy extends Cross[DiplomacyCross](chisel)
+
+  trait DiplomacyCross extends common.ChiselCrossModule {
+    def scalaVersion: T[String] = T(scala)
+    def millSourcePath = super.millSourcePath / "diplomacy"
+    def moduleDeps = super.moduleDeps ++ Seq(cde)
+    def ivyDeps = T(super.ivyDeps() ++ Agg(sourcecode))
+  }
+}
+
+object rocketutils extends Cross[RocketutilsCross](chisel)
+
+trait RocketutilsCross extends common.ChiselCrossModule {
+  def scalaVersion = T(scala)
+
+  def moduleDeps = super.moduleDeps ++ Seq(dependencies.cde, dependencies.diplomacy(crossValue))
+
+  def ivyDeps = T(super.ivyDeps() ++ Agg(json4sJackson))
+}

rocketutils/common.sc

@@ -0,0 +1,29 @@
+import mill._
+import mill.scalalib._
+
+trait ChiselModule extends ScalaModule {
+  def scalaVersion: T[String]
+  def chiselVersion: T[String]
+
+  def ivyDeps = T(super.ivyDeps() ++ Some(ivy"org.chipsalliance::chisel:${chiselVersion()}"))
+  def scalacPluginIvyDeps = T(super.ivyDeps() ++ Agg(ivy"org.chipsalliance:::chisel-plugin:${chiselVersion()}"))
+}
+
+trait ChiselCrossModule extends ScalaModule with Cross.Module[String] {
+  def scalaVersion: T[String]
+  def chiselVersion: T[String] = T(crossValue)
+
+  def ivyDeps = T(super.ivyDeps() ++ Some(ivy"org.chipsalliance::chisel:${chiselVersion()}"))
+  def scalacPluginIvyDeps = T(super.ivyDeps() ++ Agg(ivy"org.chipsalliance:::chisel-plugin:${chiselVersion()}"))
+}
+
+trait ChiselSourceModule extends ScalaModule {
+  def scalaVersion: T[String]
+
+  def chiselModule: ScalaModule
+  def chiselPluginJar: T[PathRef]
+
+  def moduleDeps = super.moduleDeps ++ Agg(chiselModule)
+  def scalacOptions = T(super.scalacOptions() ++ Seq(s"-Xplugin:${chiselPluginJar().path}"))
+  def scalacPluginClasspath: T[Agg[PathRef]] = T(super.scalacPluginClasspath() ++ Agg(chiselPluginJar()))
+}

rocketutils/rocketutils/src/rocketutils/Annotations.scala

@@ -0,0 +1,126 @@
+// See LICENSE.SiFive for license details.
+
+package org.chipsalliance.rocketutils
+
+import chisel3._
+import chisel3.experimental.{annotate, ChiselAnnotation}
+
+import firrtl.annotations._
+
+/** Record a sram. */
+case class SRAMAnnotation(target: Named,
+  address_width: Int,
+  name: String,
+  data_width: Int,
+  depth: BigInt,
+  description: String,
+  write_mask_granularity: Int) extends SingleTargetAnnotation[Named] {
+  def duplicate(n: Named) = this.copy(n)
+}
+
+/** Record a set of interrupts. */
+case class InterruptsPortAnnotation(target: Named, name: String, interruptIndexes: Seq[Int]) extends SingleTargetAnnotation[Named] {
+  def duplicate(n: Named) = this.copy(n)
+}
+
+/** Record a case class that was used to parameterize this target. */
+case class GlobalConstantsAnnotation(target: Named, xLen: Int) extends SingleTargetAnnotation[Named] {
+  def duplicate(n: Named) = this.copy(n)
+}
+
+case class GlobalConstantsChiselAnnotation[T <: Product](target: InstanceId, xLen: Int) extends ChiselAnnotation {
+  def toFirrtl = GlobalConstantsAnnotation(target.toNamed, xLen)
+}
+
+/** Record a case class that was used to parameterize this target. */
+case class ParamsAnnotation(target: Named, paramsClassName: String, params: Map[String,Any]) extends SingleTargetAnnotation[Named] {
+  def duplicate(n: Named) = this.copy(n)
+}
+
+case class ParamsChiselAnnotation[T <: Product](target: InstanceId, params: T) extends ChiselAnnotation {
+  private val paramMap = params.getClass.getDeclaredFields.map(_.getName).zip(params.productIterator).toMap
+  def toFirrtl = ParamsAnnotation(target.toNamed, params.getClass.getName, paramMap)
+}
+
+/** Marks this module as a candidate for register retiming */
+case class RetimeModuleAnnotation(target: ModuleName) extends SingleTargetAnnotation[ModuleName] {
+  def duplicate(n: ModuleName) = this.copy(n)
+}
+
+/** Record the resetVector. */
+case class ResetVectorAnnotation(target: Named, resetVec: BigInt) extends SingleTargetAnnotation[Named] {
+  def duplicate(n: Named): ResetVectorAnnotation = this.copy(n)
+}
+
+/** Helper object containing methods for applying annotations to targets */
+object Annotated {
+
+  def srams(
+    component: InstanceId,
+    name: String,
+    address_width: Int,
+    data_width: Int,
+    depth: BigInt,
+    description: String,
+    write_mask_granularity: Int): Unit = {
+    annotate(new ChiselAnnotation {def toFirrtl: Annotation = SRAMAnnotation(
+      component.toNamed,
+      address_width = address_width,
+      name = name,
+      data_width = data_width,
+      depth = depth,
+      description = description,
+      write_mask_granularity = write_mask_granularity
+    )})}
+
+  def interrupts(component: InstanceId, name: String, interrupts: Seq[Int]): Unit = {
+    annotate(new ChiselAnnotation {def toFirrtl: Annotation = InterruptsPortAnnotation(
+      component.toNamed,
+      name,
+      interrupts
+    )})
+  }
+
+  def resetVector(component: InstanceId, resetVec: BigInt): Unit = {
+    annotate(new ChiselAnnotation {def toFirrtl: Annotation = ResetVectorAnnotation(component.toNamed, resetVec)})
+  }
+
+  def constants(component: InstanceId, xLen: Int): Unit = {
+    annotate(GlobalConstantsChiselAnnotation(component, xLen ))
+  }
+
+  def params[T <: Product](component: InstanceId, params: T): T = {
+    annotate(ParamsChiselAnnotation(component, params))
+    params
+  }
+}
+
+/** Mix this into a Module class or instance to mark its ports as untouchable */
+trait DontTouch { self: RawModule =>
+  // TODO: replace this with an implicit class from UserModule that uses getPorts
+  // TODO: this is a workaround for firrtl #756
+  def dontTouch(data: Data): Unit = data match {
+     case agg: Aggregate => agg.getElements.foreach(dontTouch)
+     case elt: Element => chisel3.dontTouch(elt)
+  }
+
+  /** Marks every port as don't touch
+    *
+    * @note This method can only be called after the Module has been fully constructed
+    *   (after Module(...))
+    */
+  def dontTouchPorts(): this.type = {
+    self.getModulePorts.foreach(dontTouch(_))
+    self
+  }
+
+  def dontTouchPortsExcept(f: Data => Boolean): this.type = {
+    self.getModulePorts.filterNot(f).foreach(dontTouch(_))
+    self
+  }
+}
+
+/** Mix this into a Module class or instance to mark it for register retiming */
+trait ShouldBeRetimed { self: RawModule =>
+  chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl: RetimeModuleAnnotation = RetimeModuleAnnotation(self.toNamed) })
+}