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llvm · Nov 26, 2024 · 66eb94f · 66eb94f
1 parent 6bb984a
commit 66eb94f
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Showing 5 changed files with 22 additions and 11 deletions.
diff --git a/frontends/PyCDE/test/test_handshake.py b/frontends/PyCDE/test/test_handshake.py
@@ -15,6 +15,15 @@
 # CHECK:    return %0 : i8
 # CHECK:  }
 
+# CHECK:  hw.module @Top(in %clk : i1, in %rst : i1, in %a : i8, in %a_valid : i1, in %x_ready : i1, out a_ready : i1, out x : i8, out x_valid : i1)
+# CHECK:    %TestFunc.in0_ready, %TestFunc.out0, %TestFunc.out0_valid = hw.instance "TestFunc" @TestFunc(in0: %a: i8, in0_valid: %a_valid: i1, clk: %clk: i1, rst: %rst: i1, out0_ready: %x_ready: i1) -> (in0_ready: i1, out0: i8, out0_valid: i1)
+# CHECK:    hw.output %TestFunc.in0_ready, %TestFunc.out0, %TestFunc.out0_valid : i1, i8, i1
+# CHECK:  hw.module @TestFunc(in %in0 : i8, in %in0_valid : i1, in %clk : i1, in %rst : i1, in %out0_ready : i1, out in0_ready : i1, out out0 : i8, out out0_valid : i1)
+# CHECK:    %c15_i8 = hw.constant 15 : i8
+# CHECK:    [[R0:%.+]] = comb.and %out0_ready, %in0_valid : i1
+# CHECK:    [[R1:%.+]] = comb.and bin %in0, %c15_i8 : i8
+# CHECK:    hw.output [[R0]], [[R1]], %in0_valid : i1, i8, i1
+
 
 class TestFunc(Func):
   a = Input(Bits(8))
@@ -28,10 +37,7 @@ def build(ports):
 BarType = types.struct({"foo": types.i12}, "bar")
 
 
-@unittestmodule(print=True,
-                run_passes=True,
-                print_after_passes=True,
-                debug=True)
+@unittestmodule(print=True, run_passes=True, print_after_passes=True)
 class Top(Module):
   clk = Clock()
   rst = Input(Bits(1))

diff --git a/frontends/PyCDE/test/test_polynomial.py b/frontends/PyCDE/test/test_polynomial.py
@@ -122,7 +122,7 @@ def construct(self):
 
 print("Generating rest...")
 poly.generate()
-poly.run_passes()
+poly.run_passes(debug=True)
 
 print("=== Final IR...")
 poly.print()

diff --git a/lib/Conversion/DCToHW/DCToHW.cpp b/lib/Conversion/DCToHW/DCToHW.cpp
@@ -838,10 +838,8 @@ static bool isDCType(Type type) { return isa<TokenType, ValueType>(type); }
 ///  Returns true if the given `op` is considered as legal - i.e. it does not
 ///  contain any dc-typed values.
 static bool isLegalOp(Operation *op) {
-  if (auto funcOp = dyn_cast<HWModuleLike>(op)) {
-    return llvm::none_of(funcOp.getPortTypes(), isDCType) &&
-           llvm::none_of(funcOp.getBodyBlock()->getArgumentTypes(), isDCType);
-  }
+  if (auto funcOp = dyn_cast<HWModuleLike>(op))
+    return llvm::none_of(funcOp.getPortTypes(), isDCType);
 
   bool operandsOK = llvm::none_of(op->getOperandTypes(), isDCType);
   bool resultsOK = llvm::none_of(op->getResultTypes(), isDCType);

diff --git a/lib/Conversion/HandshakeToDC/HandshakeToDC.cpp b/lib/Conversion/HandshakeToDC/HandshakeToDC.cpp
@@ -763,7 +763,7 @@ class HandshakeToDCPass
   void runOnOperation() override {
     mlir::ModuleOp mod = getOperation();
     auto targetModifier = [](mlir::ConversionTarget &target) {
-      target.addLegalDialect<hw::HWDialect, func::FuncDialect>();
+      // target.addLegalDialect<hw::HWDialect, func::FuncDialect>();
     };
 
     auto patternBuilder = [&](TypeConverter &typeConverter,
@@ -807,7 +807,8 @@ LogicalResult circt::handshaketodc::runHandshakeToDC(
   ConversionTarget target(*ctx);
   target.addIllegalDialect<handshake::HandshakeDialect>();
   target.addLegalDialect<dc::DCDialect>();
-  target.addLegalOp<mlir::ModuleOp, handshake::ESIInstanceOp>();
+  target.addLegalOp<mlir::ModuleOp, handshake::ESIInstanceOp, hw::HWModuleOp,
+                    hw::OutputOp>();
 
   // And any user-specified target adjustments
   if (configureTarget)

diff --git a/test/Conversion/DCToHW/basic.mlir b/test/Conversion/DCToHW/basic.mlir
@@ -196,3 +196,9 @@ hw.module @merge(in %first : !dc.token, in %second : !dc.token, out token : !dc.
     %selected = dc.merge %first, %second
     hw.output %selected : !dc.value<i1>
 }
+
+// CHECK:  hw.module.extern @ext(in %a : i32, out b : i32)
+hw.module.extern @ext(in %a : i32, out b : i32)
+
+// CHECK:  hw.module.extern @extDC(in %a : !esi.channel<i32>, out b : i32)
+hw.module.extern @extDC(in %a : !dc.value<i32>, out b : i32)