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[FIRRTL] infer more return types in asm format #7781

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[FIRRTL] infer more return types in asm format #7781

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2 changes: 1 addition & 1 deletion include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td
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Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ def FormalOp : FIRRTLOp<"formal", [
%c42_8 = firrtl.constant 42 : !firrtl.uint<8>
firrtl.connect %bar, %c42_8: !firrtl.uint<8>, !firrtl.uint<8>
%c69_8 = firrtl.constant 69 : !firrtl.uint<8>
%cond = firrtl.eq %c69_8, %out : (!firrtl.uint<8>, !firrtl.uint<8>) -> !firrtl.uint<1>
%cond = firrtl.eq %c69_8, %out : !firrtl.uint<8>, !firrtl.uint<8>
firrtl.assert %cond
}

Expand Down
32 changes: 13 additions & 19 deletions include/circt/Dialect/FIRRTL/FIRRTLExpressions.td
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Expand Up @@ -419,7 +419,7 @@ def SubaccessOp : FIRRTLExprOp<"subaccess"> {
let results = (outs FIRRTLBaseType:$result);

let assemblyFormat =
"$input `[` $index `]` attr-dict `:` qualified(type($input)) `,` qualified(type($index))";
"$input `[` $index `]` attr-dict `:` qualified(type(operands))";

let hasCanonicalizer = true;
let inferTypeDecl = [{
Expand Down Expand Up @@ -582,10 +582,7 @@ class BinaryPrimOp<string mnemonic, Type lhsType, Type rhsType, Type resultType,
let arguments = (ins lhsType:$lhs, rhsType:$rhs);
let results = (outs resultType:$result);

let assemblyFormat = [{
$lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
}];
let assemblyFormat = "$lhs `,` $rhs attr-dict `:` qualified(type(operands))";

// Give concrete operations a chance to set a type inference callback. If left
// empty, a declaration for `inferReturnType` will be emitted that the
Expand Down Expand Up @@ -709,8 +706,7 @@ class UnaryPrimOp<string mnemonic, Type srcType, Type resultType,
let arguments = (ins srcType:$input);
let results = (outs resultType:$result);

let assemblyFormat =
"$input attr-dict `:` functional-type($input, $result)";
let assemblyFormat = "$input attr-dict `:` qualified(type($input))";

// Give concrete operations a chance to set a type inference callback. If left
// empty, a declaration for `inferReturnType` will be emitted that the
Expand Down Expand Up @@ -791,7 +787,7 @@ def BitsPrimOp : PrimOp<"bits"> {
let results = (outs UIntType:$result);

let assemblyFormat =
"$input $hi `to` $lo attr-dict `:` functional-type($input, $result)";
"$input $hi `to` $lo attr-dict `:` qualified(type($input))";

let description = [{
The `bits` operation extracts the bits between `hi` (inclusive) and `lo`
Expand Down Expand Up @@ -824,7 +820,7 @@ def HeadPrimOp : PrimOp<"head"> {
let results = (outs UIntType:$result);

let assemblyFormat =
"$input `,` $amount attr-dict `:` functional-type($input, $result)";
"$input `,` $amount attr-dict `:` qualified(type($input))";

let inferTypeDecl = [{
static FIRRTLType inferReturnType(FIRRTLType input, int64_t amount,
Expand All @@ -851,7 +847,7 @@ def MuxPrimOp : PrimOp<"mux"> {
let results = (outs PassiveType:$result);

let assemblyFormat =
"`(` operands `)` attr-dict `:` functional-type(operands, $result)";
"`(` $sel `,` $high `,` $low `)` attr-dict `:` qualified(type(operands))";

let inferTypeDecl = [{
static FIRRTLType inferReturnType(FIRRTLType sel, FIRRTLType high,
Expand All @@ -878,7 +874,7 @@ def PadPrimOp : PrimOp<"pad"> {
let results = (outs IntType:$result);

let assemblyFormat =
"$input `,` $amount attr-dict `:` functional-type($input, $result)";
"$input `,` $amount attr-dict `:` qualified(type($input))";

let description = [{
Pad the input out to an `amount` wide integer, sign extending or zero
Expand Down Expand Up @@ -908,7 +904,7 @@ class ShiftPrimOp<string mnemonic> : PrimOp<mnemonic> {
let results = (outs IntType:$result);

let assemblyFormat =
"$input `,` $amount attr-dict `:` functional-type($input, $result)";
"$input `,` $amount attr-dict `:` qualified(type($input))";

let inferTypeDecl = [{
static FIRRTLType inferReturnType(FIRRTLType input, int64_t amount,
Expand Down Expand Up @@ -950,7 +946,7 @@ def TailPrimOp : PrimOp<"tail"> {
let results = (outs UIntType:$result);

let assemblyFormat =
"$input `,` $amount attr-dict `:` functional-type($input, $result)";
"$input `,` $amount attr-dict `:` qualified(type($input))";

let description = [{
The `tail` operation truncates the `amount` most significant bits from
Expand Down Expand Up @@ -999,7 +995,7 @@ def Mux2CellIntrinsicOp : PrimOp<"int.mux2cell"> {
let hasCanonicalizer = true;

let assemblyFormat =
"`(` operands `)` attr-dict `:` functional-type(operands, $result)";
"`(` operands `)` attr-dict `:` qualified(type(operands))";
}

def Mux4CellIntrinsicOp : PrimOp<"int.mux4cell"> {
Expand All @@ -1021,7 +1017,7 @@ def Mux4CellIntrinsicOp : PrimOp<"int.mux4cell"> {
let hasCanonicalizer = true;

let assemblyFormat =
"`(` operands `)` attr-dict `:` functional-type(operands, $result)";
"`(` operands `)` attr-dict `:` qualified(type(operands))";
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1226,8 +1222,7 @@ def ObjectAnyRefCastOp : FIRRTLOp<"object.anyref_cast", [Pure]> {
let arguments = (ins ClassType:$input);
let results = (outs AnyRefType:$result);

let assemblyFormat =
"$input attr-dict `:` type($input)";
let assemblyFormat = "$input attr-dict `:` type($input)";
}

def StringConstantOp : FIRRTLOp<"string", [Pure, ConstantLike]> {
Expand Down Expand Up @@ -1485,8 +1480,7 @@ def RefCastOp : FIRRTLOp<"ref.cast",
let hasFolder = 1;
let hasVerifier = 1;

let assemblyFormat =
"$input attr-dict `:` functional-type($input, $result)";
let assemblyFormat = "$input attr-dict `:` functional-type($input, $result)";
}

def RefResolveOp: FIRRTLExprOp<"ref.resolve",
Expand Down
2 changes: 1 addition & 1 deletion test/CAPI/firrtl.c
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Expand Up @@ -39,7 +39,7 @@ void testExport(MlirContext ctx) {
" firrtl.module @ExportTestSimpleModule(in %in_1: !firrtl.uint<32>,\n"
" in %in_2: !firrtl.uint<32>,\n"
" out %out: !firrtl.uint<32>) {\n"
" %0 = firrtl.and %in_1, %in_2 : (!firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<32>\n"
" %0 = firrtl.and %in_1, %in_2 : !firrtl.uint<32>, !firrtl.uint<32>\n"
" firrtl.connect %out, %0 : !firrtl.uint<32>, !firrtl.uint<32>\n"
" }\n"
"}\n";
Expand Down
4 changes: 2 additions & 2 deletions test/CAPI/firtool.c
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Expand Up @@ -32,8 +32,8 @@ void exportVerilog(MlirContext ctx, bool disableOptimization) {
" firrtl.module @ExportTestSimpleModule(in %in_1: !firrtl.uint<32>,\n"
" in %in_2: !firrtl.uint<32>,\n"
" out %out: !firrtl.uint<32>) {\n"
" %0 = firrtl.and %in_1, %in_2 : (!firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<32>\n"
" %1 = firrtl.and %0, %in_2 : (!firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<32>\n"
" %0 = firrtl.and %in_1, %in_2 : !firrtl.uint<32>, !firrtl.uint<32>\n"
" %1 = firrtl.and %0, %in_2 : !firrtl.uint<32>, !firrtl.uint<32>\n"
" firrtl.connect %out, %1 : !firrtl.uint<32>, !firrtl.uint<32>\n"
" }\n"
"}\n";
Expand Down
4 changes: 2 additions & 2 deletions test/Conversion/FIRRTLToHW/intrinsics-errors.mlir
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Expand Up @@ -5,7 +5,7 @@ firrtl.circuit "Foo" {
%0 = firrtl.int.ltl.delay %a, 42 : (!firrtl.uint<1>) -> !firrtl.uint<1>
// expected-error @below {{operand of type '!ltl.sequence' cannot be used as an integer}}
// expected-error @below {{couldn't handle this operation}}
%1 = firrtl.and %0, %b : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
%1 = firrtl.and %0, %b : !firrtl.uint<1>, !firrtl.uint<1>
}
}

Expand All @@ -15,7 +15,7 @@ firrtl.circuit "Foo" {
firrtl.module @Foo(in %a: !firrtl.uint<1>, in %b: !firrtl.uint<1>) {
%0 = firrtl.wire : !firrtl.uint<1>
// expected-note @below {{leaking outside verification context here}}
%1 = firrtl.and %0, %b : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
%1 = firrtl.and %0, %b : !firrtl.uint<1>, !firrtl.uint<1>
// expected-error @below {{verification operation used in a non-verification context}}
%2 = firrtl.int.ltl.delay %a, 42 : (!firrtl.uint<1>) -> !firrtl.uint<1>
firrtl.matchingconnect %0, %2 : !firrtl.uint<1>
Expand Down
24 changes: 12 additions & 12 deletions test/Conversion/FIRRTLToHW/lower-to-hw-module.mlir
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Expand Up @@ -27,20 +27,20 @@ firrtl.circuit "Simple" {
in %in3: !firrtl.sint<8>,
out %out4: !firrtl.uint<4>) {

%1 = firrtl.asUInt %in1 : (!firrtl.uint<4>) -> !firrtl.uint<4>
%1 = firrtl.asUInt %in1 : !firrtl.uint<4>

// CHECK: comb.concat %false, %in1
// CHECK: comb.concat %false, %in1

// CHECK: comb.sub
%2 = firrtl.sub %1, %1 : (!firrtl.uint<4>, !firrtl.uint<4>) -> !firrtl.uint<5>
%2 = firrtl.sub %1, %1 : !firrtl.uint<4>, !firrtl.uint<4>

// CHECK: %3 = comb.concat %false, %in2 : i1, i2
%3 = firrtl.pad %in2, 3 : (!firrtl.uint<2>) -> !firrtl.uint<3>
%3 = firrtl.pad %in2, 3 : !firrtl.uint<2>
// CHECK: comb.concat %false, %3 : i1, i3
%4 = firrtl.pad %3, 4 : (!firrtl.uint<3>) -> !firrtl.uint<4>
%4 = firrtl.pad %3, 4 : !firrtl.uint<3>
// CHECK: [[RESULT:%.+]] = comb.xor
%5 = firrtl.xor %in2, %4 : (!firrtl.uint<2>, !firrtl.uint<4>) -> !firrtl.uint<4>
%5 = firrtl.xor %in2, %4 : !firrtl.uint<2>, !firrtl.uint<4>

firrtl.connect %out4, %5 : !firrtl.uint<4>, !firrtl.uint<4>
// CHECK-NEXT: hw.output [[RESULT]] : i4
Expand Down Expand Up @@ -115,7 +115,7 @@ firrtl.circuit "Simple" {
// CHECK-NEXT: [[T0:%.+]] = comb.concat %false, %inA
// CHECK-NEXT: [[T1:%.+]] = comb.concat %false, [[OUTC]]
// CHECK-NEXT: comb.sub bin [[T0]], [[T1]]
%0 = firrtl.sub %inA, %outC : (!firrtl.uint<4>, !firrtl.uint<4>) -> !firrtl.uint<5>
%0 = firrtl.sub %inA, %outC : !firrtl.uint<4>, !firrtl.uint<4>

// No connections to outD.

Expand All @@ -142,7 +142,7 @@ firrtl.circuit "Simple" {
firrtl.module private @Analog(in %a1: !firrtl.analog<1>,
out %outClock: !firrtl.clock) {

%clock = firrtl.asClock %a1 : (!firrtl.analog<1>) -> !firrtl.clock
%clock = firrtl.asClock %a1 : !firrtl.analog<1>
firrtl.connect %outClock, %clock : !firrtl.clock, !firrtl.clock
}

Expand All @@ -160,10 +160,10 @@ firrtl.circuit "Simple" {

// Calculation of input (the firrtl.add + firrtl.eq) happens after the
// instance.
%0 = firrtl.add %arg0, %arg0 : (!firrtl.uint<2>, !firrtl.uint<2>) -> !firrtl.uint<3>
%0 = firrtl.add %arg0, %arg0 : !firrtl.uint<2>, !firrtl.uint<2>

// Multiple uses of the add.
%a = firrtl.eq %0, %arg2 : (!firrtl.uint<3>, !firrtl.uint<3>) -> !firrtl.uint<1>
%a = firrtl.eq %0, %arg2 : !firrtl.uint<3>, !firrtl.uint<3>
// CHECK-NEXT: [[ARG]] = comb.icmp bin eq [[ADD]], %arg2 : i3
firrtl.connect %myext#0, %a : !firrtl.uint<1>, !firrtl.uint<1>

Expand All @@ -178,7 +178,7 @@ firrtl.circuit "Simple" {
%myext:2 = firrtl.instance myext @MyParameterizedExtModule(in in: !firrtl.uint<1>, out out: !firrtl.uint<8>)

// Output of the instance is fed into the input!
%11 = firrtl.bits %myext#1 2 to 2 : (!firrtl.uint<8>) -> !firrtl.uint<1>
%11 = firrtl.bits %myext#1 2 to 2 : !firrtl.uint<8>
// CHECK: %0 = comb.extract %myext.out from 2 : (i8) -> i1

firrtl.connect %myext#0, %11 : !firrtl.uint<1>, !firrtl.uint<1>
Expand All @@ -190,10 +190,10 @@ firrtl.circuit "Simple" {
in %inC: !firrtl.analog<0>,
out %outa: !firrtl.uint<4>,
out %outb: !firrtl.uint<0>) {
%0 = firrtl.mul %inA, %inB : (!firrtl.uint<4>, !firrtl.uint<0>) -> !firrtl.uint<4>
%0 = firrtl.mul %inA, %inB : !firrtl.uint<4>, !firrtl.uint<0>
firrtl.connect %outa, %0 : !firrtl.uint<4>, !firrtl.uint<4>

%1 = firrtl.mul %inB, %inB : (!firrtl.uint<0>, !firrtl.uint<0>) -> !firrtl.uint<0>
%1 = firrtl.mul %inB, %inB : !firrtl.uint<0>, !firrtl.uint<0>
firrtl.connect %outb, %1 : !firrtl.uint<0>, !firrtl.uint<0>

firrtl.attach %inC, %inC : !firrtl.analog<0>, !firrtl.analog<0>
Expand Down
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