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Catch all repository for FPGA learning/testing

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Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
rtl		rtl
tb		tb
Makefile		Makefile
README.md		README.md

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README

This project is a soft introduction to digital design and FPGA development.

Directories

rtl: contains the synthesizable code of the project
tb: Testbench directory, contains verif environment
syn: Tool dependant synthesis scripts and constraints
examples: Board dependant projects
lib: Device abstraction code
scripts: Scripts.... whenever it will be required

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Catch all repository for FPGA learning/testing

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Verilog 96.7%
Makefile 3.3%