syntheseprojekt

Copyright notice:

• yosys -- Yosys Open SYnthesis Suite
• Copyright (C) 2012 Clifford Wolf [email protected]

This project is about the reverse engineering of Yosys, an open-source tool for digital synthesis, for educational use.

Milestones: -Verilog Lexer (done) -Verilog Parser (done) -AST Structure (halfway done) -AST to internal RTLIL format (in progress)