Merge branch 'main' into 0.6-release

.github/workflows/setup-oss-cad-suite/action.yml

@@ -0,0 +1,27 @@
+name: Setup OSS CAD Suite
+
+inputs:
+  osscadsuite-version:
+    description: 'version to install'
+    required: true
+
+runs:
+  using: composite
+  steps:
+    - id: cache-oss-cad-suite
+      uses: actions/cache@v3
+      with:
+        path: oss-cad-suite
+        key: oss-cad-suite-${{ runner.os }}-${{ inputs.osscadsuite-version }}
+
+    - shell: bash
+      if: steps.cache-oss-cad-suite.outputs.cache-hit != 'true'
+      run: |
+        VERSION=${{ inputs.osscadsuite-version }}
+        ARTIFACT=oss-cad-suite-linux-x64-$(echo $VERSION | tr -d '-')
+        wget -q -O - https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${VERSION}/${ARTIFACT}.tgz | tar -zx
+
+    # Add the CAD Suite to the PATH
+    - shell: bash
+      run: echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH
+

.github/workflows/test.yml

@@ -117,9 +117,9 @@ jobs:
           z3 --version
           cvc4 --version
       - name: Install Tabby OSS Cad Suite (from YosysHQ)
-        uses: YosysHQ/setup-oss-cad-suite@v1
+        uses: ./.github/workflows/setup-oss-cad-suite
         with:
-          osscadsuite-version: '2022-08-18'
+          osscadsuite-version: '2023-01-09'
       - name: Test
         run: sbt "testOnly -- -n Formal -Dformal_engine=${{ matrix.backend }}"
 
@@ -148,21 +148,34 @@ jobs:
       - name: Check Formatting
         run: sbt scalafmtCheckAll
 
+  no-warn:
+    name: No Warnings with Scala 2.13 for PRs
+    if: github.event_name == 'pull_request'
+    runs-on: ubuntu-20.04
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Check for Warnings
+        run: sbt "set ThisBuild / scalacOptions ++= Seq(\"-Xfatal-warnings\") ; compile"
+      - name: Check for Warnings in Tests
+        run: sbt "set ThisBuild / scalacOptions ++= Seq(\"-Xfatal-warnings\") ; Test / compile"
+
   # Sentinel job to simplify how we specify which checks need to pass in branch
   # protection and in Mergify
   #
   # When adding new jobs, please add them to `needs` below
   all_tests_passed:
     name: "all tests passed"
-    needs: [test, doc, verilator, formal, formal-mac, icarus, test-mac]
+    needs: [test, doc, verilator, formal, formal-mac, icarus, test-mac, no-warn]
     runs-on: ubuntu-latest
     steps:
       - run: echo Success!
 
   # sbt ci-release publishes all cross versions so this job needs to be
   # separate from a Scala versions build matrix to avoid duplicate publishing
   publish:
-    needs: [all_tests_passed]
+    # note: we do not require a warning check for publishing!
+    needs: [test, doc, verilator, formal, formal-mac, icarus, test-mac]
     runs-on: ubuntu-20.04
     if: github.event_name == 'push'
 

build.sbt

@@ -58,7 +58,23 @@ scalacOptions ++= Seq(
   "-deprecation",
   "-feature",
   "-Xcheckinit",
-  "-Wconf:msg=firrtl:s", // do not warn about firrtl imports
+  // do not warn about firrtl imports, once the firrtl repo is removed, we will need to import the code
+  "-Wconf:cat=deprecation&msg=Importing from firrtl is deprecated:s",
+  // do not warn about firrtl deprecations
+  "-Wconf:cat=deprecation&msg=will not be supported as part of the migration to the MLIR-based FIRRTL Compiler:s",
+  // TODO: remove FixedPoint support after 3.6 release
+  "-Wconf:cat=deprecation&msg=class FixedPoint:s",
+  "-Wconf:cat=deprecation&msg=class BinaryPoint:s",
+  "-Wconf:cat=deprecation&msg=object FixedPoint:s",
+  "-Wconf:cat=deprecation&msg=class fromDoubleToLiteral:s",
+  "-Wconf:cat=deprecation&msg=class fromBigDecimalToLiteral:s",
+  "-Wconf:cat=deprecation&msg=trait HasBinaryPoint:s",
+  "-Wconf:cat=deprecation&msg=object UnknownBinaryPoint:s",
+  // TODO: remove Interval support after 3.6 release
+  "-Wconf:cat=deprecation&msg=class Interval:s",
+  "-Wconf:cat=deprecation&msg=object Interval:s",
+  "-Wconf:cat=deprecation&msg=class fromBigDecimalToLiteralInterval:s",
+  "-Wconf:cat=deprecation&msg=class fromBigIntToLiteralInterval:s"
 ) ++ {
   CrossVersion.partialVersion(scalaVersion.value) match {
     case Some((2, n)) if n >= 13 => Seq("-Ymacro-annotations")
@@ -69,9 +85,9 @@ scalacOptions ++= Seq(
 libraryDependencies ++= Seq(
   "edu.berkeley.cs" %% "chisel3" % defaultVersions("chisel3"),
   "edu.berkeley.cs" %% "treadle" % defaultVersions("treadle"),
-  "org.scalatest" %% "scalatest" % "3.2.14",
+  "org.scalatest" %% "scalatest" % "3.2.15",
   "com.lihaoyi" %% "utest" % "0.8.1",
-  "net.java.dev.jna" % "jna" % "5.12.1",
+  "net.java.dev.jna" % "jna" % "5.13.0",
   "org.scala-lang" % "scala-reflect" % scalaVersion.value,
   compilerPlugin(("edu.berkeley.cs" % "chisel3-plugin" % defaultVersions("chisel3")).cross(CrossVersion.full))
 ) ++ {

build.sc

@@ -71,9 +71,9 @@ class chiseltestCrossModule(val crossScalaVersion: String)
 
   override def ivyDeps = T {
     Agg(
-      ivy"org.scalatest::scalatest:3.2.14",
+      ivy"org.scalatest::scalatest:3.2.15",
       ivy"com.lihaoyi::utest:0.8.1",
-      ivy"net.java.dev.jna:jna:5.12.1"
+      ivy"net.java.dev.jna:jna:5.13.0"
     ) ++ chisel3IvyDeps ++ treadleIvyDeps
   }
 

project/build.properties

@@ -1 +1 @@
-sbt.version=1.8.0
+sbt.version=1.8.2

src/main/scala/chisel3/internaltest/EnumHelpers.scala

@@ -2,7 +2,7 @@
 
 package chisel3.internaltest
 
-import chisel3.experimental.EnumType
+import chisel3.EnumType
 
 /** Helper functions to allow for peeks and better debugging of ChiselEnums.
   * This needs to be in a `chisel3` package in order to access the package private

src/main/scala/chiseltest/experimental/UncheckedClockPoke.scala

@@ -5,7 +5,8 @@ package chiseltest.experimental
 import chiseltest.UnpokeableException
 import chiseltest.internal.Context
 import chisel3._
-import chisel3.experimental.{DataMirror, Direction}
+import chisel3.reflect._
+import chisel3.experimental.Direction
 
 package object UncheckedClockPoke {
 

src/main/scala/chiseltest/internal/BackendExecutive.scala

@@ -2,7 +2,8 @@
 
 package chiseltest.internal
 
-import chisel3.experimental.{BaseModule, DataMirror}
+import chisel3.experimental.BaseModule
+import chisel3.reflect.DataMirror
 import chisel3.{Data, Element, Module, Record, Vec}
 import chiseltest.coverage.Coverage
 import chiseltest.simulator.{Compiler, DebugPrintWrapper, Simulator}

src/main/scala/chiseltest/internal/PeekPokeTesterBackend.scala

@@ -1,7 +1,7 @@
 package chiseltest.internal
 
 import chisel3._
-import chisel3.experimental.DataMirror
+import chisel3.reflect.DataMirror
 import chiseltest.defaults
 import chiseltest.iotesters.PeekPokeTester
 import chiseltest.simulator.SimulatorContext

src/main/scala/chiseltest/iotesters/PeekPokeTester.scala

@@ -1,18 +1,14 @@
 package chiseltest.iotesters
 
 import chisel3._
-import chisel3.experimental._
+import chisel3.experimental.{FixedPoint, Interval}
 import chisel3.internal.firrtl.KnownBinaryPoint
-import chiseltest.ChiselAssertionError
-import chiseltest.internal.{Context, FailedExpectException}
 import chiseltest.simulator.SimulatorContext
 import logger.LazyLogging
-import org.scalatest.exceptions.TestFailedException
 
 import scala.collection.immutable
 import scala.collection.mutable
 import scala.language.implicitConversions
-import scala.util.Random
 import scala.annotation.{implicitNotFound, tailrec}
 
 // A typeclass that defines the types we can poke, peek, or expect from

src/main/scala/chiseltest/package.scala

@@ -3,7 +3,8 @@
 import scala.language.implicitConversions
 import chiseltest.internal._
 import chisel3._
-import chisel3.experimental.{DataMirror, Direction, EnumType, FixedPoint, Interval}
+import chisel3.experimental.{Direction, FixedPoint, Interval}
+import chisel3.reflect.DataMirror
 import chisel3.experimental.BundleLiterals._
 import chisel3.experimental.VecLiterals._
 import chisel3.internal.firrtl.KnownBinaryPoint
@@ -45,40 +46,64 @@ package object chiseltest {
 
   /** allows access to chisel UInt type signals with Scala native values */
   implicit class testableUInt(x: UInt) {
+    private def isZeroWidth = x.widthOption.contains(0)
     def poke(value: UInt): Unit = poke(value.litValue)
     def poke(value: BigInt): Unit = {
       Utils.ensureFits(x, value)
-      Utils.pokeBits(x, value)
+      if (!isZeroWidth) { // poking a zero width value is a no-op
+        Utils.pokeBits(x, value)
+      }
     }
     private[chiseltest] def expectInternal(value: BigInt, message: Option[() => String]): Unit = {
       Utils.ensureFits(x, value)
-      Utils.expectBits(x, value, message, None)
+      if (!isZeroWidth) { // zero width UInts always have the value 0
+        Utils.expectBits(x, value, message, None)
+      }
     }
     def expect(value: UInt): Unit = expectInternal(value.litValue, None)
     def expect(value: UInt, message: => String): Unit = expectInternal(value.litValue, Some(() => message))
     def expect(value: BigInt): Unit = expectInternal(value, None)
     def expect(value: BigInt, message: => String): Unit = expectInternal(value, Some(() => message))
-    def peek():    UInt = Context().backend.peekBits(x).asUInt(DataMirror.widthOf(x))
-    def peekInt(): BigInt = Context().backend.peekBits(x)
+    def peekInt(): BigInt = if (!isZeroWidth) { Context().backend.peekBits(x) }
+    else {
+      // zero width UInts always have the value 0
+      0
+    }
+    def peek(): UInt = if (!isZeroWidth) { peekInt().asUInt(DataMirror.widthOf(x)) }
+    else {
+      0.U // TODO: change to 0-width constant once supported: https://github.com/chipsalliance/chisel3/pull/2932
+    }
   }
 
   /** allows access to chisel SInt type signals with Scala native values */
   implicit class testableSInt(x: SInt) {
+    private def isZeroWidth = x.widthOption.contains(0)
     def poke(value: SInt): Unit = poke(value.litValue)
     def poke(value: BigInt): Unit = {
       Utils.ensureFits(x, value)
-      Utils.pokeBits(x, value)
+      if (!isZeroWidth) { // poking a zero width value is a no-op
+        Utils.pokeBits(x, value)
+      }
     }
     private[chiseltest] def expectInternal(value: BigInt, message: Option[() => String]): Unit = {
       Utils.ensureFits(x, value)
-      Utils.expectBits(x, value, message, None)
+      if (!isZeroWidth) { // zero width UInts always have the value 0
+        Utils.expectBits(x, value, message, None)
+      }
     }
     def expect(value: SInt): Unit = expectInternal(value.litValue, None)
     def expect(value: SInt, message: => String): Unit = expectInternal(value.litValue, Some(() => message))
     def expect(value: BigInt): Unit = expectInternal(value, None)
     def expect(value: BigInt, message: => String): Unit = expectInternal(value, Some(() => message))
-    def peek():    SInt = Context().backend.peekBits(x).asSInt(DataMirror.widthOf(x))
-    def peekInt(): BigInt = Context().backend.peekBits(x)
+    def peekInt(): BigInt = if (!isZeroWidth) { Context().backend.peekBits(x) }
+    else {
+      // zero width UInts always have the value 0
+      0
+    }
+    def peek(): SInt = if (!isZeroWidth) { peekInt().asSInt(DataMirror.widthOf(x)) }
+    else {
+      0.S // TODO: change to 0-width constant once supported: https://github.com/chipsalliance/chisel3/pull/2932
+    }
   }
 
   /** allows access to chisel Interval type signals with Scala native values */
@@ -242,9 +267,14 @@ package object chiseltest {
         case _: Vec[_] | _: Record => false
         case _ => true
       }
+      val isZeroWidthInt = value match {
+        case v: Bits if v.widthOption.contains(0) => true
+        case _ => false
+      }
       // if we are dealing with a ground type non-literal, this is only allowed if we are doing a partial poke/expect
       if (isGroundType && !value.isLit) {
-        if (allowPartial) { true }
+        // zero-width integers do not carry a value and thus are allowed to be DontCare
+        if (allowPartial || isZeroWidthInt) { true }
         else {
           throw new NonLiteralValueError(value, x, op)
         }
@@ -376,6 +406,8 @@ package object chiseltest {
     // Throw an exception if the value cannot fit into the signal.
     def ensureFits(signal: SInt, value: BigInt): Unit = {
       signal.widthOption match {
+        case Some(0) => // special case: 0-width SInts always represent 0
+          ensureInRange(signal, value, 0, 0)
         case Some(w) =>
           val m = BigInt(1) << (w - 1)
           ensureInRange(signal, value, -m, m - 1)

src/main/scala/chiseltest/simulator/IcarusSimulator.scala

@@ -7,12 +7,13 @@ import firrtl.options.Dependency
 import firrtl.stage.RunFirrtlTransformAnnotation
 import firrtl.transforms.formal.RemoveVerificationStatements
 import firrtl.{AnnotationSeq, CircuitState}
+import logger.LazyLogging
 
 case object IcarusBackendAnnotation extends SimulatorAnnotation {
   override def getSimulator: Simulator = IcarusSimulator
 }
 
-private object IcarusSimulator extends Simulator {
+private object IcarusSimulator extends Simulator with LazyLogging {
   override def name: String = "iverilog"
 
   /** is this simulator installed on the local machine? */
@@ -58,9 +59,12 @@ private object IcarusSimulator extends Simulator {
     val targetDir = Compiler.requireTargetDir(state.annotations)
     val toplevel = TopmoduleInfo(state.circuit)
 
+    // show verbose messages
+    val verbose = state.annotations.contains(SimulatorDebugAnnotation)
+
     // Create the VPI files that icarus needs + a custom harness
     val moduleNames = GetModuleNames(state.circuit)
-    val compileDir = makeCompileDir(targetDir)
+    val compileDir = makeCompileDir(targetDir, verbose)
     val verilogHarness = generateHarness(compileDir, toplevel, moduleNames)
 
     // Compile VPI code
@@ -69,8 +73,10 @@ private object IcarusSimulator extends Simulator {
     // compile low firrtl to System Verilog for verilator to use
     val passes = if (majorVersion >= 11) { Seq() }
     else {
-      println("WARN: Icarus Verilog only supports chisel's assert/assume/cover statements starting with version 11.")
-      println(
+      logger.warn(
+        "WARN: Icarus Verilog only supports chisel's assert/assume/cover statements starting with version 11."
+      )
+      logger.warn(
         s"      You are using version ${majorVersion}.${minorVersion} and we are going to remove all unsupported statements."
       )
       Seq(RunFirrtlTransformAnnotation(Dependency[RemoveVerificationStatements]))
@@ -83,13 +89,14 @@ private object IcarusSimulator extends Simulator {
       getSimulatorArgs(state)
 
     // the binary we created communicates using our standard IPC interface
-    new IPCSimulatorContext(simCmd, toplevel, IcarusSimulator)
+    new IPCSimulatorContext(simCmd, toplevel, IcarusSimulator, verbose)
   }
 
-  private def makeCompileDir(targetDir: os.Path): os.Path = {
+  private def makeCompileDir(targetDir: os.Path, verbose: Boolean): os.Path = {
     val compileDir = targetDir / "icarus"
     if (os.exists(compileDir)) {
-      println(s"Deleting stale Icarus Verilog object directory: $compileDir")
+      if (verbose)
+        println(s"Deleting stale Icarus Verilog object directory: $compileDir")
       os.remove.all(compileDir)
     }
     os.makeDir(compileDir)

src/main/scala/chiseltest/simulator/VcsSimulator.scala

@@ -96,8 +96,11 @@ private object VcsSimulator extends Simulator {
       userSimFlags ++
       waveformFlags(targetDir, toplevel.name, state.annotations)
 
+    // show verbose debug messages
+    val verbose = state.annotations.contains(SimulatorDebugAnnotation)
+
     // the binary we created communicates using our standard IPC interface
-    new IPCSimulatorContext(simCmd, toplevel, VcsSimulator)
+    new IPCSimulatorContext(simCmd, toplevel, VcsSimulator, verbose)
   }
 
   private def waveformFlags(targetDir: os.Path, topName: String, annos: AnnotationSeq): Seq[String] = {